1 /* 2 * 3 * Intel Management Engine Interface (Intel MEI) Linux driver 4 * Copyright (c) 2003-2012, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 */ 16 17 18 19 #ifndef _MEI_INTERFACE_H_ 20 #define _MEI_INTERFACE_H_ 21 22 #include <linux/irqreturn.h> 23 #include <linux/pci.h> 24 #include <linux/mei.h> 25 26 #include "mei_dev.h" 27 #include "client.h" 28 29 /* 30 * mei_cfg - mei device configuration 31 * 32 * @fw_status: FW status 33 * @quirk_probe: device exclusion quirk 34 */ 35 struct mei_cfg { 36 const struct mei_fw_status fw_status; 37 bool (*quirk_probe)(struct pci_dev *pdev); 38 }; 39 40 41 #define MEI_PCI_DEVICE(dev, cfg) \ 42 .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \ 43 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ 44 .driver_data = (kernel_ulong_t)(cfg), 45 46 #define MEI_ME_RPM_TIMEOUT 500 /* ms */ 47 48 /** 49 * struct mei_me_hw - me hw specific data 50 * 51 * @cfg: per device generation config and ops 52 * @mem_addr: io memory address 53 * @pg_state: power gating state 54 * @d0i3_supported: di03 support 55 */ 56 struct mei_me_hw { 57 const struct mei_cfg *cfg; 58 void __iomem *mem_addr; 59 enum mei_pg_state pg_state; 60 bool d0i3_supported; 61 }; 62 63 #define to_me_hw(dev) (struct mei_me_hw *)((dev)->hw) 64 65 /** 66 * enum mei_cfg_idx - indices to platform specific configurations. 67 * 68 * Note: has to be synchronized with mei_cfg_list[] 69 * 70 * @MEI_ME_UNDEF_CFG: Lower sentinel. 71 * @MEI_ME_ICH_CFG: I/O Controller Hub legacy devices. 72 * @MEI_ME_ICH10_CFG: I/O Controller Hub platforms Gen10 73 * @MEI_ME_PCH_CFG: Platform Controller Hub platforms (Up to Gen8). 74 * @MEI_ME_PCH_CPT_PBG_CFG:Platform Controller Hub workstations 75 * with quirk for Node Manager exclusion. 76 * @MEI_ME_PCH8_CFG: Platform Controller Hub Gen8 and newer 77 * client platforms. 78 * @MEI_ME_PCH8_SPS_CFG: Platform Controller Hub Gen8 and newer 79 * servers platforms with quirk for 80 * SPS firmware exclusion. 81 * @MEI_ME_NUM_CFG: Upper Sentinel. 82 */ 83 enum mei_cfg_idx { 84 MEI_ME_UNDEF_CFG, 85 MEI_ME_ICH_CFG, 86 MEI_ME_ICH10_CFG, 87 MEI_ME_PCH_CFG, 88 MEI_ME_PCH_CPT_PBG_CFG, 89 MEI_ME_PCH8_CFG, 90 MEI_ME_PCH8_SPS_CFG, 91 MEI_ME_NUM_CFG, 92 }; 93 94 const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx); 95 96 struct mei_device *mei_me_dev_init(struct pci_dev *pdev, 97 const struct mei_cfg *cfg); 98 99 int mei_me_pg_enter_sync(struct mei_device *dev); 100 int mei_me_pg_exit_sync(struct mei_device *dev); 101 102 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id); 103 irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id); 104 105 #endif /* _MEI_INTERFACE_H_ */ 106