1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2012-2018, Intel Corporation. All rights reserved. 4 * Intel Management Engine Interface (Intel MEI) Linux driver 5 */ 6 7 #ifndef _MEI_INTERFACE_H_ 8 #define _MEI_INTERFACE_H_ 9 10 #include <linux/irqreturn.h> 11 #include <linux/pci.h> 12 #include <linux/mei.h> 13 14 #include "mei_dev.h" 15 #include "client.h" 16 17 /* 18 * mei_cfg - mei device configuration 19 * 20 * @fw_status: FW status 21 * @quirk_probe: device exclusion quirk 22 * @dma_size: device DMA buffers size 23 */ 24 struct mei_cfg { 25 const struct mei_fw_status fw_status; 26 bool (*quirk_probe)(struct pci_dev *pdev); 27 size_t dma_size[DMA_DSCR_NUM]; 28 }; 29 30 31 #define MEI_PCI_DEVICE(dev, cfg) \ 32 .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \ 33 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ 34 .driver_data = (kernel_ulong_t)(cfg), 35 36 #define MEI_ME_RPM_TIMEOUT 500 /* ms */ 37 38 /** 39 * struct mei_me_hw - me hw specific data 40 * 41 * @cfg: per device generation config and ops 42 * @mem_addr: io memory address 43 * @pg_state: power gating state 44 * @d0i3_supported: di03 support 45 * @hbuf_depth: depth of hardware host/write buffer in slots 46 */ 47 struct mei_me_hw { 48 const struct mei_cfg *cfg; 49 void __iomem *mem_addr; 50 enum mei_pg_state pg_state; 51 bool d0i3_supported; 52 u8 hbuf_depth; 53 }; 54 55 #define to_me_hw(dev) (struct mei_me_hw *)((dev)->hw) 56 57 /** 58 * enum mei_cfg_idx - indices to platform specific configurations. 59 * 60 * Note: has to be synchronized with mei_cfg_list[] 61 * 62 * @MEI_ME_UNDEF_CFG: Lower sentinel. 63 * @MEI_ME_ICH_CFG: I/O Controller Hub legacy devices. 64 * @MEI_ME_ICH10_CFG: I/O Controller Hub platforms Gen10 65 * @MEI_ME_PCH_CFG: Platform Controller Hub platforms (Up to Gen8). 66 * @MEI_ME_PCH_CPT_PBG_CFG:Platform Controller Hub workstations 67 * with quirk for Node Manager exclusion. 68 * @MEI_ME_PCH8_CFG: Platform Controller Hub Gen8 and newer 69 * client platforms. 70 * @MEI_ME_PCH8_SPS_CFG: Platform Controller Hub Gen8 and newer 71 * servers platforms with quirk for 72 * SPS firmware exclusion. 73 * @MEI_ME_PCH12_CFG: Platform Controller Hub Gen12 and newer 74 * @MEI_ME_NUM_CFG: Upper Sentinel. 75 */ 76 enum mei_cfg_idx { 77 MEI_ME_UNDEF_CFG, 78 MEI_ME_ICH_CFG, 79 MEI_ME_ICH10_CFG, 80 MEI_ME_PCH_CFG, 81 MEI_ME_PCH_CPT_PBG_CFG, 82 MEI_ME_PCH8_CFG, 83 MEI_ME_PCH8_SPS_CFG, 84 MEI_ME_PCH12_CFG, 85 MEI_ME_NUM_CFG, 86 }; 87 88 const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx); 89 90 struct mei_device *mei_me_dev_init(struct pci_dev *pdev, 91 const struct mei_cfg *cfg); 92 93 int mei_me_pg_enter_sync(struct mei_device *dev); 94 int mei_me_pg_exit_sync(struct mei_device *dev); 95 96 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id); 97 irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id); 98 99 #endif /* _MEI_INTERFACE_H_ */ 100