xref: /openbmc/linux/drivers/misc/mei/hw-me.c (revision f220d3eb)
1 /*
2  *
3  * Intel Management Engine Interface (Intel MEI) Linux driver
4  * Copyright (c) 2003-2012, Intel Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  */
16 
17 #include <linux/pci.h>
18 
19 #include <linux/kthread.h>
20 #include <linux/interrupt.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/sizes.h>
23 
24 #include "mei_dev.h"
25 #include "hbm.h"
26 
27 #include "hw-me.h"
28 #include "hw-me-regs.h"
29 
30 #include "mei-trace.h"
31 
32 /**
33  * mei_me_reg_read - Reads 32bit data from the mei device
34  *
35  * @hw: the me hardware structure
36  * @offset: offset from which to read the data
37  *
38  * Return: register value (u32)
39  */
40 static inline u32 mei_me_reg_read(const struct mei_me_hw *hw,
41 			       unsigned long offset)
42 {
43 	return ioread32(hw->mem_addr + offset);
44 }
45 
46 
47 /**
48  * mei_me_reg_write - Writes 32bit data to the mei device
49  *
50  * @hw: the me hardware structure
51  * @offset: offset from which to write the data
52  * @value: register value to write (u32)
53  */
54 static inline void mei_me_reg_write(const struct mei_me_hw *hw,
55 				 unsigned long offset, u32 value)
56 {
57 	iowrite32(value, hw->mem_addr + offset);
58 }
59 
60 /**
61  * mei_me_mecbrw_read - Reads 32bit data from ME circular buffer
62  *  read window register
63  *
64  * @dev: the device structure
65  *
66  * Return: ME_CB_RW register value (u32)
67  */
68 static inline u32 mei_me_mecbrw_read(const struct mei_device *dev)
69 {
70 	return mei_me_reg_read(to_me_hw(dev), ME_CB_RW);
71 }
72 
73 /**
74  * mei_me_hcbww_write - write 32bit data to the host circular buffer
75  *
76  * @dev: the device structure
77  * @data: 32bit data to be written to the host circular buffer
78  */
79 static inline void mei_me_hcbww_write(struct mei_device *dev, u32 data)
80 {
81 	mei_me_reg_write(to_me_hw(dev), H_CB_WW, data);
82 }
83 
84 /**
85  * mei_me_mecsr_read - Reads 32bit data from the ME CSR
86  *
87  * @dev: the device structure
88  *
89  * Return: ME_CSR_HA register value (u32)
90  */
91 static inline u32 mei_me_mecsr_read(const struct mei_device *dev)
92 {
93 	u32 reg;
94 
95 	reg = mei_me_reg_read(to_me_hw(dev), ME_CSR_HA);
96 	trace_mei_reg_read(dev->dev, "ME_CSR_HA", ME_CSR_HA, reg);
97 
98 	return reg;
99 }
100 
101 /**
102  * mei_hcsr_read - Reads 32bit data from the host CSR
103  *
104  * @dev: the device structure
105  *
106  * Return: H_CSR register value (u32)
107  */
108 static inline u32 mei_hcsr_read(const struct mei_device *dev)
109 {
110 	u32 reg;
111 
112 	reg = mei_me_reg_read(to_me_hw(dev), H_CSR);
113 	trace_mei_reg_read(dev->dev, "H_CSR", H_CSR, reg);
114 
115 	return reg;
116 }
117 
118 /**
119  * mei_hcsr_write - writes H_CSR register to the mei device
120  *
121  * @dev: the device structure
122  * @reg: new register value
123  */
124 static inline void mei_hcsr_write(struct mei_device *dev, u32 reg)
125 {
126 	trace_mei_reg_write(dev->dev, "H_CSR", H_CSR, reg);
127 	mei_me_reg_write(to_me_hw(dev), H_CSR, reg);
128 }
129 
130 /**
131  * mei_hcsr_set - writes H_CSR register to the mei device,
132  * and ignores the H_IS bit for it is write-one-to-zero.
133  *
134  * @dev: the device structure
135  * @reg: new register value
136  */
137 static inline void mei_hcsr_set(struct mei_device *dev, u32 reg)
138 {
139 	reg &= ~H_CSR_IS_MASK;
140 	mei_hcsr_write(dev, reg);
141 }
142 
143 /**
144  * mei_hcsr_set_hig - set host interrupt (set H_IG)
145  *
146  * @dev: the device structure
147  */
148 static inline void mei_hcsr_set_hig(struct mei_device *dev)
149 {
150 	u32 hcsr;
151 
152 	hcsr = mei_hcsr_read(dev) | H_IG;
153 	mei_hcsr_set(dev, hcsr);
154 }
155 
156 /**
157  * mei_me_d0i3c_read - Reads 32bit data from the D0I3C register
158  *
159  * @dev: the device structure
160  *
161  * Return: H_D0I3C register value (u32)
162  */
163 static inline u32 mei_me_d0i3c_read(const struct mei_device *dev)
164 {
165 	u32 reg;
166 
167 	reg = mei_me_reg_read(to_me_hw(dev), H_D0I3C);
168 	trace_mei_reg_read(dev->dev, "H_D0I3C", H_D0I3C, reg);
169 
170 	return reg;
171 }
172 
173 /**
174  * mei_me_d0i3c_write - writes H_D0I3C register to device
175  *
176  * @dev: the device structure
177  * @reg: new register value
178  */
179 static inline void mei_me_d0i3c_write(struct mei_device *dev, u32 reg)
180 {
181 	trace_mei_reg_write(dev->dev, "H_D0I3C", H_D0I3C, reg);
182 	mei_me_reg_write(to_me_hw(dev), H_D0I3C, reg);
183 }
184 
185 /**
186  * mei_me_fw_status - read fw status register from pci config space
187  *
188  * @dev: mei device
189  * @fw_status: fw status register values
190  *
191  * Return: 0 on success, error otherwise
192  */
193 static int mei_me_fw_status(struct mei_device *dev,
194 			    struct mei_fw_status *fw_status)
195 {
196 	struct pci_dev *pdev = to_pci_dev(dev->dev);
197 	struct mei_me_hw *hw = to_me_hw(dev);
198 	const struct mei_fw_status *fw_src = &hw->cfg->fw_status;
199 	int ret;
200 	int i;
201 
202 	if (!fw_status)
203 		return -EINVAL;
204 
205 	fw_status->count = fw_src->count;
206 	for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) {
207 		ret = pci_read_config_dword(pdev, fw_src->status[i],
208 					    &fw_status->status[i]);
209 		trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HSF_X",
210 				       fw_src->status[i],
211 				       fw_status->status[i]);
212 		if (ret)
213 			return ret;
214 	}
215 
216 	return 0;
217 }
218 
219 /**
220  * mei_me_hw_config - configure hw dependent settings
221  *
222  * @dev: mei device
223  */
224 static void mei_me_hw_config(struct mei_device *dev)
225 {
226 	struct pci_dev *pdev = to_pci_dev(dev->dev);
227 	struct mei_me_hw *hw = to_me_hw(dev);
228 	u32 hcsr, reg;
229 
230 	/* Doesn't change in runtime */
231 	hcsr = mei_hcsr_read(dev);
232 	hw->hbuf_depth = (hcsr & H_CBD) >> 24;
233 
234 	reg = 0;
235 	pci_read_config_dword(pdev, PCI_CFG_HFS_1, &reg);
236 	trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg);
237 	hw->d0i3_supported =
238 		((reg & PCI_CFG_HFS_1_D0I3_MSK) == PCI_CFG_HFS_1_D0I3_MSK);
239 
240 	hw->pg_state = MEI_PG_OFF;
241 	if (hw->d0i3_supported) {
242 		reg = mei_me_d0i3c_read(dev);
243 		if (reg & H_D0I3C_I3)
244 			hw->pg_state = MEI_PG_ON;
245 	}
246 }
247 
248 /**
249  * mei_me_pg_state  - translate internal pg state
250  *   to the mei power gating state
251  *
252  * @dev:  mei device
253  *
254  * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise
255  */
256 static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev)
257 {
258 	struct mei_me_hw *hw = to_me_hw(dev);
259 
260 	return hw->pg_state;
261 }
262 
263 static inline u32 me_intr_src(u32 hcsr)
264 {
265 	return hcsr & H_CSR_IS_MASK;
266 }
267 
268 /**
269  * me_intr_disable - disables mei device interrupts
270  *      using supplied hcsr register value.
271  *
272  * @dev: the device structure
273  * @hcsr: supplied hcsr register value
274  */
275 static inline void me_intr_disable(struct mei_device *dev, u32 hcsr)
276 {
277 	hcsr &= ~H_CSR_IE_MASK;
278 	mei_hcsr_set(dev, hcsr);
279 }
280 
281 /**
282  * mei_me_intr_clear - clear and stop interrupts
283  *
284  * @dev: the device structure
285  * @hcsr: supplied hcsr register value
286  */
287 static inline void me_intr_clear(struct mei_device *dev, u32 hcsr)
288 {
289 	if (me_intr_src(hcsr))
290 		mei_hcsr_write(dev, hcsr);
291 }
292 
293 /**
294  * mei_me_intr_clear - clear and stop interrupts
295  *
296  * @dev: the device structure
297  */
298 static void mei_me_intr_clear(struct mei_device *dev)
299 {
300 	u32 hcsr = mei_hcsr_read(dev);
301 
302 	me_intr_clear(dev, hcsr);
303 }
304 /**
305  * mei_me_intr_enable - enables mei device interrupts
306  *
307  * @dev: the device structure
308  */
309 static void mei_me_intr_enable(struct mei_device *dev)
310 {
311 	u32 hcsr = mei_hcsr_read(dev);
312 
313 	hcsr |= H_CSR_IE_MASK;
314 	mei_hcsr_set(dev, hcsr);
315 }
316 
317 /**
318  * mei_me_intr_disable - disables mei device interrupts
319  *
320  * @dev: the device structure
321  */
322 static void mei_me_intr_disable(struct mei_device *dev)
323 {
324 	u32 hcsr = mei_hcsr_read(dev);
325 
326 	me_intr_disable(dev, hcsr);
327 }
328 
329 /**
330  * mei_me_synchronize_irq - wait for pending IRQ handlers
331  *
332  * @dev: the device structure
333  */
334 static void mei_me_synchronize_irq(struct mei_device *dev)
335 {
336 	struct pci_dev *pdev = to_pci_dev(dev->dev);
337 
338 	synchronize_irq(pdev->irq);
339 }
340 
341 /**
342  * mei_me_hw_reset_release - release device from the reset
343  *
344  * @dev: the device structure
345  */
346 static void mei_me_hw_reset_release(struct mei_device *dev)
347 {
348 	u32 hcsr = mei_hcsr_read(dev);
349 
350 	hcsr |= H_IG;
351 	hcsr &= ~H_RST;
352 	mei_hcsr_set(dev, hcsr);
353 
354 	/* complete this write before we set host ready on another CPU */
355 	mmiowb();
356 }
357 
358 /**
359  * mei_me_host_set_ready - enable device
360  *
361  * @dev: mei device
362  */
363 static void mei_me_host_set_ready(struct mei_device *dev)
364 {
365 	u32 hcsr = mei_hcsr_read(dev);
366 
367 	hcsr |= H_CSR_IE_MASK | H_IG | H_RDY;
368 	mei_hcsr_set(dev, hcsr);
369 }
370 
371 /**
372  * mei_me_host_is_ready - check whether the host has turned ready
373  *
374  * @dev: mei device
375  * Return: bool
376  */
377 static bool mei_me_host_is_ready(struct mei_device *dev)
378 {
379 	u32 hcsr = mei_hcsr_read(dev);
380 
381 	return (hcsr & H_RDY) == H_RDY;
382 }
383 
384 /**
385  * mei_me_hw_is_ready - check whether the me(hw) has turned ready
386  *
387  * @dev: mei device
388  * Return: bool
389  */
390 static bool mei_me_hw_is_ready(struct mei_device *dev)
391 {
392 	u32 mecsr = mei_me_mecsr_read(dev);
393 
394 	return (mecsr & ME_RDY_HRA) == ME_RDY_HRA;
395 }
396 
397 /**
398  * mei_me_hw_is_resetting - check whether the me(hw) is in reset
399  *
400  * @dev: mei device
401  * Return: bool
402  */
403 static bool mei_me_hw_is_resetting(struct mei_device *dev)
404 {
405 	u32 mecsr = mei_me_mecsr_read(dev);
406 
407 	return (mecsr & ME_RST_HRA) == ME_RST_HRA;
408 }
409 
410 /**
411  * mei_me_hw_ready_wait - wait until the me(hw) has turned ready
412  *  or timeout is reached
413  *
414  * @dev: mei device
415  * Return: 0 on success, error otherwise
416  */
417 static int mei_me_hw_ready_wait(struct mei_device *dev)
418 {
419 	mutex_unlock(&dev->device_lock);
420 	wait_event_timeout(dev->wait_hw_ready,
421 			dev->recvd_hw_ready,
422 			mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT));
423 	mutex_lock(&dev->device_lock);
424 	if (!dev->recvd_hw_ready) {
425 		dev_err(dev->dev, "wait hw ready failed\n");
426 		return -ETIME;
427 	}
428 
429 	mei_me_hw_reset_release(dev);
430 	dev->recvd_hw_ready = false;
431 	return 0;
432 }
433 
434 /**
435  * mei_me_hw_start - hw start routine
436  *
437  * @dev: mei device
438  * Return: 0 on success, error otherwise
439  */
440 static int mei_me_hw_start(struct mei_device *dev)
441 {
442 	int ret = mei_me_hw_ready_wait(dev);
443 
444 	if (ret)
445 		return ret;
446 	dev_dbg(dev->dev, "hw is ready\n");
447 
448 	mei_me_host_set_ready(dev);
449 	return ret;
450 }
451 
452 
453 /**
454  * mei_hbuf_filled_slots - gets number of device filled buffer slots
455  *
456  * @dev: the device structure
457  *
458  * Return: number of filled slots
459  */
460 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev)
461 {
462 	u32 hcsr;
463 	char read_ptr, write_ptr;
464 
465 	hcsr = mei_hcsr_read(dev);
466 
467 	read_ptr = (char) ((hcsr & H_CBRP) >> 8);
468 	write_ptr = (char) ((hcsr & H_CBWP) >> 16);
469 
470 	return (unsigned char) (write_ptr - read_ptr);
471 }
472 
473 /**
474  * mei_me_hbuf_is_empty - checks if host buffer is empty.
475  *
476  * @dev: the device structure
477  *
478  * Return: true if empty, false - otherwise.
479  */
480 static bool mei_me_hbuf_is_empty(struct mei_device *dev)
481 {
482 	return mei_hbuf_filled_slots(dev) == 0;
483 }
484 
485 /**
486  * mei_me_hbuf_empty_slots - counts write empty slots.
487  *
488  * @dev: the device structure
489  *
490  * Return: -EOVERFLOW if overflow, otherwise empty slots count
491  */
492 static int mei_me_hbuf_empty_slots(struct mei_device *dev)
493 {
494 	struct mei_me_hw *hw = to_me_hw(dev);
495 	unsigned char filled_slots, empty_slots;
496 
497 	filled_slots = mei_hbuf_filled_slots(dev);
498 	empty_slots = hw->hbuf_depth - filled_slots;
499 
500 	/* check for overflow */
501 	if (filled_slots > hw->hbuf_depth)
502 		return -EOVERFLOW;
503 
504 	return empty_slots;
505 }
506 
507 /**
508  * mei_me_hbuf_depth - returns depth of the hw buffer.
509  *
510  * @dev: the device structure
511  *
512  * Return: size of hw buffer in slots
513  */
514 static u32 mei_me_hbuf_depth(const struct mei_device *dev)
515 {
516 	struct mei_me_hw *hw = to_me_hw(dev);
517 
518 	return hw->hbuf_depth;
519 }
520 
521 /**
522  * mei_me_hbuf_write - writes a message to host hw buffer.
523  *
524  * @dev: the device structure
525  * @hdr: header of message
526  * @hdr_len: header length in bytes: must be multiplication of a slot (4bytes)
527  * @data: payload
528  * @data_len: payload length in bytes
529  *
530  * Return: 0 if success, < 0 - otherwise.
531  */
532 static int mei_me_hbuf_write(struct mei_device *dev,
533 			     const void *hdr, size_t hdr_len,
534 			     const void *data, size_t data_len)
535 {
536 	unsigned long rem;
537 	unsigned long i;
538 	const u32 *reg_buf;
539 	u32 dw_cnt;
540 	int empty_slots;
541 
542 	if (WARN_ON(!hdr || !data || hdr_len & 0x3))
543 		return -EINVAL;
544 
545 	dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM((struct mei_msg_hdr *)hdr));
546 
547 	empty_slots = mei_hbuf_empty_slots(dev);
548 	dev_dbg(dev->dev, "empty slots = %hu.\n", empty_slots);
549 
550 	if (empty_slots < 0)
551 		return -EOVERFLOW;
552 
553 	dw_cnt = mei_data2slots(hdr_len + data_len);
554 	if (dw_cnt > (u32)empty_slots)
555 		return -EMSGSIZE;
556 
557 	reg_buf = hdr;
558 	for (i = 0; i < hdr_len / MEI_SLOT_SIZE; i++)
559 		mei_me_hcbww_write(dev, reg_buf[i]);
560 
561 	reg_buf = data;
562 	for (i = 0; i < data_len / MEI_SLOT_SIZE; i++)
563 		mei_me_hcbww_write(dev, reg_buf[i]);
564 
565 	rem = data_len & 0x3;
566 	if (rem > 0) {
567 		u32 reg = 0;
568 
569 		memcpy(&reg, (const u8 *)data + data_len - rem, rem);
570 		mei_me_hcbww_write(dev, reg);
571 	}
572 
573 	mei_hcsr_set_hig(dev);
574 	if (!mei_me_hw_is_ready(dev))
575 		return -EIO;
576 
577 	return 0;
578 }
579 
580 /**
581  * mei_me_count_full_read_slots - counts read full slots.
582  *
583  * @dev: the device structure
584  *
585  * Return: -EOVERFLOW if overflow, otherwise filled slots count
586  */
587 static int mei_me_count_full_read_slots(struct mei_device *dev)
588 {
589 	u32 me_csr;
590 	char read_ptr, write_ptr;
591 	unsigned char buffer_depth, filled_slots;
592 
593 	me_csr = mei_me_mecsr_read(dev);
594 	buffer_depth = (unsigned char)((me_csr & ME_CBD_HRA) >> 24);
595 	read_ptr = (char) ((me_csr & ME_CBRP_HRA) >> 8);
596 	write_ptr = (char) ((me_csr & ME_CBWP_HRA) >> 16);
597 	filled_slots = (unsigned char) (write_ptr - read_ptr);
598 
599 	/* check for overflow */
600 	if (filled_slots > buffer_depth)
601 		return -EOVERFLOW;
602 
603 	dev_dbg(dev->dev, "filled_slots =%08x\n", filled_slots);
604 	return (int)filled_slots;
605 }
606 
607 /**
608  * mei_me_read_slots - reads a message from mei device.
609  *
610  * @dev: the device structure
611  * @buffer: message buffer will be written
612  * @buffer_length: message size will be read
613  *
614  * Return: always 0
615  */
616 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer,
617 			     unsigned long buffer_length)
618 {
619 	u32 *reg_buf = (u32 *)buffer;
620 
621 	for (; buffer_length >= MEI_SLOT_SIZE; buffer_length -= MEI_SLOT_SIZE)
622 		*reg_buf++ = mei_me_mecbrw_read(dev);
623 
624 	if (buffer_length > 0) {
625 		u32 reg = mei_me_mecbrw_read(dev);
626 
627 		memcpy(reg_buf, &reg, buffer_length);
628 	}
629 
630 	mei_hcsr_set_hig(dev);
631 	return 0;
632 }
633 
634 /**
635  * mei_me_pg_set - write pg enter register
636  *
637  * @dev: the device structure
638  */
639 static void mei_me_pg_set(struct mei_device *dev)
640 {
641 	struct mei_me_hw *hw = to_me_hw(dev);
642 	u32 reg;
643 
644 	reg = mei_me_reg_read(hw, H_HPG_CSR);
645 	trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
646 
647 	reg |= H_HPG_CSR_PGI;
648 
649 	trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
650 	mei_me_reg_write(hw, H_HPG_CSR, reg);
651 }
652 
653 /**
654  * mei_me_pg_unset - write pg exit register
655  *
656  * @dev: the device structure
657  */
658 static void mei_me_pg_unset(struct mei_device *dev)
659 {
660 	struct mei_me_hw *hw = to_me_hw(dev);
661 	u32 reg;
662 
663 	reg = mei_me_reg_read(hw, H_HPG_CSR);
664 	trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
665 
666 	WARN(!(reg & H_HPG_CSR_PGI), "PGI is not set\n");
667 
668 	reg |= H_HPG_CSR_PGIHEXR;
669 
670 	trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
671 	mei_me_reg_write(hw, H_HPG_CSR, reg);
672 }
673 
674 /**
675  * mei_me_pg_legacy_enter_sync - perform legacy pg entry procedure
676  *
677  * @dev: the device structure
678  *
679  * Return: 0 on success an error code otherwise
680  */
681 static int mei_me_pg_legacy_enter_sync(struct mei_device *dev)
682 {
683 	struct mei_me_hw *hw = to_me_hw(dev);
684 	unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
685 	int ret;
686 
687 	dev->pg_event = MEI_PG_EVENT_WAIT;
688 
689 	ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD);
690 	if (ret)
691 		return ret;
692 
693 	mutex_unlock(&dev->device_lock);
694 	wait_event_timeout(dev->wait_pg,
695 		dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
696 	mutex_lock(&dev->device_lock);
697 
698 	if (dev->pg_event == MEI_PG_EVENT_RECEIVED) {
699 		mei_me_pg_set(dev);
700 		ret = 0;
701 	} else {
702 		ret = -ETIME;
703 	}
704 
705 	dev->pg_event = MEI_PG_EVENT_IDLE;
706 	hw->pg_state = MEI_PG_ON;
707 
708 	return ret;
709 }
710 
711 /**
712  * mei_me_pg_legacy_exit_sync - perform legacy pg exit procedure
713  *
714  * @dev: the device structure
715  *
716  * Return: 0 on success an error code otherwise
717  */
718 static int mei_me_pg_legacy_exit_sync(struct mei_device *dev)
719 {
720 	struct mei_me_hw *hw = to_me_hw(dev);
721 	unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
722 	int ret;
723 
724 	if (dev->pg_event == MEI_PG_EVENT_RECEIVED)
725 		goto reply;
726 
727 	dev->pg_event = MEI_PG_EVENT_WAIT;
728 
729 	mei_me_pg_unset(dev);
730 
731 	mutex_unlock(&dev->device_lock);
732 	wait_event_timeout(dev->wait_pg,
733 		dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
734 	mutex_lock(&dev->device_lock);
735 
736 reply:
737 	if (dev->pg_event != MEI_PG_EVENT_RECEIVED) {
738 		ret = -ETIME;
739 		goto out;
740 	}
741 
742 	dev->pg_event = MEI_PG_EVENT_INTR_WAIT;
743 	ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD);
744 	if (ret)
745 		return ret;
746 
747 	mutex_unlock(&dev->device_lock);
748 	wait_event_timeout(dev->wait_pg,
749 		dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout);
750 	mutex_lock(&dev->device_lock);
751 
752 	if (dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED)
753 		ret = 0;
754 	else
755 		ret = -ETIME;
756 
757 out:
758 	dev->pg_event = MEI_PG_EVENT_IDLE;
759 	hw->pg_state = MEI_PG_OFF;
760 
761 	return ret;
762 }
763 
764 /**
765  * mei_me_pg_in_transition - is device now in pg transition
766  *
767  * @dev: the device structure
768  *
769  * Return: true if in pg transition, false otherwise
770  */
771 static bool mei_me_pg_in_transition(struct mei_device *dev)
772 {
773 	return dev->pg_event >= MEI_PG_EVENT_WAIT &&
774 	       dev->pg_event <= MEI_PG_EVENT_INTR_WAIT;
775 }
776 
777 /**
778  * mei_me_pg_is_enabled - detect if PG is supported by HW
779  *
780  * @dev: the device structure
781  *
782  * Return: true is pg supported, false otherwise
783  */
784 static bool mei_me_pg_is_enabled(struct mei_device *dev)
785 {
786 	struct mei_me_hw *hw = to_me_hw(dev);
787 	u32 reg = mei_me_mecsr_read(dev);
788 
789 	if (hw->d0i3_supported)
790 		return true;
791 
792 	if ((reg & ME_PGIC_HRA) == 0)
793 		goto notsupported;
794 
795 	if (!dev->hbm_f_pg_supported)
796 		goto notsupported;
797 
798 	return true;
799 
800 notsupported:
801 	dev_dbg(dev->dev, "pg: not supported: d0i3 = %d HGP = %d hbm version %d.%d ?= %d.%d\n",
802 		hw->d0i3_supported,
803 		!!(reg & ME_PGIC_HRA),
804 		dev->version.major_version,
805 		dev->version.minor_version,
806 		HBM_MAJOR_VERSION_PGI,
807 		HBM_MINOR_VERSION_PGI);
808 
809 	return false;
810 }
811 
812 /**
813  * mei_me_d0i3_set - write d0i3 register bit on mei device.
814  *
815  * @dev: the device structure
816  * @intr: ask for interrupt
817  *
818  * Return: D0I3C register value
819  */
820 static u32 mei_me_d0i3_set(struct mei_device *dev, bool intr)
821 {
822 	u32 reg = mei_me_d0i3c_read(dev);
823 
824 	reg |= H_D0I3C_I3;
825 	if (intr)
826 		reg |= H_D0I3C_IR;
827 	else
828 		reg &= ~H_D0I3C_IR;
829 	mei_me_d0i3c_write(dev, reg);
830 	/* read it to ensure HW consistency */
831 	reg = mei_me_d0i3c_read(dev);
832 	return reg;
833 }
834 
835 /**
836  * mei_me_d0i3_unset - clean d0i3 register bit on mei device.
837  *
838  * @dev: the device structure
839  *
840  * Return: D0I3C register value
841  */
842 static u32 mei_me_d0i3_unset(struct mei_device *dev)
843 {
844 	u32 reg = mei_me_d0i3c_read(dev);
845 
846 	reg &= ~H_D0I3C_I3;
847 	reg |= H_D0I3C_IR;
848 	mei_me_d0i3c_write(dev, reg);
849 	/* read it to ensure HW consistency */
850 	reg = mei_me_d0i3c_read(dev);
851 	return reg;
852 }
853 
854 /**
855  * mei_me_d0i3_enter_sync - perform d0i3 entry procedure
856  *
857  * @dev: the device structure
858  *
859  * Return: 0 on success an error code otherwise
860  */
861 static int mei_me_d0i3_enter_sync(struct mei_device *dev)
862 {
863 	struct mei_me_hw *hw = to_me_hw(dev);
864 	unsigned long d0i3_timeout = mei_secs_to_jiffies(MEI_D0I3_TIMEOUT);
865 	unsigned long pgi_timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
866 	int ret;
867 	u32 reg;
868 
869 	reg = mei_me_d0i3c_read(dev);
870 	if (reg & H_D0I3C_I3) {
871 		/* we are in d0i3, nothing to do */
872 		dev_dbg(dev->dev, "d0i3 set not needed\n");
873 		ret = 0;
874 		goto on;
875 	}
876 
877 	/* PGI entry procedure */
878 	dev->pg_event = MEI_PG_EVENT_WAIT;
879 
880 	ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD);
881 	if (ret)
882 		/* FIXME: should we reset here? */
883 		goto out;
884 
885 	mutex_unlock(&dev->device_lock);
886 	wait_event_timeout(dev->wait_pg,
887 		dev->pg_event == MEI_PG_EVENT_RECEIVED, pgi_timeout);
888 	mutex_lock(&dev->device_lock);
889 
890 	if (dev->pg_event != MEI_PG_EVENT_RECEIVED) {
891 		ret = -ETIME;
892 		goto out;
893 	}
894 	/* end PGI entry procedure */
895 
896 	dev->pg_event = MEI_PG_EVENT_INTR_WAIT;
897 
898 	reg = mei_me_d0i3_set(dev, true);
899 	if (!(reg & H_D0I3C_CIP)) {
900 		dev_dbg(dev->dev, "d0i3 enter wait not needed\n");
901 		ret = 0;
902 		goto on;
903 	}
904 
905 	mutex_unlock(&dev->device_lock);
906 	wait_event_timeout(dev->wait_pg,
907 		dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, d0i3_timeout);
908 	mutex_lock(&dev->device_lock);
909 
910 	if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) {
911 		reg = mei_me_d0i3c_read(dev);
912 		if (!(reg & H_D0I3C_I3)) {
913 			ret = -ETIME;
914 			goto out;
915 		}
916 	}
917 
918 	ret = 0;
919 on:
920 	hw->pg_state = MEI_PG_ON;
921 out:
922 	dev->pg_event = MEI_PG_EVENT_IDLE;
923 	dev_dbg(dev->dev, "d0i3 enter ret = %d\n", ret);
924 	return ret;
925 }
926 
927 /**
928  * mei_me_d0i3_enter - perform d0i3 entry procedure
929  *   no hbm PG handshake
930  *   no waiting for confirmation; runs with interrupts
931  *   disabled
932  *
933  * @dev: the device structure
934  *
935  * Return: 0 on success an error code otherwise
936  */
937 static int mei_me_d0i3_enter(struct mei_device *dev)
938 {
939 	struct mei_me_hw *hw = to_me_hw(dev);
940 	u32 reg;
941 
942 	reg = mei_me_d0i3c_read(dev);
943 	if (reg & H_D0I3C_I3) {
944 		/* we are in d0i3, nothing to do */
945 		dev_dbg(dev->dev, "already d0i3 : set not needed\n");
946 		goto on;
947 	}
948 
949 	mei_me_d0i3_set(dev, false);
950 on:
951 	hw->pg_state = MEI_PG_ON;
952 	dev->pg_event = MEI_PG_EVENT_IDLE;
953 	dev_dbg(dev->dev, "d0i3 enter\n");
954 	return 0;
955 }
956 
957 /**
958  * mei_me_d0i3_exit_sync - perform d0i3 exit procedure
959  *
960  * @dev: the device structure
961  *
962  * Return: 0 on success an error code otherwise
963  */
964 static int mei_me_d0i3_exit_sync(struct mei_device *dev)
965 {
966 	struct mei_me_hw *hw = to_me_hw(dev);
967 	unsigned long timeout = mei_secs_to_jiffies(MEI_D0I3_TIMEOUT);
968 	int ret;
969 	u32 reg;
970 
971 	dev->pg_event = MEI_PG_EVENT_INTR_WAIT;
972 
973 	reg = mei_me_d0i3c_read(dev);
974 	if (!(reg & H_D0I3C_I3)) {
975 		/* we are not in d0i3, nothing to do */
976 		dev_dbg(dev->dev, "d0i3 exit not needed\n");
977 		ret = 0;
978 		goto off;
979 	}
980 
981 	reg = mei_me_d0i3_unset(dev);
982 	if (!(reg & H_D0I3C_CIP)) {
983 		dev_dbg(dev->dev, "d0i3 exit wait not needed\n");
984 		ret = 0;
985 		goto off;
986 	}
987 
988 	mutex_unlock(&dev->device_lock);
989 	wait_event_timeout(dev->wait_pg,
990 		dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout);
991 	mutex_lock(&dev->device_lock);
992 
993 	if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) {
994 		reg = mei_me_d0i3c_read(dev);
995 		if (reg & H_D0I3C_I3) {
996 			ret = -ETIME;
997 			goto out;
998 		}
999 	}
1000 
1001 	ret = 0;
1002 off:
1003 	hw->pg_state = MEI_PG_OFF;
1004 out:
1005 	dev->pg_event = MEI_PG_EVENT_IDLE;
1006 
1007 	dev_dbg(dev->dev, "d0i3 exit ret = %d\n", ret);
1008 	return ret;
1009 }
1010 
1011 /**
1012  * mei_me_pg_legacy_intr - perform legacy pg processing
1013  *			   in interrupt thread handler
1014  *
1015  * @dev: the device structure
1016  */
1017 static void mei_me_pg_legacy_intr(struct mei_device *dev)
1018 {
1019 	struct mei_me_hw *hw = to_me_hw(dev);
1020 
1021 	if (dev->pg_event != MEI_PG_EVENT_INTR_WAIT)
1022 		return;
1023 
1024 	dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED;
1025 	hw->pg_state = MEI_PG_OFF;
1026 	if (waitqueue_active(&dev->wait_pg))
1027 		wake_up(&dev->wait_pg);
1028 }
1029 
1030 /**
1031  * mei_me_d0i3_intr - perform d0i3 processing in interrupt thread handler
1032  *
1033  * @dev: the device structure
1034  * @intr_source: interrupt source
1035  */
1036 static void mei_me_d0i3_intr(struct mei_device *dev, u32 intr_source)
1037 {
1038 	struct mei_me_hw *hw = to_me_hw(dev);
1039 
1040 	if (dev->pg_event == MEI_PG_EVENT_INTR_WAIT &&
1041 	    (intr_source & H_D0I3C_IS)) {
1042 		dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED;
1043 		if (hw->pg_state == MEI_PG_ON) {
1044 			hw->pg_state = MEI_PG_OFF;
1045 			if (dev->hbm_state != MEI_HBM_IDLE) {
1046 				/*
1047 				 * force H_RDY because it could be
1048 				 * wiped off during PG
1049 				 */
1050 				dev_dbg(dev->dev, "d0i3 set host ready\n");
1051 				mei_me_host_set_ready(dev);
1052 			}
1053 		} else {
1054 			hw->pg_state = MEI_PG_ON;
1055 		}
1056 
1057 		wake_up(&dev->wait_pg);
1058 	}
1059 
1060 	if (hw->pg_state == MEI_PG_ON && (intr_source & H_IS)) {
1061 		/*
1062 		 * HW sent some data and we are in D0i3, so
1063 		 * we got here because of HW initiated exit from D0i3.
1064 		 * Start runtime pm resume sequence to exit low power state.
1065 		 */
1066 		dev_dbg(dev->dev, "d0i3 want resume\n");
1067 		mei_hbm_pg_resume(dev);
1068 	}
1069 }
1070 
1071 /**
1072  * mei_me_pg_intr - perform pg processing in interrupt thread handler
1073  *
1074  * @dev: the device structure
1075  * @intr_source: interrupt source
1076  */
1077 static void mei_me_pg_intr(struct mei_device *dev, u32 intr_source)
1078 {
1079 	struct mei_me_hw *hw = to_me_hw(dev);
1080 
1081 	if (hw->d0i3_supported)
1082 		mei_me_d0i3_intr(dev, intr_source);
1083 	else
1084 		mei_me_pg_legacy_intr(dev);
1085 }
1086 
1087 /**
1088  * mei_me_pg_enter_sync - perform runtime pm entry procedure
1089  *
1090  * @dev: the device structure
1091  *
1092  * Return: 0 on success an error code otherwise
1093  */
1094 int mei_me_pg_enter_sync(struct mei_device *dev)
1095 {
1096 	struct mei_me_hw *hw = to_me_hw(dev);
1097 
1098 	if (hw->d0i3_supported)
1099 		return mei_me_d0i3_enter_sync(dev);
1100 	else
1101 		return mei_me_pg_legacy_enter_sync(dev);
1102 }
1103 
1104 /**
1105  * mei_me_pg_exit_sync - perform runtime pm exit procedure
1106  *
1107  * @dev: the device structure
1108  *
1109  * Return: 0 on success an error code otherwise
1110  */
1111 int mei_me_pg_exit_sync(struct mei_device *dev)
1112 {
1113 	struct mei_me_hw *hw = to_me_hw(dev);
1114 
1115 	if (hw->d0i3_supported)
1116 		return mei_me_d0i3_exit_sync(dev);
1117 	else
1118 		return mei_me_pg_legacy_exit_sync(dev);
1119 }
1120 
1121 /**
1122  * mei_me_hw_reset - resets fw via mei csr register.
1123  *
1124  * @dev: the device structure
1125  * @intr_enable: if interrupt should be enabled after reset.
1126  *
1127  * Return: 0 on success an error code otherwise
1128  */
1129 static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
1130 {
1131 	struct mei_me_hw *hw = to_me_hw(dev);
1132 	int ret;
1133 	u32 hcsr;
1134 
1135 	if (intr_enable) {
1136 		mei_me_intr_enable(dev);
1137 		if (hw->d0i3_supported) {
1138 			ret = mei_me_d0i3_exit_sync(dev);
1139 			if (ret)
1140 				return ret;
1141 		}
1142 	}
1143 
1144 	pm_runtime_set_active(dev->dev);
1145 
1146 	hcsr = mei_hcsr_read(dev);
1147 	/* H_RST may be found lit before reset is started,
1148 	 * for example if preceding reset flow hasn't completed.
1149 	 * In that case asserting H_RST will be ignored, therefore
1150 	 * we need to clean H_RST bit to start a successful reset sequence.
1151 	 */
1152 	if ((hcsr & H_RST) == H_RST) {
1153 		dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr);
1154 		hcsr &= ~H_RST;
1155 		mei_hcsr_set(dev, hcsr);
1156 		hcsr = mei_hcsr_read(dev);
1157 	}
1158 
1159 	hcsr |= H_RST | H_IG | H_CSR_IS_MASK;
1160 
1161 	if (!intr_enable)
1162 		hcsr &= ~H_CSR_IE_MASK;
1163 
1164 	dev->recvd_hw_ready = false;
1165 	mei_hcsr_write(dev, hcsr);
1166 
1167 	/*
1168 	 * Host reads the H_CSR once to ensure that the
1169 	 * posted write to H_CSR completes.
1170 	 */
1171 	hcsr = mei_hcsr_read(dev);
1172 
1173 	if ((hcsr & H_RST) == 0)
1174 		dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr);
1175 
1176 	if ((hcsr & H_RDY) == H_RDY)
1177 		dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr);
1178 
1179 	if (!intr_enable) {
1180 		mei_me_hw_reset_release(dev);
1181 		if (hw->d0i3_supported) {
1182 			ret = mei_me_d0i3_enter(dev);
1183 			if (ret)
1184 				return ret;
1185 		}
1186 	}
1187 	return 0;
1188 }
1189 
1190 /**
1191  * mei_me_irq_quick_handler - The ISR of the MEI device
1192  *
1193  * @irq: The irq number
1194  * @dev_id: pointer to the device structure
1195  *
1196  * Return: irqreturn_t
1197  */
1198 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id)
1199 {
1200 	struct mei_device *dev = (struct mei_device *)dev_id;
1201 	u32 hcsr;
1202 
1203 	hcsr = mei_hcsr_read(dev);
1204 	if (!me_intr_src(hcsr))
1205 		return IRQ_NONE;
1206 
1207 	dev_dbg(dev->dev, "interrupt source 0x%08X\n", me_intr_src(hcsr));
1208 
1209 	/* disable interrupts on device */
1210 	me_intr_disable(dev, hcsr);
1211 	return IRQ_WAKE_THREAD;
1212 }
1213 
1214 /**
1215  * mei_me_irq_thread_handler - function called after ISR to handle the interrupt
1216  * processing.
1217  *
1218  * @irq: The irq number
1219  * @dev_id: pointer to the device structure
1220  *
1221  * Return: irqreturn_t
1222  *
1223  */
1224 irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
1225 {
1226 	struct mei_device *dev = (struct mei_device *) dev_id;
1227 	struct list_head cmpl_list;
1228 	s32 slots;
1229 	u32 hcsr;
1230 	int rets = 0;
1231 
1232 	dev_dbg(dev->dev, "function called after ISR to handle the interrupt processing.\n");
1233 	/* initialize our complete list */
1234 	mutex_lock(&dev->device_lock);
1235 
1236 	hcsr = mei_hcsr_read(dev);
1237 	me_intr_clear(dev, hcsr);
1238 
1239 	INIT_LIST_HEAD(&cmpl_list);
1240 
1241 	/* check if ME wants a reset */
1242 	if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) {
1243 		dev_warn(dev->dev, "FW not ready: resetting.\n");
1244 		schedule_work(&dev->reset_work);
1245 		goto end;
1246 	}
1247 
1248 	if (mei_me_hw_is_resetting(dev))
1249 		mei_hcsr_set_hig(dev);
1250 
1251 	mei_me_pg_intr(dev, me_intr_src(hcsr));
1252 
1253 	/*  check if we need to start the dev */
1254 	if (!mei_host_is_ready(dev)) {
1255 		if (mei_hw_is_ready(dev)) {
1256 			dev_dbg(dev->dev, "we need to start the dev.\n");
1257 			dev->recvd_hw_ready = true;
1258 			wake_up(&dev->wait_hw_ready);
1259 		} else {
1260 			dev_dbg(dev->dev, "Spurious Interrupt\n");
1261 		}
1262 		goto end;
1263 	}
1264 	/* check slots available for reading */
1265 	slots = mei_count_full_read_slots(dev);
1266 	while (slots > 0) {
1267 		dev_dbg(dev->dev, "slots to read = %08x\n", slots);
1268 		rets = mei_irq_read_handler(dev, &cmpl_list, &slots);
1269 		/* There is a race between ME write and interrupt delivery:
1270 		 * Not all data is always available immediately after the
1271 		 * interrupt, so try to read again on the next interrupt.
1272 		 */
1273 		if (rets == -ENODATA)
1274 			break;
1275 
1276 		if (rets &&
1277 		    (dev->dev_state != MEI_DEV_RESETTING &&
1278 		     dev->dev_state != MEI_DEV_POWER_DOWN)) {
1279 			dev_err(dev->dev, "mei_irq_read_handler ret = %d.\n",
1280 						rets);
1281 			schedule_work(&dev->reset_work);
1282 			goto end;
1283 		}
1284 	}
1285 
1286 	dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
1287 
1288 	/*
1289 	 * During PG handshake only allowed write is the replay to the
1290 	 * PG exit message, so block calling write function
1291 	 * if the pg event is in PG handshake
1292 	 */
1293 	if (dev->pg_event != MEI_PG_EVENT_WAIT &&
1294 	    dev->pg_event != MEI_PG_EVENT_RECEIVED) {
1295 		rets = mei_irq_write_handler(dev, &cmpl_list);
1296 		dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
1297 	}
1298 
1299 	mei_irq_compl_handler(dev, &cmpl_list);
1300 
1301 end:
1302 	dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets);
1303 	mei_me_intr_enable(dev);
1304 	mutex_unlock(&dev->device_lock);
1305 	return IRQ_HANDLED;
1306 }
1307 
1308 static const struct mei_hw_ops mei_me_hw_ops = {
1309 
1310 	.fw_status = mei_me_fw_status,
1311 	.pg_state  = mei_me_pg_state,
1312 
1313 	.host_is_ready = mei_me_host_is_ready,
1314 
1315 	.hw_is_ready = mei_me_hw_is_ready,
1316 	.hw_reset = mei_me_hw_reset,
1317 	.hw_config = mei_me_hw_config,
1318 	.hw_start = mei_me_hw_start,
1319 
1320 	.pg_in_transition = mei_me_pg_in_transition,
1321 	.pg_is_enabled = mei_me_pg_is_enabled,
1322 
1323 	.intr_clear = mei_me_intr_clear,
1324 	.intr_enable = mei_me_intr_enable,
1325 	.intr_disable = mei_me_intr_disable,
1326 	.synchronize_irq = mei_me_synchronize_irq,
1327 
1328 	.hbuf_free_slots = mei_me_hbuf_empty_slots,
1329 	.hbuf_is_ready = mei_me_hbuf_is_empty,
1330 	.hbuf_depth = mei_me_hbuf_depth,
1331 
1332 	.write = mei_me_hbuf_write,
1333 
1334 	.rdbuf_full_slots = mei_me_count_full_read_slots,
1335 	.read_hdr = mei_me_mecbrw_read,
1336 	.read = mei_me_read_slots
1337 };
1338 
1339 static bool mei_me_fw_type_nm(struct pci_dev *pdev)
1340 {
1341 	u32 reg;
1342 
1343 	pci_read_config_dword(pdev, PCI_CFG_HFS_2, &reg);
1344 	trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_2", PCI_CFG_HFS_2, reg);
1345 	/* make sure that bit 9 (NM) is up and bit 10 (DM) is down */
1346 	return (reg & 0x600) == 0x200;
1347 }
1348 
1349 #define MEI_CFG_FW_NM                           \
1350 	.quirk_probe = mei_me_fw_type_nm
1351 
1352 static bool mei_me_fw_type_sps(struct pci_dev *pdev)
1353 {
1354 	u32 reg;
1355 	unsigned int devfn;
1356 
1357 	/*
1358 	 * Read ME FW Status register to check for SPS Firmware
1359 	 * The SPS FW is only signaled in pci function 0
1360 	 */
1361 	devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0);
1362 	pci_bus_read_config_dword(pdev->bus, devfn, PCI_CFG_HFS_1, &reg);
1363 	trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg);
1364 	/* if bits [19:16] = 15, running SPS Firmware */
1365 	return (reg & 0xf0000) == 0xf0000;
1366 }
1367 
1368 #define MEI_CFG_FW_SPS                           \
1369 	.quirk_probe = mei_me_fw_type_sps
1370 
1371 
1372 #define MEI_CFG_ICH_HFS                      \
1373 	.fw_status.count = 0
1374 
1375 #define MEI_CFG_ICH10_HFS                        \
1376 	.fw_status.count = 1,                   \
1377 	.fw_status.status[0] = PCI_CFG_HFS_1
1378 
1379 #define MEI_CFG_PCH_HFS                         \
1380 	.fw_status.count = 2,                   \
1381 	.fw_status.status[0] = PCI_CFG_HFS_1,   \
1382 	.fw_status.status[1] = PCI_CFG_HFS_2
1383 
1384 #define MEI_CFG_PCH8_HFS                        \
1385 	.fw_status.count = 6,                   \
1386 	.fw_status.status[0] = PCI_CFG_HFS_1,   \
1387 	.fw_status.status[1] = PCI_CFG_HFS_2,   \
1388 	.fw_status.status[2] = PCI_CFG_HFS_3,   \
1389 	.fw_status.status[3] = PCI_CFG_HFS_4,   \
1390 	.fw_status.status[4] = PCI_CFG_HFS_5,   \
1391 	.fw_status.status[5] = PCI_CFG_HFS_6
1392 
1393 #define MEI_CFG_DMA_128 \
1394 	.dma_size[DMA_DSCR_HOST] = SZ_128K, \
1395 	.dma_size[DMA_DSCR_DEVICE] = SZ_128K, \
1396 	.dma_size[DMA_DSCR_CTRL] = PAGE_SIZE
1397 
1398 /* ICH Legacy devices */
1399 static const struct mei_cfg mei_me_ich_cfg = {
1400 	MEI_CFG_ICH_HFS,
1401 };
1402 
1403 /* ICH devices */
1404 static const struct mei_cfg mei_me_ich10_cfg = {
1405 	MEI_CFG_ICH10_HFS,
1406 };
1407 
1408 /* PCH devices */
1409 static const struct mei_cfg mei_me_pch_cfg = {
1410 	MEI_CFG_PCH_HFS,
1411 };
1412 
1413 /* PCH Cougar Point and Patsburg with quirk for Node Manager exclusion */
1414 static const struct mei_cfg mei_me_pch_cpt_pbg_cfg = {
1415 	MEI_CFG_PCH_HFS,
1416 	MEI_CFG_FW_NM,
1417 };
1418 
1419 /* PCH8 Lynx Point and newer devices */
1420 static const struct mei_cfg mei_me_pch8_cfg = {
1421 	MEI_CFG_PCH8_HFS,
1422 };
1423 
1424 /* PCH8 Lynx Point with quirk for SPS Firmware exclusion */
1425 static const struct mei_cfg mei_me_pch8_sps_cfg = {
1426 	MEI_CFG_PCH8_HFS,
1427 	MEI_CFG_FW_SPS,
1428 };
1429 
1430 /* Cannon Lake and newer devices */
1431 static const struct mei_cfg mei_me_pch12_cfg = {
1432 	MEI_CFG_PCH8_HFS,
1433 	MEI_CFG_DMA_128,
1434 };
1435 
1436 /*
1437  * mei_cfg_list - A list of platform platform specific configurations.
1438  * Note: has to be synchronized with  enum mei_cfg_idx.
1439  */
1440 static const struct mei_cfg *const mei_cfg_list[] = {
1441 	[MEI_ME_UNDEF_CFG] = NULL,
1442 	[MEI_ME_ICH_CFG] = &mei_me_ich_cfg,
1443 	[MEI_ME_ICH10_CFG] = &mei_me_ich10_cfg,
1444 	[MEI_ME_PCH_CFG] = &mei_me_pch_cfg,
1445 	[MEI_ME_PCH_CPT_PBG_CFG] = &mei_me_pch_cpt_pbg_cfg,
1446 	[MEI_ME_PCH8_CFG] = &mei_me_pch8_cfg,
1447 	[MEI_ME_PCH8_SPS_CFG] = &mei_me_pch8_sps_cfg,
1448 	[MEI_ME_PCH12_CFG] = &mei_me_pch12_cfg,
1449 };
1450 
1451 const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx)
1452 {
1453 	BUILD_BUG_ON(ARRAY_SIZE(mei_cfg_list) != MEI_ME_NUM_CFG);
1454 
1455 	if (idx >= MEI_ME_NUM_CFG)
1456 		return NULL;
1457 
1458 	return mei_cfg_list[idx];
1459 };
1460 
1461 /**
1462  * mei_me_dev_init - allocates and initializes the mei device structure
1463  *
1464  * @pdev: The pci device structure
1465  * @cfg: per device generation config
1466  *
1467  * Return: The mei_device pointer on success, NULL on failure.
1468  */
1469 struct mei_device *mei_me_dev_init(struct pci_dev *pdev,
1470 				   const struct mei_cfg *cfg)
1471 {
1472 	struct mei_device *dev;
1473 	struct mei_me_hw *hw;
1474 
1475 	dev = devm_kzalloc(&pdev->dev, sizeof(struct mei_device) +
1476 			   sizeof(struct mei_me_hw), GFP_KERNEL);
1477 	if (!dev)
1478 		return NULL;
1479 	hw = to_me_hw(dev);
1480 
1481 	mei_device_init(dev, &pdev->dev, &mei_me_hw_ops);
1482 	hw->cfg = cfg;
1483 	return dev;
1484 }
1485 
1486