1 /* 2 * 3 * Intel Management Engine Interface (Intel MEI) Linux driver 4 * Copyright (c) 2003-2012, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 */ 16 17 #include <linux/pci.h> 18 19 #include <linux/kthread.h> 20 #include <linux/interrupt.h> 21 22 #include "mei_dev.h" 23 #include "hw-me.h" 24 25 #include "hbm.h" 26 27 28 /** 29 * mei_me_reg_read - Reads 32bit data from the mei device 30 * 31 * @dev: the device structure 32 * @offset: offset from which to read the data 33 * 34 * returns register value (u32) 35 */ 36 static inline u32 mei_me_reg_read(const struct mei_me_hw *hw, 37 unsigned long offset) 38 { 39 return ioread32(hw->mem_addr + offset); 40 } 41 42 43 /** 44 * mei_me_reg_write - Writes 32bit data to the mei device 45 * 46 * @dev: the device structure 47 * @offset: offset from which to write the data 48 * @value: register value to write (u32) 49 */ 50 static inline void mei_me_reg_write(const struct mei_me_hw *hw, 51 unsigned long offset, u32 value) 52 { 53 iowrite32(value, hw->mem_addr + offset); 54 } 55 56 /** 57 * mei_me_mecbrw_read - Reads 32bit data from ME circular buffer 58 * read window register 59 * 60 * @dev: the device structure 61 * 62 * returns ME_CB_RW register value (u32) 63 */ 64 static u32 mei_me_mecbrw_read(const struct mei_device *dev) 65 { 66 return mei_me_reg_read(to_me_hw(dev), ME_CB_RW); 67 } 68 /** 69 * mei_me_mecsr_read - Reads 32bit data from the ME CSR 70 * 71 * @dev: the device structure 72 * 73 * returns ME_CSR_HA register value (u32) 74 */ 75 static inline u32 mei_me_mecsr_read(const struct mei_me_hw *hw) 76 { 77 return mei_me_reg_read(hw, ME_CSR_HA); 78 } 79 80 /** 81 * mei_hcsr_read - Reads 32bit data from the host CSR 82 * 83 * @dev: the device structure 84 * 85 * returns H_CSR register value (u32) 86 */ 87 static inline u32 mei_hcsr_read(const struct mei_me_hw *hw) 88 { 89 return mei_me_reg_read(hw, H_CSR); 90 } 91 92 /** 93 * mei_hcsr_set - writes H_CSR register to the mei device, 94 * and ignores the H_IS bit for it is write-one-to-zero. 95 * 96 * @dev: the device structure 97 */ 98 static inline void mei_hcsr_set(struct mei_me_hw *hw, u32 hcsr) 99 { 100 hcsr &= ~H_IS; 101 mei_me_reg_write(hw, H_CSR, hcsr); 102 } 103 104 105 /** 106 * mei_me_hw_config - configure hw dependent settings 107 * 108 * @dev: mei device 109 */ 110 static void mei_me_hw_config(struct mei_device *dev) 111 { 112 u32 hcsr = mei_hcsr_read(to_me_hw(dev)); 113 /* Doesn't change in runtime */ 114 dev->hbuf_depth = (hcsr & H_CBD) >> 24; 115 } 116 /** 117 * mei_clear_interrupts - clear and stop interrupts 118 * 119 * @dev: the device structure 120 */ 121 static void mei_me_intr_clear(struct mei_device *dev) 122 { 123 struct mei_me_hw *hw = to_me_hw(dev); 124 u32 hcsr = mei_hcsr_read(hw); 125 if ((hcsr & H_IS) == H_IS) 126 mei_me_reg_write(hw, H_CSR, hcsr); 127 } 128 /** 129 * mei_me_intr_enable - enables mei device interrupts 130 * 131 * @dev: the device structure 132 */ 133 static void mei_me_intr_enable(struct mei_device *dev) 134 { 135 struct mei_me_hw *hw = to_me_hw(dev); 136 u32 hcsr = mei_hcsr_read(hw); 137 hcsr |= H_IE; 138 mei_hcsr_set(hw, hcsr); 139 } 140 141 /** 142 * mei_disable_interrupts - disables mei device interrupts 143 * 144 * @dev: the device structure 145 */ 146 static void mei_me_intr_disable(struct mei_device *dev) 147 { 148 struct mei_me_hw *hw = to_me_hw(dev); 149 u32 hcsr = mei_hcsr_read(hw); 150 hcsr &= ~H_IE; 151 mei_hcsr_set(hw, hcsr); 152 } 153 154 /** 155 * mei_me_hw_reset_release - release device from the reset 156 * 157 * @dev: the device structure 158 */ 159 static void mei_me_hw_reset_release(struct mei_device *dev) 160 { 161 struct mei_me_hw *hw = to_me_hw(dev); 162 u32 hcsr = mei_hcsr_read(hw); 163 164 hcsr |= H_IG; 165 hcsr &= ~H_RST; 166 mei_hcsr_set(hw, hcsr); 167 } 168 /** 169 * mei_me_hw_reset - resets fw via mei csr register. 170 * 171 * @dev: the device structure 172 * @intr_enable: if interrupt should be enabled after reset. 173 */ 174 static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable) 175 { 176 struct mei_me_hw *hw = to_me_hw(dev); 177 u32 hcsr = mei_hcsr_read(hw); 178 179 dev_dbg(&dev->pdev->dev, "before reset HCSR = 0x%08x.\n", hcsr); 180 181 hcsr |= (H_RST | H_IG); 182 183 if (intr_enable) 184 hcsr |= H_IE; 185 else 186 hcsr |= ~H_IE; 187 188 mei_hcsr_set(hw, hcsr); 189 190 if (dev->dev_state == MEI_DEV_POWER_DOWN) 191 mei_me_hw_reset_release(dev); 192 193 dev_dbg(&dev->pdev->dev, "current HCSR = 0x%08x.\n", mei_hcsr_read(hw)); 194 return 0; 195 } 196 197 /** 198 * mei_me_host_set_ready - enable device 199 * 200 * @dev - mei device 201 * returns bool 202 */ 203 204 static void mei_me_host_set_ready(struct mei_device *dev) 205 { 206 struct mei_me_hw *hw = to_me_hw(dev); 207 hw->host_hw_state |= H_IE | H_IG | H_RDY; 208 mei_hcsr_set(hw, hw->host_hw_state); 209 } 210 /** 211 * mei_me_host_is_ready - check whether the host has turned ready 212 * 213 * @dev - mei device 214 * returns bool 215 */ 216 static bool mei_me_host_is_ready(struct mei_device *dev) 217 { 218 struct mei_me_hw *hw = to_me_hw(dev); 219 hw->host_hw_state = mei_hcsr_read(hw); 220 return (hw->host_hw_state & H_RDY) == H_RDY; 221 } 222 223 /** 224 * mei_me_hw_is_ready - check whether the me(hw) has turned ready 225 * 226 * @dev - mei device 227 * returns bool 228 */ 229 static bool mei_me_hw_is_ready(struct mei_device *dev) 230 { 231 struct mei_me_hw *hw = to_me_hw(dev); 232 hw->me_hw_state = mei_me_mecsr_read(hw); 233 return (hw->me_hw_state & ME_RDY_HRA) == ME_RDY_HRA; 234 } 235 236 static int mei_me_hw_ready_wait(struct mei_device *dev) 237 { 238 int err; 239 if (mei_me_hw_is_ready(dev)) 240 return 0; 241 242 dev->recvd_hw_ready = false; 243 mutex_unlock(&dev->device_lock); 244 err = wait_event_interruptible_timeout(dev->wait_hw_ready, 245 dev->recvd_hw_ready, 246 mei_secs_to_jiffies(MEI_INTEROP_TIMEOUT)); 247 mutex_lock(&dev->device_lock); 248 if (!err && !dev->recvd_hw_ready) { 249 if (!err) 250 err = -ETIMEDOUT; 251 dev_err(&dev->pdev->dev, 252 "wait hw ready failed. status = %d\n", err); 253 return err; 254 } 255 256 dev->recvd_hw_ready = false; 257 return 0; 258 } 259 260 static int mei_me_hw_start(struct mei_device *dev) 261 { 262 int ret = mei_me_hw_ready_wait(dev); 263 if (ret) 264 return ret; 265 dev_dbg(&dev->pdev->dev, "hw is ready\n"); 266 267 mei_me_host_set_ready(dev); 268 return ret; 269 } 270 271 272 /** 273 * mei_hbuf_filled_slots - gets number of device filled buffer slots 274 * 275 * @dev: the device structure 276 * 277 * returns number of filled slots 278 */ 279 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev) 280 { 281 struct mei_me_hw *hw = to_me_hw(dev); 282 char read_ptr, write_ptr; 283 284 hw->host_hw_state = mei_hcsr_read(hw); 285 286 read_ptr = (char) ((hw->host_hw_state & H_CBRP) >> 8); 287 write_ptr = (char) ((hw->host_hw_state & H_CBWP) >> 16); 288 289 return (unsigned char) (write_ptr - read_ptr); 290 } 291 292 /** 293 * mei_me_hbuf_is_empty - checks if host buffer is empty. 294 * 295 * @dev: the device structure 296 * 297 * returns true if empty, false - otherwise. 298 */ 299 static bool mei_me_hbuf_is_empty(struct mei_device *dev) 300 { 301 return mei_hbuf_filled_slots(dev) == 0; 302 } 303 304 /** 305 * mei_me_hbuf_empty_slots - counts write empty slots. 306 * 307 * @dev: the device structure 308 * 309 * returns -1(ESLOTS_OVERFLOW) if overflow, otherwise empty slots count 310 */ 311 static int mei_me_hbuf_empty_slots(struct mei_device *dev) 312 { 313 unsigned char filled_slots, empty_slots; 314 315 filled_slots = mei_hbuf_filled_slots(dev); 316 empty_slots = dev->hbuf_depth - filled_slots; 317 318 /* check for overflow */ 319 if (filled_slots > dev->hbuf_depth) 320 return -EOVERFLOW; 321 322 return empty_slots; 323 } 324 325 static size_t mei_me_hbuf_max_len(const struct mei_device *dev) 326 { 327 return dev->hbuf_depth * sizeof(u32) - sizeof(struct mei_msg_hdr); 328 } 329 330 331 /** 332 * mei_write_message - writes a message to mei device. 333 * 334 * @dev: the device structure 335 * @header: mei HECI header of message 336 * @buf: message payload will be written 337 * 338 * This function returns -EIO if write has failed 339 */ 340 static int mei_me_write_message(struct mei_device *dev, 341 struct mei_msg_hdr *header, 342 unsigned char *buf) 343 { 344 struct mei_me_hw *hw = to_me_hw(dev); 345 unsigned long rem; 346 unsigned long length = header->length; 347 u32 *reg_buf = (u32 *)buf; 348 u32 hcsr; 349 u32 dw_cnt; 350 int i; 351 int empty_slots; 352 353 dev_dbg(&dev->pdev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header)); 354 355 empty_slots = mei_hbuf_empty_slots(dev); 356 dev_dbg(&dev->pdev->dev, "empty slots = %hu.\n", empty_slots); 357 358 dw_cnt = mei_data2slots(length); 359 if (empty_slots < 0 || dw_cnt > empty_slots) 360 return -EIO; 361 362 mei_me_reg_write(hw, H_CB_WW, *((u32 *) header)); 363 364 for (i = 0; i < length / 4; i++) 365 mei_me_reg_write(hw, H_CB_WW, reg_buf[i]); 366 367 rem = length & 0x3; 368 if (rem > 0) { 369 u32 reg = 0; 370 memcpy(®, &buf[length - rem], rem); 371 mei_me_reg_write(hw, H_CB_WW, reg); 372 } 373 374 hcsr = mei_hcsr_read(hw) | H_IG; 375 mei_hcsr_set(hw, hcsr); 376 if (!mei_me_hw_is_ready(dev)) 377 return -EIO; 378 379 return 0; 380 } 381 382 /** 383 * mei_me_count_full_read_slots - counts read full slots. 384 * 385 * @dev: the device structure 386 * 387 * returns -1(ESLOTS_OVERFLOW) if overflow, otherwise filled slots count 388 */ 389 static int mei_me_count_full_read_slots(struct mei_device *dev) 390 { 391 struct mei_me_hw *hw = to_me_hw(dev); 392 char read_ptr, write_ptr; 393 unsigned char buffer_depth, filled_slots; 394 395 hw->me_hw_state = mei_me_mecsr_read(hw); 396 buffer_depth = (unsigned char)((hw->me_hw_state & ME_CBD_HRA) >> 24); 397 read_ptr = (char) ((hw->me_hw_state & ME_CBRP_HRA) >> 8); 398 write_ptr = (char) ((hw->me_hw_state & ME_CBWP_HRA) >> 16); 399 filled_slots = (unsigned char) (write_ptr - read_ptr); 400 401 /* check for overflow */ 402 if (filled_slots > buffer_depth) 403 return -EOVERFLOW; 404 405 dev_dbg(&dev->pdev->dev, "filled_slots =%08x\n", filled_slots); 406 return (int)filled_slots; 407 } 408 409 /** 410 * mei_me_read_slots - reads a message from mei device. 411 * 412 * @dev: the device structure 413 * @buffer: message buffer will be written 414 * @buffer_length: message size will be read 415 */ 416 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer, 417 unsigned long buffer_length) 418 { 419 struct mei_me_hw *hw = to_me_hw(dev); 420 u32 *reg_buf = (u32 *)buffer; 421 u32 hcsr; 422 423 for (; buffer_length >= sizeof(u32); buffer_length -= sizeof(u32)) 424 *reg_buf++ = mei_me_mecbrw_read(dev); 425 426 if (buffer_length > 0) { 427 u32 reg = mei_me_mecbrw_read(dev); 428 memcpy(reg_buf, ®, buffer_length); 429 } 430 431 hcsr = mei_hcsr_read(hw) | H_IG; 432 mei_hcsr_set(hw, hcsr); 433 return 0; 434 } 435 436 /** 437 * mei_me_irq_quick_handler - The ISR of the MEI device 438 * 439 * @irq: The irq number 440 * @dev_id: pointer to the device structure 441 * 442 * returns irqreturn_t 443 */ 444 445 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id) 446 { 447 struct mei_device *dev = (struct mei_device *) dev_id; 448 struct mei_me_hw *hw = to_me_hw(dev); 449 u32 csr_reg = mei_hcsr_read(hw); 450 451 if ((csr_reg & H_IS) != H_IS) 452 return IRQ_NONE; 453 454 /* clear H_IS bit in H_CSR */ 455 mei_me_reg_write(hw, H_CSR, csr_reg); 456 457 return IRQ_WAKE_THREAD; 458 } 459 460 /** 461 * mei_me_irq_thread_handler - function called after ISR to handle the interrupt 462 * processing. 463 * 464 * @irq: The irq number 465 * @dev_id: pointer to the device structure 466 * 467 * returns irqreturn_t 468 * 469 */ 470 irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id) 471 { 472 struct mei_device *dev = (struct mei_device *) dev_id; 473 struct mei_cl_cb complete_list; 474 s32 slots; 475 int rets; 476 477 dev_dbg(&dev->pdev->dev, "function called after ISR to handle the interrupt processing.\n"); 478 /* initialize our complete list */ 479 mutex_lock(&dev->device_lock); 480 mei_io_list_init(&complete_list); 481 482 /* Ack the interrupt here 483 * In case of MSI we don't go through the quick handler */ 484 if (pci_dev_msi_enabled(dev->pdev)) 485 mei_clear_interrupts(dev); 486 487 /* check if ME wants a reset */ 488 if (!mei_hw_is_ready(dev) && 489 dev->dev_state != MEI_DEV_RESETTING && 490 dev->dev_state != MEI_DEV_INITIALIZING && 491 dev->dev_state != MEI_DEV_POWER_DOWN && 492 dev->dev_state != MEI_DEV_POWER_UP) { 493 dev_dbg(&dev->pdev->dev, "FW not ready.\n"); 494 mei_reset(dev, 1); 495 mutex_unlock(&dev->device_lock); 496 return IRQ_HANDLED; 497 } 498 499 /* check if we need to start the dev */ 500 if (!mei_host_is_ready(dev)) { 501 if (mei_hw_is_ready(dev)) { 502 dev_dbg(&dev->pdev->dev, "we need to start the dev.\n"); 503 504 dev->recvd_hw_ready = true; 505 wake_up_interruptible(&dev->wait_hw_ready); 506 507 mutex_unlock(&dev->device_lock); 508 return IRQ_HANDLED; 509 } else { 510 dev_dbg(&dev->pdev->dev, "Reset Completed.\n"); 511 mei_me_hw_reset_release(dev); 512 mutex_unlock(&dev->device_lock); 513 return IRQ_HANDLED; 514 } 515 } 516 /* check slots available for reading */ 517 slots = mei_count_full_read_slots(dev); 518 while (slots > 0) { 519 /* we have urgent data to send so break the read */ 520 if (dev->wr_ext_msg.hdr.length) 521 break; 522 dev_dbg(&dev->pdev->dev, "slots =%08x\n", slots); 523 dev_dbg(&dev->pdev->dev, "call mei_irq_read_handler.\n"); 524 rets = mei_irq_read_handler(dev, &complete_list, &slots); 525 if (rets) 526 goto end; 527 } 528 rets = mei_irq_write_handler(dev, &complete_list); 529 end: 530 dev_dbg(&dev->pdev->dev, "end of bottom half function.\n"); 531 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); 532 533 mutex_unlock(&dev->device_lock); 534 535 mei_irq_compl_handler(dev, &complete_list); 536 537 return IRQ_HANDLED; 538 } 539 static const struct mei_hw_ops mei_me_hw_ops = { 540 541 .host_is_ready = mei_me_host_is_ready, 542 543 .hw_is_ready = mei_me_hw_is_ready, 544 .hw_reset = mei_me_hw_reset, 545 .hw_config = mei_me_hw_config, 546 .hw_start = mei_me_hw_start, 547 548 .intr_clear = mei_me_intr_clear, 549 .intr_enable = mei_me_intr_enable, 550 .intr_disable = mei_me_intr_disable, 551 552 .hbuf_free_slots = mei_me_hbuf_empty_slots, 553 .hbuf_is_ready = mei_me_hbuf_is_empty, 554 .hbuf_max_len = mei_me_hbuf_max_len, 555 556 .write = mei_me_write_message, 557 558 .rdbuf_full_slots = mei_me_count_full_read_slots, 559 .read_hdr = mei_me_mecbrw_read, 560 .read = mei_me_read_slots 561 }; 562 563 /** 564 * mei_me_dev_init - allocates and initializes the mei device structure 565 * 566 * @pdev: The pci device structure 567 * 568 * returns The mei_device_device pointer on success, NULL on failure. 569 */ 570 struct mei_device *mei_me_dev_init(struct pci_dev *pdev) 571 { 572 struct mei_device *dev; 573 574 dev = kzalloc(sizeof(struct mei_device) + 575 sizeof(struct mei_me_hw), GFP_KERNEL); 576 if (!dev) 577 return NULL; 578 579 mei_device_init(dev); 580 581 dev->ops = &mei_me_hw_ops; 582 583 dev->pdev = pdev; 584 return dev; 585 } 586 587