1 /* 2 * 3 * Intel Management Engine Interface (Intel MEI) Linux driver 4 * Copyright (c) 2003-2012, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 */ 16 17 #include <linux/pci.h> 18 19 #include <linux/kthread.h> 20 #include <linux/interrupt.h> 21 22 #include "mei_dev.h" 23 #include "hbm.h" 24 25 #include "hw-me.h" 26 #include "hw-me-regs.h" 27 28 /** 29 * mei_me_reg_read - Reads 32bit data from the mei device 30 * 31 * @hw: the me hardware structure 32 * @offset: offset from which to read the data 33 * 34 * Return: register value (u32) 35 */ 36 static inline u32 mei_me_reg_read(const struct mei_me_hw *hw, 37 unsigned long offset) 38 { 39 return ioread32(hw->mem_addr + offset); 40 } 41 42 43 /** 44 * mei_me_reg_write - Writes 32bit data to the mei device 45 * 46 * @hw: the me hardware structure 47 * @offset: offset from which to write the data 48 * @value: register value to write (u32) 49 */ 50 static inline void mei_me_reg_write(const struct mei_me_hw *hw, 51 unsigned long offset, u32 value) 52 { 53 iowrite32(value, hw->mem_addr + offset); 54 } 55 56 /** 57 * mei_me_mecbrw_read - Reads 32bit data from ME circular buffer 58 * read window register 59 * 60 * @dev: the device structure 61 * 62 * Return: ME_CB_RW register value (u32) 63 */ 64 static u32 mei_me_mecbrw_read(const struct mei_device *dev) 65 { 66 return mei_me_reg_read(to_me_hw(dev), ME_CB_RW); 67 } 68 /** 69 * mei_me_mecsr_read - Reads 32bit data from the ME CSR 70 * 71 * @hw: the me hardware structure 72 * 73 * Return: ME_CSR_HA register value (u32) 74 */ 75 static inline u32 mei_me_mecsr_read(const struct mei_me_hw *hw) 76 { 77 return mei_me_reg_read(hw, ME_CSR_HA); 78 } 79 80 /** 81 * mei_hcsr_read - Reads 32bit data from the host CSR 82 * 83 * @hw: the me hardware structure 84 * 85 * Return: H_CSR register value (u32) 86 */ 87 static inline u32 mei_hcsr_read(const struct mei_me_hw *hw) 88 { 89 return mei_me_reg_read(hw, H_CSR); 90 } 91 92 /** 93 * mei_hcsr_set - writes H_CSR register to the mei device, 94 * and ignores the H_IS bit for it is write-one-to-zero. 95 * 96 * @hw: the me hardware structure 97 * @hcsr: new register value 98 */ 99 static inline void mei_hcsr_set(struct mei_me_hw *hw, u32 hcsr) 100 { 101 hcsr &= ~H_IS; 102 mei_me_reg_write(hw, H_CSR, hcsr); 103 } 104 105 /** 106 * mei_me_fw_status - read fw status register from pci config space 107 * 108 * @dev: mei device 109 * @fw_status: fw status register values 110 * 111 * Return: 0 on success, error otherwise 112 */ 113 static int mei_me_fw_status(struct mei_device *dev, 114 struct mei_fw_status *fw_status) 115 { 116 struct pci_dev *pdev = to_pci_dev(dev->dev); 117 struct mei_me_hw *hw = to_me_hw(dev); 118 const struct mei_fw_status *fw_src = &hw->cfg->fw_status; 119 int ret; 120 int i; 121 122 if (!fw_status) 123 return -EINVAL; 124 125 fw_status->count = fw_src->count; 126 for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) { 127 ret = pci_read_config_dword(pdev, 128 fw_src->status[i], &fw_status->status[i]); 129 if (ret) 130 return ret; 131 } 132 133 return 0; 134 } 135 136 /** 137 * mei_me_hw_config - configure hw dependent settings 138 * 139 * @dev: mei device 140 */ 141 static void mei_me_hw_config(struct mei_device *dev) 142 { 143 struct mei_me_hw *hw = to_me_hw(dev); 144 u32 hcsr = mei_hcsr_read(to_me_hw(dev)); 145 /* Doesn't change in runtime */ 146 dev->hbuf_depth = (hcsr & H_CBD) >> 24; 147 148 hw->pg_state = MEI_PG_OFF; 149 } 150 151 /** 152 * mei_me_pg_state - translate internal pg state 153 * to the mei power gating state 154 * 155 * @dev: mei device 156 * 157 * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise 158 */ 159 static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev) 160 { 161 struct mei_me_hw *hw = to_me_hw(dev); 162 163 return hw->pg_state; 164 } 165 166 /** 167 * mei_me_intr_clear - clear and stop interrupts 168 * 169 * @dev: the device structure 170 */ 171 static void mei_me_intr_clear(struct mei_device *dev) 172 { 173 struct mei_me_hw *hw = to_me_hw(dev); 174 u32 hcsr = mei_hcsr_read(hw); 175 176 if ((hcsr & H_IS) == H_IS) 177 mei_me_reg_write(hw, H_CSR, hcsr); 178 } 179 /** 180 * mei_me_intr_enable - enables mei device interrupts 181 * 182 * @dev: the device structure 183 */ 184 static void mei_me_intr_enable(struct mei_device *dev) 185 { 186 struct mei_me_hw *hw = to_me_hw(dev); 187 u32 hcsr = mei_hcsr_read(hw); 188 189 hcsr |= H_IE; 190 mei_hcsr_set(hw, hcsr); 191 } 192 193 /** 194 * mei_me_intr_disable - disables mei device interrupts 195 * 196 * @dev: the device structure 197 */ 198 static void mei_me_intr_disable(struct mei_device *dev) 199 { 200 struct mei_me_hw *hw = to_me_hw(dev); 201 u32 hcsr = mei_hcsr_read(hw); 202 203 hcsr &= ~H_IE; 204 mei_hcsr_set(hw, hcsr); 205 } 206 207 /** 208 * mei_me_hw_reset_release - release device from the reset 209 * 210 * @dev: the device structure 211 */ 212 static void mei_me_hw_reset_release(struct mei_device *dev) 213 { 214 struct mei_me_hw *hw = to_me_hw(dev); 215 u32 hcsr = mei_hcsr_read(hw); 216 217 hcsr |= H_IG; 218 hcsr &= ~H_RST; 219 mei_hcsr_set(hw, hcsr); 220 221 /* complete this write before we set host ready on another CPU */ 222 mmiowb(); 223 } 224 /** 225 * mei_me_hw_reset - resets fw via mei csr register. 226 * 227 * @dev: the device structure 228 * @intr_enable: if interrupt should be enabled after reset. 229 * 230 * Return: always 0 231 */ 232 static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable) 233 { 234 struct mei_me_hw *hw = to_me_hw(dev); 235 u32 hcsr = mei_hcsr_read(hw); 236 237 /* H_RST may be found lit before reset is started, 238 * for example if preceding reset flow hasn't completed. 239 * In that case asserting H_RST will be ignored, therefore 240 * we need to clean H_RST bit to start a successful reset sequence. 241 */ 242 if ((hcsr & H_RST) == H_RST) { 243 dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr); 244 hcsr &= ~H_RST; 245 mei_hcsr_set(hw, hcsr); 246 hcsr = mei_hcsr_read(hw); 247 } 248 249 hcsr |= H_RST | H_IG | H_IS; 250 251 if (intr_enable) 252 hcsr |= H_IE; 253 else 254 hcsr &= ~H_IE; 255 256 dev->recvd_hw_ready = false; 257 mei_me_reg_write(hw, H_CSR, hcsr); 258 259 /* 260 * Host reads the H_CSR once to ensure that the 261 * posted write to H_CSR completes. 262 */ 263 hcsr = mei_hcsr_read(hw); 264 265 if ((hcsr & H_RST) == 0) 266 dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr); 267 268 if ((hcsr & H_RDY) == H_RDY) 269 dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr); 270 271 if (intr_enable == false) 272 mei_me_hw_reset_release(dev); 273 274 return 0; 275 } 276 277 /** 278 * mei_me_host_set_ready - enable device 279 * 280 * @dev: mei device 281 */ 282 static void mei_me_host_set_ready(struct mei_device *dev) 283 { 284 struct mei_me_hw *hw = to_me_hw(dev); 285 u32 hcsr = mei_hcsr_read(hw); 286 287 hcsr |= H_IE | H_IG | H_RDY; 288 mei_hcsr_set(hw, hcsr); 289 } 290 291 /** 292 * mei_me_host_is_ready - check whether the host has turned ready 293 * 294 * @dev: mei device 295 * Return: bool 296 */ 297 static bool mei_me_host_is_ready(struct mei_device *dev) 298 { 299 struct mei_me_hw *hw = to_me_hw(dev); 300 u32 hcsr = mei_hcsr_read(hw); 301 302 return (hcsr & H_RDY) == H_RDY; 303 } 304 305 /** 306 * mei_me_hw_is_ready - check whether the me(hw) has turned ready 307 * 308 * @dev: mei device 309 * Return: bool 310 */ 311 static bool mei_me_hw_is_ready(struct mei_device *dev) 312 { 313 struct mei_me_hw *hw = to_me_hw(dev); 314 u32 mecsr = mei_me_mecsr_read(hw); 315 316 return (mecsr & ME_RDY_HRA) == ME_RDY_HRA; 317 } 318 319 /** 320 * mei_me_hw_ready_wait - wait until the me(hw) has turned ready 321 * or timeout is reached 322 * 323 * @dev: mei device 324 * Return: 0 on success, error otherwise 325 */ 326 static int mei_me_hw_ready_wait(struct mei_device *dev) 327 { 328 mutex_unlock(&dev->device_lock); 329 wait_event_timeout(dev->wait_hw_ready, 330 dev->recvd_hw_ready, 331 mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT)); 332 mutex_lock(&dev->device_lock); 333 if (!dev->recvd_hw_ready) { 334 dev_err(dev->dev, "wait hw ready failed\n"); 335 return -ETIME; 336 } 337 338 mei_me_hw_reset_release(dev); 339 dev->recvd_hw_ready = false; 340 return 0; 341 } 342 343 /** 344 * mei_me_hw_start - hw start routine 345 * 346 * @dev: mei device 347 * Return: 0 on success, error otherwise 348 */ 349 static int mei_me_hw_start(struct mei_device *dev) 350 { 351 int ret = mei_me_hw_ready_wait(dev); 352 353 if (ret) 354 return ret; 355 dev_dbg(dev->dev, "hw is ready\n"); 356 357 mei_me_host_set_ready(dev); 358 return ret; 359 } 360 361 362 /** 363 * mei_hbuf_filled_slots - gets number of device filled buffer slots 364 * 365 * @dev: the device structure 366 * 367 * Return: number of filled slots 368 */ 369 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev) 370 { 371 struct mei_me_hw *hw = to_me_hw(dev); 372 u32 hcsr; 373 char read_ptr, write_ptr; 374 375 hcsr = mei_hcsr_read(hw); 376 377 read_ptr = (char) ((hcsr & H_CBRP) >> 8); 378 write_ptr = (char) ((hcsr & H_CBWP) >> 16); 379 380 return (unsigned char) (write_ptr - read_ptr); 381 } 382 383 /** 384 * mei_me_hbuf_is_empty - checks if host buffer is empty. 385 * 386 * @dev: the device structure 387 * 388 * Return: true if empty, false - otherwise. 389 */ 390 static bool mei_me_hbuf_is_empty(struct mei_device *dev) 391 { 392 return mei_hbuf_filled_slots(dev) == 0; 393 } 394 395 /** 396 * mei_me_hbuf_empty_slots - counts write empty slots. 397 * 398 * @dev: the device structure 399 * 400 * Return: -EOVERFLOW if overflow, otherwise empty slots count 401 */ 402 static int mei_me_hbuf_empty_slots(struct mei_device *dev) 403 { 404 unsigned char filled_slots, empty_slots; 405 406 filled_slots = mei_hbuf_filled_slots(dev); 407 empty_slots = dev->hbuf_depth - filled_slots; 408 409 /* check for overflow */ 410 if (filled_slots > dev->hbuf_depth) 411 return -EOVERFLOW; 412 413 return empty_slots; 414 } 415 416 /** 417 * mei_me_hbuf_max_len - returns size of hw buffer. 418 * 419 * @dev: the device structure 420 * 421 * Return: size of hw buffer in bytes 422 */ 423 static size_t mei_me_hbuf_max_len(const struct mei_device *dev) 424 { 425 return dev->hbuf_depth * sizeof(u32) - sizeof(struct mei_msg_hdr); 426 } 427 428 429 /** 430 * mei_me_write_message - writes a message to mei device. 431 * 432 * @dev: the device structure 433 * @header: mei HECI header of message 434 * @buf: message payload will be written 435 * 436 * Return: -EIO if write has failed 437 */ 438 static int mei_me_write_message(struct mei_device *dev, 439 struct mei_msg_hdr *header, 440 unsigned char *buf) 441 { 442 struct mei_me_hw *hw = to_me_hw(dev); 443 unsigned long rem; 444 unsigned long length = header->length; 445 u32 *reg_buf = (u32 *)buf; 446 u32 hcsr; 447 u32 dw_cnt; 448 int i; 449 int empty_slots; 450 451 dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header)); 452 453 empty_slots = mei_hbuf_empty_slots(dev); 454 dev_dbg(dev->dev, "empty slots = %hu.\n", empty_slots); 455 456 dw_cnt = mei_data2slots(length); 457 if (empty_slots < 0 || dw_cnt > empty_slots) 458 return -EMSGSIZE; 459 460 mei_me_reg_write(hw, H_CB_WW, *((u32 *) header)); 461 462 for (i = 0; i < length / 4; i++) 463 mei_me_reg_write(hw, H_CB_WW, reg_buf[i]); 464 465 rem = length & 0x3; 466 if (rem > 0) { 467 u32 reg = 0; 468 469 memcpy(®, &buf[length - rem], rem); 470 mei_me_reg_write(hw, H_CB_WW, reg); 471 } 472 473 hcsr = mei_hcsr_read(hw) | H_IG; 474 mei_hcsr_set(hw, hcsr); 475 if (!mei_me_hw_is_ready(dev)) 476 return -EIO; 477 478 return 0; 479 } 480 481 /** 482 * mei_me_count_full_read_slots - counts read full slots. 483 * 484 * @dev: the device structure 485 * 486 * Return: -EOVERFLOW if overflow, otherwise filled slots count 487 */ 488 static int mei_me_count_full_read_slots(struct mei_device *dev) 489 { 490 struct mei_me_hw *hw = to_me_hw(dev); 491 u32 me_csr; 492 char read_ptr, write_ptr; 493 unsigned char buffer_depth, filled_slots; 494 495 me_csr = mei_me_mecsr_read(hw); 496 buffer_depth = (unsigned char)((me_csr & ME_CBD_HRA) >> 24); 497 read_ptr = (char) ((me_csr & ME_CBRP_HRA) >> 8); 498 write_ptr = (char) ((me_csr & ME_CBWP_HRA) >> 16); 499 filled_slots = (unsigned char) (write_ptr - read_ptr); 500 501 /* check for overflow */ 502 if (filled_slots > buffer_depth) 503 return -EOVERFLOW; 504 505 dev_dbg(dev->dev, "filled_slots =%08x\n", filled_slots); 506 return (int)filled_slots; 507 } 508 509 /** 510 * mei_me_read_slots - reads a message from mei device. 511 * 512 * @dev: the device structure 513 * @buffer: message buffer will be written 514 * @buffer_length: message size will be read 515 * 516 * Return: always 0 517 */ 518 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer, 519 unsigned long buffer_length) 520 { 521 struct mei_me_hw *hw = to_me_hw(dev); 522 u32 *reg_buf = (u32 *)buffer; 523 u32 hcsr; 524 525 for (; buffer_length >= sizeof(u32); buffer_length -= sizeof(u32)) 526 *reg_buf++ = mei_me_mecbrw_read(dev); 527 528 if (buffer_length > 0) { 529 u32 reg = mei_me_mecbrw_read(dev); 530 531 memcpy(reg_buf, ®, buffer_length); 532 } 533 534 hcsr = mei_hcsr_read(hw) | H_IG; 535 mei_hcsr_set(hw, hcsr); 536 return 0; 537 } 538 539 /** 540 * mei_me_pg_enter - write pg enter register 541 * 542 * @dev: the device structure 543 */ 544 static void mei_me_pg_enter(struct mei_device *dev) 545 { 546 struct mei_me_hw *hw = to_me_hw(dev); 547 u32 reg = mei_me_reg_read(hw, H_HPG_CSR); 548 549 reg |= H_HPG_CSR_PGI; 550 mei_me_reg_write(hw, H_HPG_CSR, reg); 551 } 552 553 /** 554 * mei_me_pg_exit - write pg exit register 555 * 556 * @dev: the device structure 557 */ 558 static void mei_me_pg_exit(struct mei_device *dev) 559 { 560 struct mei_me_hw *hw = to_me_hw(dev); 561 u32 reg = mei_me_reg_read(hw, H_HPG_CSR); 562 563 WARN(!(reg & H_HPG_CSR_PGI), "PGI is not set\n"); 564 565 reg |= H_HPG_CSR_PGIHEXR; 566 mei_me_reg_write(hw, H_HPG_CSR, reg); 567 } 568 569 /** 570 * mei_me_pg_set_sync - perform pg entry procedure 571 * 572 * @dev: the device structure 573 * 574 * Return: 0 on success an error code otherwise 575 */ 576 int mei_me_pg_set_sync(struct mei_device *dev) 577 { 578 struct mei_me_hw *hw = to_me_hw(dev); 579 unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT); 580 int ret; 581 582 dev->pg_event = MEI_PG_EVENT_WAIT; 583 584 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD); 585 if (ret) 586 return ret; 587 588 mutex_unlock(&dev->device_lock); 589 wait_event_timeout(dev->wait_pg, 590 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); 591 mutex_lock(&dev->device_lock); 592 593 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) { 594 mei_me_pg_enter(dev); 595 ret = 0; 596 } else { 597 ret = -ETIME; 598 } 599 600 dev->pg_event = MEI_PG_EVENT_IDLE; 601 hw->pg_state = MEI_PG_ON; 602 603 return ret; 604 } 605 606 /** 607 * mei_me_pg_unset_sync - perform pg exit procedure 608 * 609 * @dev: the device structure 610 * 611 * Return: 0 on success an error code otherwise 612 */ 613 int mei_me_pg_unset_sync(struct mei_device *dev) 614 { 615 struct mei_me_hw *hw = to_me_hw(dev); 616 unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT); 617 int ret; 618 619 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) 620 goto reply; 621 622 dev->pg_event = MEI_PG_EVENT_WAIT; 623 624 mei_me_pg_exit(dev); 625 626 mutex_unlock(&dev->device_lock); 627 wait_event_timeout(dev->wait_pg, 628 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); 629 mutex_lock(&dev->device_lock); 630 631 reply: 632 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) 633 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD); 634 else 635 ret = -ETIME; 636 637 dev->pg_event = MEI_PG_EVENT_IDLE; 638 hw->pg_state = MEI_PG_OFF; 639 640 return ret; 641 } 642 643 /** 644 * mei_me_pg_is_enabled - detect if PG is supported by HW 645 * 646 * @dev: the device structure 647 * 648 * Return: true is pg supported, false otherwise 649 */ 650 static bool mei_me_pg_is_enabled(struct mei_device *dev) 651 { 652 struct mei_me_hw *hw = to_me_hw(dev); 653 u32 reg = mei_me_reg_read(hw, ME_CSR_HA); 654 655 if ((reg & ME_PGIC_HRA) == 0) 656 goto notsupported; 657 658 if (!dev->hbm_f_pg_supported) 659 goto notsupported; 660 661 return true; 662 663 notsupported: 664 dev_dbg(dev->dev, "pg: not supported: HGP = %d hbm version %d.%d ?= %d.%d\n", 665 !!(reg & ME_PGIC_HRA), 666 dev->version.major_version, 667 dev->version.minor_version, 668 HBM_MAJOR_VERSION_PGI, 669 HBM_MINOR_VERSION_PGI); 670 671 return false; 672 } 673 674 /** 675 * mei_me_irq_quick_handler - The ISR of the MEI device 676 * 677 * @irq: The irq number 678 * @dev_id: pointer to the device structure 679 * 680 * Return: irqreturn_t 681 */ 682 683 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id) 684 { 685 struct mei_device *dev = (struct mei_device *) dev_id; 686 struct mei_me_hw *hw = to_me_hw(dev); 687 u32 csr_reg = mei_hcsr_read(hw); 688 689 if ((csr_reg & H_IS) != H_IS) 690 return IRQ_NONE; 691 692 /* clear H_IS bit in H_CSR */ 693 mei_me_reg_write(hw, H_CSR, csr_reg); 694 695 return IRQ_WAKE_THREAD; 696 } 697 698 /** 699 * mei_me_irq_thread_handler - function called after ISR to handle the interrupt 700 * processing. 701 * 702 * @irq: The irq number 703 * @dev_id: pointer to the device structure 704 * 705 * Return: irqreturn_t 706 * 707 */ 708 irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id) 709 { 710 struct mei_device *dev = (struct mei_device *) dev_id; 711 struct mei_cl_cb complete_list; 712 s32 slots; 713 int rets = 0; 714 715 dev_dbg(dev->dev, "function called after ISR to handle the interrupt processing.\n"); 716 /* initialize our complete list */ 717 mutex_lock(&dev->device_lock); 718 mei_io_list_init(&complete_list); 719 720 /* Ack the interrupt here 721 * In case of MSI we don't go through the quick handler */ 722 if (pci_dev_msi_enabled(to_pci_dev(dev->dev))) 723 mei_clear_interrupts(dev); 724 725 /* check if ME wants a reset */ 726 if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) { 727 dev_warn(dev->dev, "FW not ready: resetting.\n"); 728 schedule_work(&dev->reset_work); 729 goto end; 730 } 731 732 /* check if we need to start the dev */ 733 if (!mei_host_is_ready(dev)) { 734 if (mei_hw_is_ready(dev)) { 735 dev_dbg(dev->dev, "we need to start the dev.\n"); 736 dev->recvd_hw_ready = true; 737 wake_up(&dev->wait_hw_ready); 738 } else { 739 dev_dbg(dev->dev, "Spurious Interrupt\n"); 740 } 741 goto end; 742 } 743 /* check slots available for reading */ 744 slots = mei_count_full_read_slots(dev); 745 while (slots > 0) { 746 dev_dbg(dev->dev, "slots to read = %08x\n", slots); 747 rets = mei_irq_read_handler(dev, &complete_list, &slots); 748 /* There is a race between ME write and interrupt delivery: 749 * Not all data is always available immediately after the 750 * interrupt, so try to read again on the next interrupt. 751 */ 752 if (rets == -ENODATA) 753 break; 754 755 if (rets && dev->dev_state != MEI_DEV_RESETTING) { 756 dev_err(dev->dev, "mei_irq_read_handler ret = %d.\n", 757 rets); 758 schedule_work(&dev->reset_work); 759 goto end; 760 } 761 } 762 763 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); 764 765 /* 766 * During PG handshake only allowed write is the replay to the 767 * PG exit message, so block calling write function 768 * if the pg state is not idle 769 */ 770 if (dev->pg_event == MEI_PG_EVENT_IDLE) { 771 rets = mei_irq_write_handler(dev, &complete_list); 772 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); 773 } 774 775 mei_irq_compl_handler(dev, &complete_list); 776 777 end: 778 dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets); 779 mutex_unlock(&dev->device_lock); 780 return IRQ_HANDLED; 781 } 782 783 static const struct mei_hw_ops mei_me_hw_ops = { 784 785 .fw_status = mei_me_fw_status, 786 .pg_state = mei_me_pg_state, 787 788 .host_is_ready = mei_me_host_is_ready, 789 790 .hw_is_ready = mei_me_hw_is_ready, 791 .hw_reset = mei_me_hw_reset, 792 .hw_config = mei_me_hw_config, 793 .hw_start = mei_me_hw_start, 794 795 .pg_is_enabled = mei_me_pg_is_enabled, 796 797 .intr_clear = mei_me_intr_clear, 798 .intr_enable = mei_me_intr_enable, 799 .intr_disable = mei_me_intr_disable, 800 801 .hbuf_free_slots = mei_me_hbuf_empty_slots, 802 .hbuf_is_ready = mei_me_hbuf_is_empty, 803 .hbuf_max_len = mei_me_hbuf_max_len, 804 805 .write = mei_me_write_message, 806 807 .rdbuf_full_slots = mei_me_count_full_read_slots, 808 .read_hdr = mei_me_mecbrw_read, 809 .read = mei_me_read_slots 810 }; 811 812 static bool mei_me_fw_type_nm(struct pci_dev *pdev) 813 { 814 u32 reg; 815 816 pci_read_config_dword(pdev, PCI_CFG_HFS_2, ®); 817 /* make sure that bit 9 (NM) is up and bit 10 (DM) is down */ 818 return (reg & 0x600) == 0x200; 819 } 820 821 #define MEI_CFG_FW_NM \ 822 .quirk_probe = mei_me_fw_type_nm 823 824 static bool mei_me_fw_type_sps(struct pci_dev *pdev) 825 { 826 u32 reg; 827 /* Read ME FW Status check for SPS Firmware */ 828 pci_read_config_dword(pdev, PCI_CFG_HFS_1, ®); 829 /* if bits [19:16] = 15, running SPS Firmware */ 830 return (reg & 0xf0000) == 0xf0000; 831 } 832 833 #define MEI_CFG_FW_SPS \ 834 .quirk_probe = mei_me_fw_type_sps 835 836 837 #define MEI_CFG_LEGACY_HFS \ 838 .fw_status.count = 0 839 840 #define MEI_CFG_ICH_HFS \ 841 .fw_status.count = 1, \ 842 .fw_status.status[0] = PCI_CFG_HFS_1 843 844 #define MEI_CFG_PCH_HFS \ 845 .fw_status.count = 2, \ 846 .fw_status.status[0] = PCI_CFG_HFS_1, \ 847 .fw_status.status[1] = PCI_CFG_HFS_2 848 849 #define MEI_CFG_PCH8_HFS \ 850 .fw_status.count = 6, \ 851 .fw_status.status[0] = PCI_CFG_HFS_1, \ 852 .fw_status.status[1] = PCI_CFG_HFS_2, \ 853 .fw_status.status[2] = PCI_CFG_HFS_3, \ 854 .fw_status.status[3] = PCI_CFG_HFS_4, \ 855 .fw_status.status[4] = PCI_CFG_HFS_5, \ 856 .fw_status.status[5] = PCI_CFG_HFS_6 857 858 /* ICH Legacy devices */ 859 const struct mei_cfg mei_me_legacy_cfg = { 860 MEI_CFG_LEGACY_HFS, 861 }; 862 863 /* ICH devices */ 864 const struct mei_cfg mei_me_ich_cfg = { 865 MEI_CFG_ICH_HFS, 866 }; 867 868 /* PCH devices */ 869 const struct mei_cfg mei_me_pch_cfg = { 870 MEI_CFG_PCH_HFS, 871 }; 872 873 874 /* PCH Cougar Point and Patsburg with quirk for Node Manager exclusion */ 875 const struct mei_cfg mei_me_pch_cpt_pbg_cfg = { 876 MEI_CFG_PCH_HFS, 877 MEI_CFG_FW_NM, 878 }; 879 880 /* PCH8 Lynx Point and newer devices */ 881 const struct mei_cfg mei_me_pch8_cfg = { 882 MEI_CFG_PCH8_HFS, 883 }; 884 885 /* PCH8 Lynx Point with quirk for SPS Firmware exclusion */ 886 const struct mei_cfg mei_me_pch8_sps_cfg = { 887 MEI_CFG_PCH8_HFS, 888 MEI_CFG_FW_SPS, 889 }; 890 891 /** 892 * mei_me_dev_init - allocates and initializes the mei device structure 893 * 894 * @pdev: The pci device structure 895 * @cfg: per device generation config 896 * 897 * Return: The mei_device_device pointer on success, NULL on failure. 898 */ 899 struct mei_device *mei_me_dev_init(struct pci_dev *pdev, 900 const struct mei_cfg *cfg) 901 { 902 struct mei_device *dev; 903 struct mei_me_hw *hw; 904 905 dev = kzalloc(sizeof(struct mei_device) + 906 sizeof(struct mei_me_hw), GFP_KERNEL); 907 if (!dev) 908 return NULL; 909 hw = to_me_hw(dev); 910 911 mei_device_init(dev, &pdev->dev, &mei_me_hw_ops); 912 hw->cfg = cfg; 913 return dev; 914 } 915 916