1 /* 2 * 3 * Intel Management Engine Interface (Intel MEI) Linux driver 4 * Copyright (c) 2003-2012, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 */ 16 17 #include <linux/pci.h> 18 19 #include <linux/kthread.h> 20 #include <linux/interrupt.h> 21 22 #include "mei_dev.h" 23 #include "hbm.h" 24 25 #include "hw-me.h" 26 #include "hw-me-regs.h" 27 28 /** 29 * mei_me_reg_read - Reads 32bit data from the mei device 30 * 31 * @hw: the me hardware structure 32 * @offset: offset from which to read the data 33 * 34 * Return: register value (u32) 35 */ 36 static inline u32 mei_me_reg_read(const struct mei_me_hw *hw, 37 unsigned long offset) 38 { 39 return ioread32(hw->mem_addr + offset); 40 } 41 42 43 /** 44 * mei_me_reg_write - Writes 32bit data to the mei device 45 * 46 * @hw: the me hardware structure 47 * @offset: offset from which to write the data 48 * @value: register value to write (u32) 49 */ 50 static inline void mei_me_reg_write(const struct mei_me_hw *hw, 51 unsigned long offset, u32 value) 52 { 53 iowrite32(value, hw->mem_addr + offset); 54 } 55 56 /** 57 * mei_me_mecbrw_read - Reads 32bit data from ME circular buffer 58 * read window register 59 * 60 * @dev: the device structure 61 * 62 * Return: ME_CB_RW register value (u32) 63 */ 64 static u32 mei_me_mecbrw_read(const struct mei_device *dev) 65 { 66 return mei_me_reg_read(to_me_hw(dev), ME_CB_RW); 67 } 68 /** 69 * mei_me_mecsr_read - Reads 32bit data from the ME CSR 70 * 71 * @hw: the me hardware structure 72 * 73 * Return: ME_CSR_HA register value (u32) 74 */ 75 static inline u32 mei_me_mecsr_read(const struct mei_me_hw *hw) 76 { 77 return mei_me_reg_read(hw, ME_CSR_HA); 78 } 79 80 /** 81 * mei_hcsr_read - Reads 32bit data from the host CSR 82 * 83 * @hw: the me hardware structure 84 * 85 * Return: H_CSR register value (u32) 86 */ 87 static inline u32 mei_hcsr_read(const struct mei_me_hw *hw) 88 { 89 return mei_me_reg_read(hw, H_CSR); 90 } 91 92 /** 93 * mei_hcsr_set - writes H_CSR register to the mei device, 94 * and ignores the H_IS bit for it is write-one-to-zero. 95 * 96 * @hw: the me hardware structure 97 * @hcsr: new register value 98 */ 99 static inline void mei_hcsr_set(struct mei_me_hw *hw, u32 hcsr) 100 { 101 hcsr &= ~H_IS; 102 mei_me_reg_write(hw, H_CSR, hcsr); 103 } 104 105 /** 106 * mei_me_fw_status - read fw status register from pci config space 107 * 108 * @dev: mei device 109 * @fw_status: fw status register values 110 * 111 * Return: 0 on success, error otherwise 112 */ 113 static int mei_me_fw_status(struct mei_device *dev, 114 struct mei_fw_status *fw_status) 115 { 116 struct pci_dev *pdev = to_pci_dev(dev->dev); 117 struct mei_me_hw *hw = to_me_hw(dev); 118 const struct mei_fw_status *fw_src = &hw->cfg->fw_status; 119 int ret; 120 int i; 121 122 if (!fw_status) 123 return -EINVAL; 124 125 fw_status->count = fw_src->count; 126 for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) { 127 ret = pci_read_config_dword(pdev, 128 fw_src->status[i], &fw_status->status[i]); 129 if (ret) 130 return ret; 131 } 132 133 return 0; 134 } 135 136 /** 137 * mei_me_hw_config - configure hw dependent settings 138 * 139 * @dev: mei device 140 */ 141 static void mei_me_hw_config(struct mei_device *dev) 142 { 143 struct mei_me_hw *hw = to_me_hw(dev); 144 u32 hcsr = mei_hcsr_read(to_me_hw(dev)); 145 /* Doesn't change in runtime */ 146 dev->hbuf_depth = (hcsr & H_CBD) >> 24; 147 148 hw->pg_state = MEI_PG_OFF; 149 } 150 151 /** 152 * mei_me_pg_state - translate internal pg state 153 * to the mei power gating state 154 * 155 * @dev: mei device 156 * 157 * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise 158 */ 159 static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev) 160 { 161 struct mei_me_hw *hw = to_me_hw(dev); 162 163 return hw->pg_state; 164 } 165 166 /** 167 * mei_me_intr_clear - clear and stop interrupts 168 * 169 * @dev: the device structure 170 */ 171 static void mei_me_intr_clear(struct mei_device *dev) 172 { 173 struct mei_me_hw *hw = to_me_hw(dev); 174 u32 hcsr = mei_hcsr_read(hw); 175 176 if ((hcsr & H_IS) == H_IS) 177 mei_me_reg_write(hw, H_CSR, hcsr); 178 } 179 /** 180 * mei_me_intr_enable - enables mei device interrupts 181 * 182 * @dev: the device structure 183 */ 184 static void mei_me_intr_enable(struct mei_device *dev) 185 { 186 struct mei_me_hw *hw = to_me_hw(dev); 187 u32 hcsr = mei_hcsr_read(hw); 188 189 hcsr |= H_IE; 190 mei_hcsr_set(hw, hcsr); 191 } 192 193 /** 194 * mei_me_intr_disable - disables mei device interrupts 195 * 196 * @dev: the device structure 197 */ 198 static void mei_me_intr_disable(struct mei_device *dev) 199 { 200 struct mei_me_hw *hw = to_me_hw(dev); 201 u32 hcsr = mei_hcsr_read(hw); 202 203 hcsr &= ~H_IE; 204 mei_hcsr_set(hw, hcsr); 205 } 206 207 /** 208 * mei_me_hw_reset_release - release device from the reset 209 * 210 * @dev: the device structure 211 */ 212 static void mei_me_hw_reset_release(struct mei_device *dev) 213 { 214 struct mei_me_hw *hw = to_me_hw(dev); 215 u32 hcsr = mei_hcsr_read(hw); 216 217 hcsr |= H_IG; 218 hcsr &= ~H_RST; 219 mei_hcsr_set(hw, hcsr); 220 221 /* complete this write before we set host ready on another CPU */ 222 mmiowb(); 223 } 224 /** 225 * mei_me_hw_reset - resets fw via mei csr register. 226 * 227 * @dev: the device structure 228 * @intr_enable: if interrupt should be enabled after reset. 229 * 230 * Return: always 0 231 */ 232 static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable) 233 { 234 struct mei_me_hw *hw = to_me_hw(dev); 235 u32 hcsr = mei_hcsr_read(hw); 236 237 hcsr |= H_RST | H_IG | H_IS; 238 239 if (intr_enable) 240 hcsr |= H_IE; 241 else 242 hcsr &= ~H_IE; 243 244 dev->recvd_hw_ready = false; 245 mei_me_reg_write(hw, H_CSR, hcsr); 246 247 /* 248 * Host reads the H_CSR once to ensure that the 249 * posted write to H_CSR completes. 250 */ 251 hcsr = mei_hcsr_read(hw); 252 253 if ((hcsr & H_RST) == 0) 254 dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr); 255 256 if ((hcsr & H_RDY) == H_RDY) 257 dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr); 258 259 if (intr_enable == false) 260 mei_me_hw_reset_release(dev); 261 262 return 0; 263 } 264 265 /** 266 * mei_me_host_set_ready - enable device 267 * 268 * @dev: mei device 269 */ 270 static void mei_me_host_set_ready(struct mei_device *dev) 271 { 272 struct mei_me_hw *hw = to_me_hw(dev); 273 u32 hcsr = mei_hcsr_read(hw); 274 275 hcsr |= H_IE | H_IG | H_RDY; 276 mei_hcsr_set(hw, hcsr); 277 } 278 279 /** 280 * mei_me_host_is_ready - check whether the host has turned ready 281 * 282 * @dev: mei device 283 * Return: bool 284 */ 285 static bool mei_me_host_is_ready(struct mei_device *dev) 286 { 287 struct mei_me_hw *hw = to_me_hw(dev); 288 u32 hcsr = mei_hcsr_read(hw); 289 290 return (hcsr & H_RDY) == H_RDY; 291 } 292 293 /** 294 * mei_me_hw_is_ready - check whether the me(hw) has turned ready 295 * 296 * @dev: mei device 297 * Return: bool 298 */ 299 static bool mei_me_hw_is_ready(struct mei_device *dev) 300 { 301 struct mei_me_hw *hw = to_me_hw(dev); 302 u32 mecsr = mei_me_mecsr_read(hw); 303 304 return (mecsr & ME_RDY_HRA) == ME_RDY_HRA; 305 } 306 307 /** 308 * mei_me_hw_ready_wait - wait until the me(hw) has turned ready 309 * or timeout is reached 310 * 311 * @dev: mei device 312 * Return: 0 on success, error otherwise 313 */ 314 static int mei_me_hw_ready_wait(struct mei_device *dev) 315 { 316 mutex_unlock(&dev->device_lock); 317 wait_event_timeout(dev->wait_hw_ready, 318 dev->recvd_hw_ready, 319 mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT)); 320 mutex_lock(&dev->device_lock); 321 if (!dev->recvd_hw_ready) { 322 dev_err(dev->dev, "wait hw ready failed\n"); 323 return -ETIME; 324 } 325 326 dev->recvd_hw_ready = false; 327 return 0; 328 } 329 330 /** 331 * mei_me_hw_start - hw start routine 332 * 333 * @dev: mei device 334 * Return: 0 on success, error otherwise 335 */ 336 static int mei_me_hw_start(struct mei_device *dev) 337 { 338 int ret = mei_me_hw_ready_wait(dev); 339 340 if (ret) 341 return ret; 342 dev_dbg(dev->dev, "hw is ready\n"); 343 344 mei_me_host_set_ready(dev); 345 return ret; 346 } 347 348 349 /** 350 * mei_hbuf_filled_slots - gets number of device filled buffer slots 351 * 352 * @dev: the device structure 353 * 354 * Return: number of filled slots 355 */ 356 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev) 357 { 358 struct mei_me_hw *hw = to_me_hw(dev); 359 u32 hcsr; 360 char read_ptr, write_ptr; 361 362 hcsr = mei_hcsr_read(hw); 363 364 read_ptr = (char) ((hcsr & H_CBRP) >> 8); 365 write_ptr = (char) ((hcsr & H_CBWP) >> 16); 366 367 return (unsigned char) (write_ptr - read_ptr); 368 } 369 370 /** 371 * mei_me_hbuf_is_empty - checks if host buffer is empty. 372 * 373 * @dev: the device structure 374 * 375 * Return: true if empty, false - otherwise. 376 */ 377 static bool mei_me_hbuf_is_empty(struct mei_device *dev) 378 { 379 return mei_hbuf_filled_slots(dev) == 0; 380 } 381 382 /** 383 * mei_me_hbuf_empty_slots - counts write empty slots. 384 * 385 * @dev: the device structure 386 * 387 * Return: -EOVERFLOW if overflow, otherwise empty slots count 388 */ 389 static int mei_me_hbuf_empty_slots(struct mei_device *dev) 390 { 391 unsigned char filled_slots, empty_slots; 392 393 filled_slots = mei_hbuf_filled_slots(dev); 394 empty_slots = dev->hbuf_depth - filled_slots; 395 396 /* check for overflow */ 397 if (filled_slots > dev->hbuf_depth) 398 return -EOVERFLOW; 399 400 return empty_slots; 401 } 402 403 /** 404 * mei_me_hbuf_max_len - returns size of hw buffer. 405 * 406 * @dev: the device structure 407 * 408 * Return: size of hw buffer in bytes 409 */ 410 static size_t mei_me_hbuf_max_len(const struct mei_device *dev) 411 { 412 return dev->hbuf_depth * sizeof(u32) - sizeof(struct mei_msg_hdr); 413 } 414 415 416 /** 417 * mei_me_write_message - writes a message to mei device. 418 * 419 * @dev: the device structure 420 * @header: mei HECI header of message 421 * @buf: message payload will be written 422 * 423 * Return: -EIO if write has failed 424 */ 425 static int mei_me_write_message(struct mei_device *dev, 426 struct mei_msg_hdr *header, 427 unsigned char *buf) 428 { 429 struct mei_me_hw *hw = to_me_hw(dev); 430 unsigned long rem; 431 unsigned long length = header->length; 432 u32 *reg_buf = (u32 *)buf; 433 u32 hcsr; 434 u32 dw_cnt; 435 int i; 436 int empty_slots; 437 438 dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header)); 439 440 empty_slots = mei_hbuf_empty_slots(dev); 441 dev_dbg(dev->dev, "empty slots = %hu.\n", empty_slots); 442 443 dw_cnt = mei_data2slots(length); 444 if (empty_slots < 0 || dw_cnt > empty_slots) 445 return -EMSGSIZE; 446 447 mei_me_reg_write(hw, H_CB_WW, *((u32 *) header)); 448 449 for (i = 0; i < length / 4; i++) 450 mei_me_reg_write(hw, H_CB_WW, reg_buf[i]); 451 452 rem = length & 0x3; 453 if (rem > 0) { 454 u32 reg = 0; 455 456 memcpy(®, &buf[length - rem], rem); 457 mei_me_reg_write(hw, H_CB_WW, reg); 458 } 459 460 hcsr = mei_hcsr_read(hw) | H_IG; 461 mei_hcsr_set(hw, hcsr); 462 if (!mei_me_hw_is_ready(dev)) 463 return -EIO; 464 465 return 0; 466 } 467 468 /** 469 * mei_me_count_full_read_slots - counts read full slots. 470 * 471 * @dev: the device structure 472 * 473 * Return: -EOVERFLOW if overflow, otherwise filled slots count 474 */ 475 static int mei_me_count_full_read_slots(struct mei_device *dev) 476 { 477 struct mei_me_hw *hw = to_me_hw(dev); 478 u32 me_csr; 479 char read_ptr, write_ptr; 480 unsigned char buffer_depth, filled_slots; 481 482 me_csr = mei_me_mecsr_read(hw); 483 buffer_depth = (unsigned char)((me_csr & ME_CBD_HRA) >> 24); 484 read_ptr = (char) ((me_csr & ME_CBRP_HRA) >> 8); 485 write_ptr = (char) ((me_csr & ME_CBWP_HRA) >> 16); 486 filled_slots = (unsigned char) (write_ptr - read_ptr); 487 488 /* check for overflow */ 489 if (filled_slots > buffer_depth) 490 return -EOVERFLOW; 491 492 dev_dbg(dev->dev, "filled_slots =%08x\n", filled_slots); 493 return (int)filled_slots; 494 } 495 496 /** 497 * mei_me_read_slots - reads a message from mei device. 498 * 499 * @dev: the device structure 500 * @buffer: message buffer will be written 501 * @buffer_length: message size will be read 502 * 503 * Return: always 0 504 */ 505 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer, 506 unsigned long buffer_length) 507 { 508 struct mei_me_hw *hw = to_me_hw(dev); 509 u32 *reg_buf = (u32 *)buffer; 510 u32 hcsr; 511 512 for (; buffer_length >= sizeof(u32); buffer_length -= sizeof(u32)) 513 *reg_buf++ = mei_me_mecbrw_read(dev); 514 515 if (buffer_length > 0) { 516 u32 reg = mei_me_mecbrw_read(dev); 517 518 memcpy(reg_buf, ®, buffer_length); 519 } 520 521 hcsr = mei_hcsr_read(hw) | H_IG; 522 mei_hcsr_set(hw, hcsr); 523 return 0; 524 } 525 526 /** 527 * mei_me_pg_enter - write pg enter register 528 * 529 * @dev: the device structure 530 */ 531 static void mei_me_pg_enter(struct mei_device *dev) 532 { 533 struct mei_me_hw *hw = to_me_hw(dev); 534 u32 reg = mei_me_reg_read(hw, H_HPG_CSR); 535 536 reg |= H_HPG_CSR_PGI; 537 mei_me_reg_write(hw, H_HPG_CSR, reg); 538 } 539 540 /** 541 * mei_me_pg_exit - write pg exit register 542 * 543 * @dev: the device structure 544 */ 545 static void mei_me_pg_exit(struct mei_device *dev) 546 { 547 struct mei_me_hw *hw = to_me_hw(dev); 548 u32 reg = mei_me_reg_read(hw, H_HPG_CSR); 549 550 WARN(!(reg & H_HPG_CSR_PGI), "PGI is not set\n"); 551 552 reg |= H_HPG_CSR_PGIHEXR; 553 mei_me_reg_write(hw, H_HPG_CSR, reg); 554 } 555 556 /** 557 * mei_me_pg_set_sync - perform pg entry procedure 558 * 559 * @dev: the device structure 560 * 561 * Return: 0 on success an error code otherwise 562 */ 563 int mei_me_pg_set_sync(struct mei_device *dev) 564 { 565 struct mei_me_hw *hw = to_me_hw(dev); 566 unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT); 567 int ret; 568 569 dev->pg_event = MEI_PG_EVENT_WAIT; 570 571 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD); 572 if (ret) 573 return ret; 574 575 mutex_unlock(&dev->device_lock); 576 wait_event_timeout(dev->wait_pg, 577 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); 578 mutex_lock(&dev->device_lock); 579 580 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) { 581 mei_me_pg_enter(dev); 582 ret = 0; 583 } else { 584 ret = -ETIME; 585 } 586 587 dev->pg_event = MEI_PG_EVENT_IDLE; 588 hw->pg_state = MEI_PG_ON; 589 590 return ret; 591 } 592 593 /** 594 * mei_me_pg_unset_sync - perform pg exit procedure 595 * 596 * @dev: the device structure 597 * 598 * Return: 0 on success an error code otherwise 599 */ 600 int mei_me_pg_unset_sync(struct mei_device *dev) 601 { 602 struct mei_me_hw *hw = to_me_hw(dev); 603 unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT); 604 int ret; 605 606 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) 607 goto reply; 608 609 dev->pg_event = MEI_PG_EVENT_WAIT; 610 611 mei_me_pg_exit(dev); 612 613 mutex_unlock(&dev->device_lock); 614 wait_event_timeout(dev->wait_pg, 615 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); 616 mutex_lock(&dev->device_lock); 617 618 reply: 619 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) 620 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD); 621 else 622 ret = -ETIME; 623 624 dev->pg_event = MEI_PG_EVENT_IDLE; 625 hw->pg_state = MEI_PG_OFF; 626 627 return ret; 628 } 629 630 /** 631 * mei_me_pg_is_enabled - detect if PG is supported by HW 632 * 633 * @dev: the device structure 634 * 635 * Return: true is pg supported, false otherwise 636 */ 637 static bool mei_me_pg_is_enabled(struct mei_device *dev) 638 { 639 struct mei_me_hw *hw = to_me_hw(dev); 640 u32 reg = mei_me_reg_read(hw, ME_CSR_HA); 641 642 if ((reg & ME_PGIC_HRA) == 0) 643 goto notsupported; 644 645 if (!dev->hbm_f_pg_supported) 646 goto notsupported; 647 648 return true; 649 650 notsupported: 651 dev_dbg(dev->dev, "pg: not supported: HGP = %d hbm version %d.%d ?= %d.%d\n", 652 !!(reg & ME_PGIC_HRA), 653 dev->version.major_version, 654 dev->version.minor_version, 655 HBM_MAJOR_VERSION_PGI, 656 HBM_MINOR_VERSION_PGI); 657 658 return false; 659 } 660 661 /** 662 * mei_me_irq_quick_handler - The ISR of the MEI device 663 * 664 * @irq: The irq number 665 * @dev_id: pointer to the device structure 666 * 667 * Return: irqreturn_t 668 */ 669 670 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id) 671 { 672 struct mei_device *dev = (struct mei_device *) dev_id; 673 struct mei_me_hw *hw = to_me_hw(dev); 674 u32 csr_reg = mei_hcsr_read(hw); 675 676 if ((csr_reg & H_IS) != H_IS) 677 return IRQ_NONE; 678 679 /* clear H_IS bit in H_CSR */ 680 mei_me_reg_write(hw, H_CSR, csr_reg); 681 682 return IRQ_WAKE_THREAD; 683 } 684 685 /** 686 * mei_me_irq_thread_handler - function called after ISR to handle the interrupt 687 * processing. 688 * 689 * @irq: The irq number 690 * @dev_id: pointer to the device structure 691 * 692 * Return: irqreturn_t 693 * 694 */ 695 irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id) 696 { 697 struct mei_device *dev = (struct mei_device *) dev_id; 698 struct mei_cl_cb complete_list; 699 s32 slots; 700 int rets = 0; 701 702 dev_dbg(dev->dev, "function called after ISR to handle the interrupt processing.\n"); 703 /* initialize our complete list */ 704 mutex_lock(&dev->device_lock); 705 mei_io_list_init(&complete_list); 706 707 /* Ack the interrupt here 708 * In case of MSI we don't go through the quick handler */ 709 if (pci_dev_msi_enabled(to_pci_dev(dev->dev))) 710 mei_clear_interrupts(dev); 711 712 /* check if ME wants a reset */ 713 if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) { 714 dev_warn(dev->dev, "FW not ready: resetting.\n"); 715 schedule_work(&dev->reset_work); 716 goto end; 717 } 718 719 /* check if we need to start the dev */ 720 if (!mei_host_is_ready(dev)) { 721 if (mei_hw_is_ready(dev)) { 722 mei_me_hw_reset_release(dev); 723 dev_dbg(dev->dev, "we need to start the dev.\n"); 724 725 dev->recvd_hw_ready = true; 726 wake_up(&dev->wait_hw_ready); 727 } else { 728 dev_dbg(dev->dev, "Spurious Interrupt\n"); 729 } 730 goto end; 731 } 732 /* check slots available for reading */ 733 slots = mei_count_full_read_slots(dev); 734 while (slots > 0) { 735 dev_dbg(dev->dev, "slots to read = %08x\n", slots); 736 rets = mei_irq_read_handler(dev, &complete_list, &slots); 737 /* There is a race between ME write and interrupt delivery: 738 * Not all data is always available immediately after the 739 * interrupt, so try to read again on the next interrupt. 740 */ 741 if (rets == -ENODATA) 742 break; 743 744 if (rets && dev->dev_state != MEI_DEV_RESETTING) { 745 dev_err(dev->dev, "mei_irq_read_handler ret = %d.\n", 746 rets); 747 schedule_work(&dev->reset_work); 748 goto end; 749 } 750 } 751 752 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); 753 754 /* 755 * During PG handshake only allowed write is the replay to the 756 * PG exit message, so block calling write function 757 * if the pg state is not idle 758 */ 759 if (dev->pg_event == MEI_PG_EVENT_IDLE) { 760 rets = mei_irq_write_handler(dev, &complete_list); 761 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); 762 } 763 764 mei_irq_compl_handler(dev, &complete_list); 765 766 end: 767 dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets); 768 mutex_unlock(&dev->device_lock); 769 return IRQ_HANDLED; 770 } 771 772 static const struct mei_hw_ops mei_me_hw_ops = { 773 774 .fw_status = mei_me_fw_status, 775 .pg_state = mei_me_pg_state, 776 777 .host_is_ready = mei_me_host_is_ready, 778 779 .hw_is_ready = mei_me_hw_is_ready, 780 .hw_reset = mei_me_hw_reset, 781 .hw_config = mei_me_hw_config, 782 .hw_start = mei_me_hw_start, 783 784 .pg_is_enabled = mei_me_pg_is_enabled, 785 786 .intr_clear = mei_me_intr_clear, 787 .intr_enable = mei_me_intr_enable, 788 .intr_disable = mei_me_intr_disable, 789 790 .hbuf_free_slots = mei_me_hbuf_empty_slots, 791 .hbuf_is_ready = mei_me_hbuf_is_empty, 792 .hbuf_max_len = mei_me_hbuf_max_len, 793 794 .write = mei_me_write_message, 795 796 .rdbuf_full_slots = mei_me_count_full_read_slots, 797 .read_hdr = mei_me_mecbrw_read, 798 .read = mei_me_read_slots 799 }; 800 801 static bool mei_me_fw_type_nm(struct pci_dev *pdev) 802 { 803 u32 reg; 804 805 pci_read_config_dword(pdev, PCI_CFG_HFS_2, ®); 806 /* make sure that bit 9 (NM) is up and bit 10 (DM) is down */ 807 return (reg & 0x600) == 0x200; 808 } 809 810 #define MEI_CFG_FW_NM \ 811 .quirk_probe = mei_me_fw_type_nm 812 813 static bool mei_me_fw_type_sps(struct pci_dev *pdev) 814 { 815 u32 reg; 816 /* Read ME FW Status check for SPS Firmware */ 817 pci_read_config_dword(pdev, PCI_CFG_HFS_1, ®); 818 /* if bits [19:16] = 15, running SPS Firmware */ 819 return (reg & 0xf0000) == 0xf0000; 820 } 821 822 #define MEI_CFG_FW_SPS \ 823 .quirk_probe = mei_me_fw_type_sps 824 825 826 #define MEI_CFG_LEGACY_HFS \ 827 .fw_status.count = 0 828 829 #define MEI_CFG_ICH_HFS \ 830 .fw_status.count = 1, \ 831 .fw_status.status[0] = PCI_CFG_HFS_1 832 833 #define MEI_CFG_PCH_HFS \ 834 .fw_status.count = 2, \ 835 .fw_status.status[0] = PCI_CFG_HFS_1, \ 836 .fw_status.status[1] = PCI_CFG_HFS_2 837 838 #define MEI_CFG_PCH8_HFS \ 839 .fw_status.count = 6, \ 840 .fw_status.status[0] = PCI_CFG_HFS_1, \ 841 .fw_status.status[1] = PCI_CFG_HFS_2, \ 842 .fw_status.status[2] = PCI_CFG_HFS_3, \ 843 .fw_status.status[3] = PCI_CFG_HFS_4, \ 844 .fw_status.status[4] = PCI_CFG_HFS_5, \ 845 .fw_status.status[5] = PCI_CFG_HFS_6 846 847 /* ICH Legacy devices */ 848 const struct mei_cfg mei_me_legacy_cfg = { 849 MEI_CFG_LEGACY_HFS, 850 }; 851 852 /* ICH devices */ 853 const struct mei_cfg mei_me_ich_cfg = { 854 MEI_CFG_ICH_HFS, 855 }; 856 857 /* PCH devices */ 858 const struct mei_cfg mei_me_pch_cfg = { 859 MEI_CFG_PCH_HFS, 860 }; 861 862 863 /* PCH Cougar Point and Patsburg with quirk for Node Manager exclusion */ 864 const struct mei_cfg mei_me_pch_cpt_pbg_cfg = { 865 MEI_CFG_PCH_HFS, 866 MEI_CFG_FW_NM, 867 }; 868 869 /* PCH8 Lynx Point and newer devices */ 870 const struct mei_cfg mei_me_pch8_cfg = { 871 MEI_CFG_PCH8_HFS, 872 }; 873 874 /* PCH8 Lynx Point with quirk for SPS Firmware exclusion */ 875 const struct mei_cfg mei_me_pch8_sps_cfg = { 876 MEI_CFG_PCH8_HFS, 877 MEI_CFG_FW_SPS, 878 }; 879 880 /** 881 * mei_me_dev_init - allocates and initializes the mei device structure 882 * 883 * @pdev: The pci device structure 884 * @cfg: per device generation config 885 * 886 * Return: The mei_device_device pointer on success, NULL on failure. 887 */ 888 struct mei_device *mei_me_dev_init(struct pci_dev *pdev, 889 const struct mei_cfg *cfg) 890 { 891 struct mei_device *dev; 892 struct mei_me_hw *hw; 893 894 dev = kzalloc(sizeof(struct mei_device) + 895 sizeof(struct mei_me_hw), GFP_KERNEL); 896 if (!dev) 897 return NULL; 898 hw = to_me_hw(dev); 899 900 mei_device_init(dev, &pdev->dev, &mei_me_hw_ops); 901 hw->cfg = cfg; 902 return dev; 903 } 904 905