1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2003-2022, Intel Corporation. All rights reserved. 4 * Intel Management Engine Interface (Intel MEI) Linux driver 5 */ 6 7 #include <linux/pci.h> 8 9 #include <linux/kthread.h> 10 #include <linux/interrupt.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/sizes.h> 13 #include <linux/delay.h> 14 15 #include "mei_dev.h" 16 #include "hbm.h" 17 18 #include "hw-me.h" 19 #include "hw-me-regs.h" 20 21 #include "mei-trace.h" 22 23 /** 24 * mei_me_reg_read - Reads 32bit data from the mei device 25 * 26 * @hw: the me hardware structure 27 * @offset: offset from which to read the data 28 * 29 * Return: register value (u32) 30 */ 31 static inline u32 mei_me_reg_read(const struct mei_me_hw *hw, 32 unsigned long offset) 33 { 34 return ioread32(hw->mem_addr + offset); 35 } 36 37 38 /** 39 * mei_me_reg_write - Writes 32bit data to the mei device 40 * 41 * @hw: the me hardware structure 42 * @offset: offset from which to write the data 43 * @value: register value to write (u32) 44 */ 45 static inline void mei_me_reg_write(const struct mei_me_hw *hw, 46 unsigned long offset, u32 value) 47 { 48 iowrite32(value, hw->mem_addr + offset); 49 } 50 51 /** 52 * mei_me_mecbrw_read - Reads 32bit data from ME circular buffer 53 * read window register 54 * 55 * @dev: the device structure 56 * 57 * Return: ME_CB_RW register value (u32) 58 */ 59 static inline u32 mei_me_mecbrw_read(const struct mei_device *dev) 60 { 61 return mei_me_reg_read(to_me_hw(dev), ME_CB_RW); 62 } 63 64 /** 65 * mei_me_hcbww_write - write 32bit data to the host circular buffer 66 * 67 * @dev: the device structure 68 * @data: 32bit data to be written to the host circular buffer 69 */ 70 static inline void mei_me_hcbww_write(struct mei_device *dev, u32 data) 71 { 72 mei_me_reg_write(to_me_hw(dev), H_CB_WW, data); 73 } 74 75 /** 76 * mei_me_mecsr_read - Reads 32bit data from the ME CSR 77 * 78 * @dev: the device structure 79 * 80 * Return: ME_CSR_HA register value (u32) 81 */ 82 static inline u32 mei_me_mecsr_read(const struct mei_device *dev) 83 { 84 u32 reg; 85 86 reg = mei_me_reg_read(to_me_hw(dev), ME_CSR_HA); 87 trace_mei_reg_read(dev->dev, "ME_CSR_HA", ME_CSR_HA, reg); 88 89 return reg; 90 } 91 92 /** 93 * mei_hcsr_read - Reads 32bit data from the host CSR 94 * 95 * @dev: the device structure 96 * 97 * Return: H_CSR register value (u32) 98 */ 99 static inline u32 mei_hcsr_read(const struct mei_device *dev) 100 { 101 u32 reg; 102 103 reg = mei_me_reg_read(to_me_hw(dev), H_CSR); 104 trace_mei_reg_read(dev->dev, "H_CSR", H_CSR, reg); 105 106 return reg; 107 } 108 109 /** 110 * mei_hcsr_write - writes H_CSR register to the mei device 111 * 112 * @dev: the device structure 113 * @reg: new register value 114 */ 115 static inline void mei_hcsr_write(struct mei_device *dev, u32 reg) 116 { 117 trace_mei_reg_write(dev->dev, "H_CSR", H_CSR, reg); 118 mei_me_reg_write(to_me_hw(dev), H_CSR, reg); 119 } 120 121 /** 122 * mei_hcsr_set - writes H_CSR register to the mei device, 123 * and ignores the H_IS bit for it is write-one-to-zero. 124 * 125 * @dev: the device structure 126 * @reg: new register value 127 */ 128 static inline void mei_hcsr_set(struct mei_device *dev, u32 reg) 129 { 130 reg &= ~H_CSR_IS_MASK; 131 mei_hcsr_write(dev, reg); 132 } 133 134 /** 135 * mei_hcsr_set_hig - set host interrupt (set H_IG) 136 * 137 * @dev: the device structure 138 */ 139 static inline void mei_hcsr_set_hig(struct mei_device *dev) 140 { 141 u32 hcsr; 142 143 hcsr = mei_hcsr_read(dev) | H_IG; 144 mei_hcsr_set(dev, hcsr); 145 } 146 147 /** 148 * mei_me_d0i3c_read - Reads 32bit data from the D0I3C register 149 * 150 * @dev: the device structure 151 * 152 * Return: H_D0I3C register value (u32) 153 */ 154 static inline u32 mei_me_d0i3c_read(const struct mei_device *dev) 155 { 156 u32 reg; 157 158 reg = mei_me_reg_read(to_me_hw(dev), H_D0I3C); 159 trace_mei_reg_read(dev->dev, "H_D0I3C", H_D0I3C, reg); 160 161 return reg; 162 } 163 164 /** 165 * mei_me_d0i3c_write - writes H_D0I3C register to device 166 * 167 * @dev: the device structure 168 * @reg: new register value 169 */ 170 static inline void mei_me_d0i3c_write(struct mei_device *dev, u32 reg) 171 { 172 trace_mei_reg_write(dev->dev, "H_D0I3C", H_D0I3C, reg); 173 mei_me_reg_write(to_me_hw(dev), H_D0I3C, reg); 174 } 175 176 /** 177 * mei_me_trc_status - read trc status register 178 * 179 * @dev: mei device 180 * @trc: trc status register value 181 * 182 * Return: 0 on success, error otherwise 183 */ 184 static int mei_me_trc_status(struct mei_device *dev, u32 *trc) 185 { 186 struct mei_me_hw *hw = to_me_hw(dev); 187 188 if (!hw->cfg->hw_trc_supported) 189 return -EOPNOTSUPP; 190 191 *trc = mei_me_reg_read(hw, ME_TRC); 192 trace_mei_reg_read(dev->dev, "ME_TRC", ME_TRC, *trc); 193 194 return 0; 195 } 196 197 /** 198 * mei_me_fw_status - read fw status register from pci config space 199 * 200 * @dev: mei device 201 * @fw_status: fw status register values 202 * 203 * Return: 0 on success, error otherwise 204 */ 205 static int mei_me_fw_status(struct mei_device *dev, 206 struct mei_fw_status *fw_status) 207 { 208 struct mei_me_hw *hw = to_me_hw(dev); 209 const struct mei_fw_status *fw_src = &hw->cfg->fw_status; 210 int ret; 211 int i; 212 213 if (!fw_status || !hw->read_fws) 214 return -EINVAL; 215 216 fw_status->count = fw_src->count; 217 for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) { 218 ret = hw->read_fws(dev, fw_src->status[i], 219 &fw_status->status[i]); 220 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_X", 221 fw_src->status[i], 222 fw_status->status[i]); 223 if (ret) 224 return ret; 225 } 226 227 return 0; 228 } 229 230 /** 231 * mei_me_hw_config - configure hw dependent settings 232 * 233 * @dev: mei device 234 * 235 * Return: 236 * * -EINVAL when read_fws is not set 237 * * 0 on success 238 * 239 */ 240 static int mei_me_hw_config(struct mei_device *dev) 241 { 242 struct mei_me_hw *hw = to_me_hw(dev); 243 u32 hcsr, reg; 244 245 if (WARN_ON(!hw->read_fws)) 246 return -EINVAL; 247 248 /* Doesn't change in runtime */ 249 hcsr = mei_hcsr_read(dev); 250 hw->hbuf_depth = (hcsr & H_CBD) >> 24; 251 252 reg = 0; 253 hw->read_fws(dev, PCI_CFG_HFS_1, ®); 254 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg); 255 hw->d0i3_supported = 256 ((reg & PCI_CFG_HFS_1_D0I3_MSK) == PCI_CFG_HFS_1_D0I3_MSK); 257 258 hw->pg_state = MEI_PG_OFF; 259 if (hw->d0i3_supported) { 260 reg = mei_me_d0i3c_read(dev); 261 if (reg & H_D0I3C_I3) 262 hw->pg_state = MEI_PG_ON; 263 } 264 265 return 0; 266 } 267 268 /** 269 * mei_me_pg_state - translate internal pg state 270 * to the mei power gating state 271 * 272 * @dev: mei device 273 * 274 * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise 275 */ 276 static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev) 277 { 278 struct mei_me_hw *hw = to_me_hw(dev); 279 280 return hw->pg_state; 281 } 282 283 static inline u32 me_intr_src(u32 hcsr) 284 { 285 return hcsr & H_CSR_IS_MASK; 286 } 287 288 /** 289 * me_intr_disable - disables mei device interrupts 290 * using supplied hcsr register value. 291 * 292 * @dev: the device structure 293 * @hcsr: supplied hcsr register value 294 */ 295 static inline void me_intr_disable(struct mei_device *dev, u32 hcsr) 296 { 297 hcsr &= ~H_CSR_IE_MASK; 298 mei_hcsr_set(dev, hcsr); 299 } 300 301 /** 302 * me_intr_clear - clear and stop interrupts 303 * 304 * @dev: the device structure 305 * @hcsr: supplied hcsr register value 306 */ 307 static inline void me_intr_clear(struct mei_device *dev, u32 hcsr) 308 { 309 if (me_intr_src(hcsr)) 310 mei_hcsr_write(dev, hcsr); 311 } 312 313 /** 314 * mei_me_intr_clear - clear and stop interrupts 315 * 316 * @dev: the device structure 317 */ 318 static void mei_me_intr_clear(struct mei_device *dev) 319 { 320 u32 hcsr = mei_hcsr_read(dev); 321 322 me_intr_clear(dev, hcsr); 323 } 324 /** 325 * mei_me_intr_enable - enables mei device interrupts 326 * 327 * @dev: the device structure 328 */ 329 static void mei_me_intr_enable(struct mei_device *dev) 330 { 331 u32 hcsr; 332 333 if (mei_me_hw_use_polling(to_me_hw(dev))) 334 return; 335 336 hcsr = mei_hcsr_read(dev) | H_CSR_IE_MASK; 337 mei_hcsr_set(dev, hcsr); 338 } 339 340 /** 341 * mei_me_intr_disable - disables mei device interrupts 342 * 343 * @dev: the device structure 344 */ 345 static void mei_me_intr_disable(struct mei_device *dev) 346 { 347 u32 hcsr = mei_hcsr_read(dev); 348 349 me_intr_disable(dev, hcsr); 350 } 351 352 /** 353 * mei_me_synchronize_irq - wait for pending IRQ handlers 354 * 355 * @dev: the device structure 356 */ 357 static void mei_me_synchronize_irq(struct mei_device *dev) 358 { 359 struct mei_me_hw *hw = to_me_hw(dev); 360 361 if (mei_me_hw_use_polling(hw)) 362 return; 363 364 synchronize_irq(hw->irq); 365 } 366 367 /** 368 * mei_me_hw_reset_release - release device from the reset 369 * 370 * @dev: the device structure 371 */ 372 static void mei_me_hw_reset_release(struct mei_device *dev) 373 { 374 u32 hcsr = mei_hcsr_read(dev); 375 376 hcsr |= H_IG; 377 hcsr &= ~H_RST; 378 mei_hcsr_set(dev, hcsr); 379 } 380 381 /** 382 * mei_me_host_set_ready - enable device 383 * 384 * @dev: mei device 385 */ 386 static void mei_me_host_set_ready(struct mei_device *dev) 387 { 388 u32 hcsr = mei_hcsr_read(dev); 389 390 if (!mei_me_hw_use_polling(to_me_hw(dev))) 391 hcsr |= H_CSR_IE_MASK; 392 393 hcsr |= H_IG | H_RDY; 394 mei_hcsr_set(dev, hcsr); 395 } 396 397 /** 398 * mei_me_host_is_ready - check whether the host has turned ready 399 * 400 * @dev: mei device 401 * Return: bool 402 */ 403 static bool mei_me_host_is_ready(struct mei_device *dev) 404 { 405 u32 hcsr = mei_hcsr_read(dev); 406 407 return (hcsr & H_RDY) == H_RDY; 408 } 409 410 /** 411 * mei_me_hw_is_ready - check whether the me(hw) has turned ready 412 * 413 * @dev: mei device 414 * Return: bool 415 */ 416 static bool mei_me_hw_is_ready(struct mei_device *dev) 417 { 418 u32 mecsr = mei_me_mecsr_read(dev); 419 420 return (mecsr & ME_RDY_HRA) == ME_RDY_HRA; 421 } 422 423 /** 424 * mei_me_hw_is_resetting - check whether the me(hw) is in reset 425 * 426 * @dev: mei device 427 * Return: bool 428 */ 429 static bool mei_me_hw_is_resetting(struct mei_device *dev) 430 { 431 u32 mecsr = mei_me_mecsr_read(dev); 432 433 return (mecsr & ME_RST_HRA) == ME_RST_HRA; 434 } 435 436 /** 437 * mei_gsc_pxp_check - check for gsc firmware entering pxp mode 438 * 439 * @dev: the device structure 440 */ 441 static void mei_gsc_pxp_check(struct mei_device *dev) 442 { 443 struct mei_me_hw *hw = to_me_hw(dev); 444 u32 fwsts5 = 0; 445 446 if (dev->pxp_mode == MEI_DEV_PXP_DEFAULT) 447 return; 448 449 hw->read_fws(dev, PCI_CFG_HFS_5, &fwsts5); 450 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_5", PCI_CFG_HFS_5, fwsts5); 451 if ((fwsts5 & GSC_CFG_HFS_5_BOOT_TYPE_MSK) == GSC_CFG_HFS_5_BOOT_TYPE_PXP) { 452 dev_dbg(dev->dev, "pxp mode is ready 0x%08x\n", fwsts5); 453 dev->pxp_mode = MEI_DEV_PXP_READY; 454 } else { 455 dev_dbg(dev->dev, "pxp mode is not ready 0x%08x\n", fwsts5); 456 } 457 } 458 459 /** 460 * mei_me_hw_ready_wait - wait until the me(hw) has turned ready 461 * or timeout is reached 462 * 463 * @dev: mei device 464 * Return: 0 on success, error otherwise 465 */ 466 static int mei_me_hw_ready_wait(struct mei_device *dev) 467 { 468 mutex_unlock(&dev->device_lock); 469 wait_event_timeout(dev->wait_hw_ready, 470 dev->recvd_hw_ready, 471 dev->timeouts.hw_ready); 472 mutex_lock(&dev->device_lock); 473 if (!dev->recvd_hw_ready) { 474 dev_err(dev->dev, "wait hw ready failed\n"); 475 return -ETIME; 476 } 477 478 mei_gsc_pxp_check(dev); 479 480 mei_me_hw_reset_release(dev); 481 dev->recvd_hw_ready = false; 482 return 0; 483 } 484 485 /** 486 * mei_me_hw_start - hw start routine 487 * 488 * @dev: mei device 489 * Return: 0 on success, error otherwise 490 */ 491 static int mei_me_hw_start(struct mei_device *dev) 492 { 493 int ret = mei_me_hw_ready_wait(dev); 494 495 if (ret) 496 return ret; 497 dev_dbg(dev->dev, "hw is ready\n"); 498 499 mei_me_host_set_ready(dev); 500 return ret; 501 } 502 503 504 /** 505 * mei_hbuf_filled_slots - gets number of device filled buffer slots 506 * 507 * @dev: the device structure 508 * 509 * Return: number of filled slots 510 */ 511 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev) 512 { 513 u32 hcsr; 514 char read_ptr, write_ptr; 515 516 hcsr = mei_hcsr_read(dev); 517 518 read_ptr = (char) ((hcsr & H_CBRP) >> 8); 519 write_ptr = (char) ((hcsr & H_CBWP) >> 16); 520 521 return (unsigned char) (write_ptr - read_ptr); 522 } 523 524 /** 525 * mei_me_hbuf_is_empty - checks if host buffer is empty. 526 * 527 * @dev: the device structure 528 * 529 * Return: true if empty, false - otherwise. 530 */ 531 static bool mei_me_hbuf_is_empty(struct mei_device *dev) 532 { 533 return mei_hbuf_filled_slots(dev) == 0; 534 } 535 536 /** 537 * mei_me_hbuf_empty_slots - counts write empty slots. 538 * 539 * @dev: the device structure 540 * 541 * Return: -EOVERFLOW if overflow, otherwise empty slots count 542 */ 543 static int mei_me_hbuf_empty_slots(struct mei_device *dev) 544 { 545 struct mei_me_hw *hw = to_me_hw(dev); 546 unsigned char filled_slots, empty_slots; 547 548 filled_slots = mei_hbuf_filled_slots(dev); 549 empty_slots = hw->hbuf_depth - filled_slots; 550 551 /* check for overflow */ 552 if (filled_slots > hw->hbuf_depth) 553 return -EOVERFLOW; 554 555 return empty_slots; 556 } 557 558 /** 559 * mei_me_hbuf_depth - returns depth of the hw buffer. 560 * 561 * @dev: the device structure 562 * 563 * Return: size of hw buffer in slots 564 */ 565 static u32 mei_me_hbuf_depth(const struct mei_device *dev) 566 { 567 struct mei_me_hw *hw = to_me_hw(dev); 568 569 return hw->hbuf_depth; 570 } 571 572 /** 573 * mei_me_hbuf_write - writes a message to host hw buffer. 574 * 575 * @dev: the device structure 576 * @hdr: header of message 577 * @hdr_len: header length in bytes: must be multiplication of a slot (4bytes) 578 * @data: payload 579 * @data_len: payload length in bytes 580 * 581 * Return: 0 if success, < 0 - otherwise. 582 */ 583 static int mei_me_hbuf_write(struct mei_device *dev, 584 const void *hdr, size_t hdr_len, 585 const void *data, size_t data_len) 586 { 587 unsigned long rem; 588 unsigned long i; 589 const u32 *reg_buf; 590 u32 dw_cnt; 591 int empty_slots; 592 593 if (WARN_ON(!hdr || !data || hdr_len & 0x3)) 594 return -EINVAL; 595 596 dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM((struct mei_msg_hdr *)hdr)); 597 598 empty_slots = mei_hbuf_empty_slots(dev); 599 dev_dbg(dev->dev, "empty slots = %d.\n", empty_slots); 600 601 if (empty_slots < 0) 602 return -EOVERFLOW; 603 604 dw_cnt = mei_data2slots(hdr_len + data_len); 605 if (dw_cnt > (u32)empty_slots) 606 return -EMSGSIZE; 607 608 reg_buf = hdr; 609 for (i = 0; i < hdr_len / MEI_SLOT_SIZE; i++) 610 mei_me_hcbww_write(dev, reg_buf[i]); 611 612 reg_buf = data; 613 for (i = 0; i < data_len / MEI_SLOT_SIZE; i++) 614 mei_me_hcbww_write(dev, reg_buf[i]); 615 616 rem = data_len & 0x3; 617 if (rem > 0) { 618 u32 reg = 0; 619 620 memcpy(®, (const u8 *)data + data_len - rem, rem); 621 mei_me_hcbww_write(dev, reg); 622 } 623 624 mei_hcsr_set_hig(dev); 625 if (!mei_me_hw_is_ready(dev)) 626 return -EIO; 627 628 return 0; 629 } 630 631 /** 632 * mei_me_count_full_read_slots - counts read full slots. 633 * 634 * @dev: the device structure 635 * 636 * Return: -EOVERFLOW if overflow, otherwise filled slots count 637 */ 638 static int mei_me_count_full_read_slots(struct mei_device *dev) 639 { 640 u32 me_csr; 641 char read_ptr, write_ptr; 642 unsigned char buffer_depth, filled_slots; 643 644 me_csr = mei_me_mecsr_read(dev); 645 buffer_depth = (unsigned char)((me_csr & ME_CBD_HRA) >> 24); 646 read_ptr = (char) ((me_csr & ME_CBRP_HRA) >> 8); 647 write_ptr = (char) ((me_csr & ME_CBWP_HRA) >> 16); 648 filled_slots = (unsigned char) (write_ptr - read_ptr); 649 650 /* check for overflow */ 651 if (filled_slots > buffer_depth) 652 return -EOVERFLOW; 653 654 dev_dbg(dev->dev, "filled_slots =%08x\n", filled_slots); 655 return (int)filled_slots; 656 } 657 658 /** 659 * mei_me_read_slots - reads a message from mei device. 660 * 661 * @dev: the device structure 662 * @buffer: message buffer will be written 663 * @buffer_length: message size will be read 664 * 665 * Return: always 0 666 */ 667 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer, 668 unsigned long buffer_length) 669 { 670 u32 *reg_buf = (u32 *)buffer; 671 672 for (; buffer_length >= MEI_SLOT_SIZE; buffer_length -= MEI_SLOT_SIZE) 673 *reg_buf++ = mei_me_mecbrw_read(dev); 674 675 if (buffer_length > 0) { 676 u32 reg = mei_me_mecbrw_read(dev); 677 678 memcpy(reg_buf, ®, buffer_length); 679 } 680 681 mei_hcsr_set_hig(dev); 682 return 0; 683 } 684 685 /** 686 * mei_me_pg_set - write pg enter register 687 * 688 * @dev: the device structure 689 */ 690 static void mei_me_pg_set(struct mei_device *dev) 691 { 692 struct mei_me_hw *hw = to_me_hw(dev); 693 u32 reg; 694 695 reg = mei_me_reg_read(hw, H_HPG_CSR); 696 trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); 697 698 reg |= H_HPG_CSR_PGI; 699 700 trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); 701 mei_me_reg_write(hw, H_HPG_CSR, reg); 702 } 703 704 /** 705 * mei_me_pg_unset - write pg exit register 706 * 707 * @dev: the device structure 708 */ 709 static void mei_me_pg_unset(struct mei_device *dev) 710 { 711 struct mei_me_hw *hw = to_me_hw(dev); 712 u32 reg; 713 714 reg = mei_me_reg_read(hw, H_HPG_CSR); 715 trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); 716 717 WARN(!(reg & H_HPG_CSR_PGI), "PGI is not set\n"); 718 719 reg |= H_HPG_CSR_PGIHEXR; 720 721 trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); 722 mei_me_reg_write(hw, H_HPG_CSR, reg); 723 } 724 725 /** 726 * mei_me_pg_legacy_enter_sync - perform legacy pg entry procedure 727 * 728 * @dev: the device structure 729 * 730 * Return: 0 on success an error code otherwise 731 */ 732 static int mei_me_pg_legacy_enter_sync(struct mei_device *dev) 733 { 734 struct mei_me_hw *hw = to_me_hw(dev); 735 int ret; 736 737 dev->pg_event = MEI_PG_EVENT_WAIT; 738 739 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD); 740 if (ret) 741 return ret; 742 743 mutex_unlock(&dev->device_lock); 744 wait_event_timeout(dev->wait_pg, 745 dev->pg_event == MEI_PG_EVENT_RECEIVED, 746 dev->timeouts.pgi); 747 mutex_lock(&dev->device_lock); 748 749 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) { 750 mei_me_pg_set(dev); 751 ret = 0; 752 } else { 753 ret = -ETIME; 754 } 755 756 dev->pg_event = MEI_PG_EVENT_IDLE; 757 hw->pg_state = MEI_PG_ON; 758 759 return ret; 760 } 761 762 /** 763 * mei_me_pg_legacy_exit_sync - perform legacy pg exit procedure 764 * 765 * @dev: the device structure 766 * 767 * Return: 0 on success an error code otherwise 768 */ 769 static int mei_me_pg_legacy_exit_sync(struct mei_device *dev) 770 { 771 struct mei_me_hw *hw = to_me_hw(dev); 772 int ret; 773 774 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) 775 goto reply; 776 777 dev->pg_event = MEI_PG_EVENT_WAIT; 778 779 mei_me_pg_unset(dev); 780 781 mutex_unlock(&dev->device_lock); 782 wait_event_timeout(dev->wait_pg, 783 dev->pg_event == MEI_PG_EVENT_RECEIVED, 784 dev->timeouts.pgi); 785 mutex_lock(&dev->device_lock); 786 787 reply: 788 if (dev->pg_event != MEI_PG_EVENT_RECEIVED) { 789 ret = -ETIME; 790 goto out; 791 } 792 793 dev->pg_event = MEI_PG_EVENT_INTR_WAIT; 794 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD); 795 if (ret) 796 return ret; 797 798 mutex_unlock(&dev->device_lock); 799 wait_event_timeout(dev->wait_pg, 800 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, 801 dev->timeouts.pgi); 802 mutex_lock(&dev->device_lock); 803 804 if (dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED) 805 ret = 0; 806 else 807 ret = -ETIME; 808 809 out: 810 dev->pg_event = MEI_PG_EVENT_IDLE; 811 hw->pg_state = MEI_PG_OFF; 812 813 return ret; 814 } 815 816 /** 817 * mei_me_pg_in_transition - is device now in pg transition 818 * 819 * @dev: the device structure 820 * 821 * Return: true if in pg transition, false otherwise 822 */ 823 static bool mei_me_pg_in_transition(struct mei_device *dev) 824 { 825 return dev->pg_event >= MEI_PG_EVENT_WAIT && 826 dev->pg_event <= MEI_PG_EVENT_INTR_WAIT; 827 } 828 829 /** 830 * mei_me_pg_is_enabled - detect if PG is supported by HW 831 * 832 * @dev: the device structure 833 * 834 * Return: true is pg supported, false otherwise 835 */ 836 static bool mei_me_pg_is_enabled(struct mei_device *dev) 837 { 838 struct mei_me_hw *hw = to_me_hw(dev); 839 u32 reg = mei_me_mecsr_read(dev); 840 841 if (hw->d0i3_supported) 842 return true; 843 844 if ((reg & ME_PGIC_HRA) == 0) 845 goto notsupported; 846 847 if (!dev->hbm_f_pg_supported) 848 goto notsupported; 849 850 return true; 851 852 notsupported: 853 dev_dbg(dev->dev, "pg: not supported: d0i3 = %d HGP = %d hbm version %d.%d ?= %d.%d\n", 854 hw->d0i3_supported, 855 !!(reg & ME_PGIC_HRA), 856 dev->version.major_version, 857 dev->version.minor_version, 858 HBM_MAJOR_VERSION_PGI, 859 HBM_MINOR_VERSION_PGI); 860 861 return false; 862 } 863 864 /** 865 * mei_me_d0i3_set - write d0i3 register bit on mei device. 866 * 867 * @dev: the device structure 868 * @intr: ask for interrupt 869 * 870 * Return: D0I3C register value 871 */ 872 static u32 mei_me_d0i3_set(struct mei_device *dev, bool intr) 873 { 874 u32 reg = mei_me_d0i3c_read(dev); 875 876 reg |= H_D0I3C_I3; 877 if (intr) 878 reg |= H_D0I3C_IR; 879 else 880 reg &= ~H_D0I3C_IR; 881 mei_me_d0i3c_write(dev, reg); 882 /* read it to ensure HW consistency */ 883 reg = mei_me_d0i3c_read(dev); 884 return reg; 885 } 886 887 /** 888 * mei_me_d0i3_unset - clean d0i3 register bit on mei device. 889 * 890 * @dev: the device structure 891 * 892 * Return: D0I3C register value 893 */ 894 static u32 mei_me_d0i3_unset(struct mei_device *dev) 895 { 896 u32 reg = mei_me_d0i3c_read(dev); 897 898 reg &= ~H_D0I3C_I3; 899 reg |= H_D0I3C_IR; 900 mei_me_d0i3c_write(dev, reg); 901 /* read it to ensure HW consistency */ 902 reg = mei_me_d0i3c_read(dev); 903 return reg; 904 } 905 906 /** 907 * mei_me_d0i3_enter_sync - perform d0i3 entry procedure 908 * 909 * @dev: the device structure 910 * 911 * Return: 0 on success an error code otherwise 912 */ 913 static int mei_me_d0i3_enter_sync(struct mei_device *dev) 914 { 915 struct mei_me_hw *hw = to_me_hw(dev); 916 int ret; 917 u32 reg; 918 919 reg = mei_me_d0i3c_read(dev); 920 if (reg & H_D0I3C_I3) { 921 /* we are in d0i3, nothing to do */ 922 dev_dbg(dev->dev, "d0i3 set not needed\n"); 923 ret = 0; 924 goto on; 925 } 926 927 /* PGI entry procedure */ 928 dev->pg_event = MEI_PG_EVENT_WAIT; 929 930 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD); 931 if (ret) 932 /* FIXME: should we reset here? */ 933 goto out; 934 935 mutex_unlock(&dev->device_lock); 936 wait_event_timeout(dev->wait_pg, 937 dev->pg_event == MEI_PG_EVENT_RECEIVED, 938 dev->timeouts.pgi); 939 mutex_lock(&dev->device_lock); 940 941 if (dev->pg_event != MEI_PG_EVENT_RECEIVED) { 942 ret = -ETIME; 943 goto out; 944 } 945 /* end PGI entry procedure */ 946 947 dev->pg_event = MEI_PG_EVENT_INTR_WAIT; 948 949 reg = mei_me_d0i3_set(dev, true); 950 if (!(reg & H_D0I3C_CIP)) { 951 dev_dbg(dev->dev, "d0i3 enter wait not needed\n"); 952 ret = 0; 953 goto on; 954 } 955 956 mutex_unlock(&dev->device_lock); 957 wait_event_timeout(dev->wait_pg, 958 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, 959 dev->timeouts.d0i3); 960 mutex_lock(&dev->device_lock); 961 962 if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) { 963 reg = mei_me_d0i3c_read(dev); 964 if (!(reg & H_D0I3C_I3)) { 965 ret = -ETIME; 966 goto out; 967 } 968 } 969 970 ret = 0; 971 on: 972 hw->pg_state = MEI_PG_ON; 973 out: 974 dev->pg_event = MEI_PG_EVENT_IDLE; 975 dev_dbg(dev->dev, "d0i3 enter ret = %d\n", ret); 976 return ret; 977 } 978 979 /** 980 * mei_me_d0i3_enter - perform d0i3 entry procedure 981 * no hbm PG handshake 982 * no waiting for confirmation; runs with interrupts 983 * disabled 984 * 985 * @dev: the device structure 986 * 987 * Return: 0 on success an error code otherwise 988 */ 989 static int mei_me_d0i3_enter(struct mei_device *dev) 990 { 991 struct mei_me_hw *hw = to_me_hw(dev); 992 u32 reg; 993 994 reg = mei_me_d0i3c_read(dev); 995 if (reg & H_D0I3C_I3) { 996 /* we are in d0i3, nothing to do */ 997 dev_dbg(dev->dev, "already d0i3 : set not needed\n"); 998 goto on; 999 } 1000 1001 mei_me_d0i3_set(dev, false); 1002 on: 1003 hw->pg_state = MEI_PG_ON; 1004 dev->pg_event = MEI_PG_EVENT_IDLE; 1005 dev_dbg(dev->dev, "d0i3 enter\n"); 1006 return 0; 1007 } 1008 1009 /** 1010 * mei_me_d0i3_exit_sync - perform d0i3 exit procedure 1011 * 1012 * @dev: the device structure 1013 * 1014 * Return: 0 on success an error code otherwise 1015 */ 1016 static int mei_me_d0i3_exit_sync(struct mei_device *dev) 1017 { 1018 struct mei_me_hw *hw = to_me_hw(dev); 1019 int ret; 1020 u32 reg; 1021 1022 dev->pg_event = MEI_PG_EVENT_INTR_WAIT; 1023 1024 reg = mei_me_d0i3c_read(dev); 1025 if (!(reg & H_D0I3C_I3)) { 1026 /* we are not in d0i3, nothing to do */ 1027 dev_dbg(dev->dev, "d0i3 exit not needed\n"); 1028 ret = 0; 1029 goto off; 1030 } 1031 1032 reg = mei_me_d0i3_unset(dev); 1033 if (!(reg & H_D0I3C_CIP)) { 1034 dev_dbg(dev->dev, "d0i3 exit wait not needed\n"); 1035 ret = 0; 1036 goto off; 1037 } 1038 1039 mutex_unlock(&dev->device_lock); 1040 wait_event_timeout(dev->wait_pg, 1041 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, 1042 dev->timeouts.d0i3); 1043 mutex_lock(&dev->device_lock); 1044 1045 if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) { 1046 reg = mei_me_d0i3c_read(dev); 1047 if (reg & H_D0I3C_I3) { 1048 ret = -ETIME; 1049 goto out; 1050 } 1051 } 1052 1053 ret = 0; 1054 off: 1055 hw->pg_state = MEI_PG_OFF; 1056 out: 1057 dev->pg_event = MEI_PG_EVENT_IDLE; 1058 1059 dev_dbg(dev->dev, "d0i3 exit ret = %d\n", ret); 1060 return ret; 1061 } 1062 1063 /** 1064 * mei_me_pg_legacy_intr - perform legacy pg processing 1065 * in interrupt thread handler 1066 * 1067 * @dev: the device structure 1068 */ 1069 static void mei_me_pg_legacy_intr(struct mei_device *dev) 1070 { 1071 struct mei_me_hw *hw = to_me_hw(dev); 1072 1073 if (dev->pg_event != MEI_PG_EVENT_INTR_WAIT) 1074 return; 1075 1076 dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED; 1077 hw->pg_state = MEI_PG_OFF; 1078 if (waitqueue_active(&dev->wait_pg)) 1079 wake_up(&dev->wait_pg); 1080 } 1081 1082 /** 1083 * mei_me_d0i3_intr - perform d0i3 processing in interrupt thread handler 1084 * 1085 * @dev: the device structure 1086 * @intr_source: interrupt source 1087 */ 1088 static void mei_me_d0i3_intr(struct mei_device *dev, u32 intr_source) 1089 { 1090 struct mei_me_hw *hw = to_me_hw(dev); 1091 1092 if (dev->pg_event == MEI_PG_EVENT_INTR_WAIT && 1093 (intr_source & H_D0I3C_IS)) { 1094 dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED; 1095 if (hw->pg_state == MEI_PG_ON) { 1096 hw->pg_state = MEI_PG_OFF; 1097 if (dev->hbm_state != MEI_HBM_IDLE) { 1098 /* 1099 * force H_RDY because it could be 1100 * wiped off during PG 1101 */ 1102 dev_dbg(dev->dev, "d0i3 set host ready\n"); 1103 mei_me_host_set_ready(dev); 1104 } 1105 } else { 1106 hw->pg_state = MEI_PG_ON; 1107 } 1108 1109 wake_up(&dev->wait_pg); 1110 } 1111 1112 if (hw->pg_state == MEI_PG_ON && (intr_source & H_IS)) { 1113 /* 1114 * HW sent some data and we are in D0i3, so 1115 * we got here because of HW initiated exit from D0i3. 1116 * Start runtime pm resume sequence to exit low power state. 1117 */ 1118 dev_dbg(dev->dev, "d0i3 want resume\n"); 1119 mei_hbm_pg_resume(dev); 1120 } 1121 } 1122 1123 /** 1124 * mei_me_pg_intr - perform pg processing in interrupt thread handler 1125 * 1126 * @dev: the device structure 1127 * @intr_source: interrupt source 1128 */ 1129 static void mei_me_pg_intr(struct mei_device *dev, u32 intr_source) 1130 { 1131 struct mei_me_hw *hw = to_me_hw(dev); 1132 1133 if (hw->d0i3_supported) 1134 mei_me_d0i3_intr(dev, intr_source); 1135 else 1136 mei_me_pg_legacy_intr(dev); 1137 } 1138 1139 /** 1140 * mei_me_pg_enter_sync - perform runtime pm entry procedure 1141 * 1142 * @dev: the device structure 1143 * 1144 * Return: 0 on success an error code otherwise 1145 */ 1146 int mei_me_pg_enter_sync(struct mei_device *dev) 1147 { 1148 struct mei_me_hw *hw = to_me_hw(dev); 1149 1150 if (hw->d0i3_supported) 1151 return mei_me_d0i3_enter_sync(dev); 1152 else 1153 return mei_me_pg_legacy_enter_sync(dev); 1154 } 1155 1156 /** 1157 * mei_me_pg_exit_sync - perform runtime pm exit procedure 1158 * 1159 * @dev: the device structure 1160 * 1161 * Return: 0 on success an error code otherwise 1162 */ 1163 int mei_me_pg_exit_sync(struct mei_device *dev) 1164 { 1165 struct mei_me_hw *hw = to_me_hw(dev); 1166 1167 if (hw->d0i3_supported) 1168 return mei_me_d0i3_exit_sync(dev); 1169 else 1170 return mei_me_pg_legacy_exit_sync(dev); 1171 } 1172 1173 /** 1174 * mei_me_hw_reset - resets fw via mei csr register. 1175 * 1176 * @dev: the device structure 1177 * @intr_enable: if interrupt should be enabled after reset. 1178 * 1179 * Return: 0 on success an error code otherwise 1180 */ 1181 static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable) 1182 { 1183 struct mei_me_hw *hw = to_me_hw(dev); 1184 int ret; 1185 u32 hcsr; 1186 1187 if (intr_enable) { 1188 mei_me_intr_enable(dev); 1189 if (hw->d0i3_supported) { 1190 ret = mei_me_d0i3_exit_sync(dev); 1191 if (ret) 1192 return ret; 1193 } else { 1194 hw->pg_state = MEI_PG_OFF; 1195 } 1196 } 1197 1198 pm_runtime_set_active(dev->dev); 1199 1200 hcsr = mei_hcsr_read(dev); 1201 /* H_RST may be found lit before reset is started, 1202 * for example if preceding reset flow hasn't completed. 1203 * In that case asserting H_RST will be ignored, therefore 1204 * we need to clean H_RST bit to start a successful reset sequence. 1205 */ 1206 if ((hcsr & H_RST) == H_RST) { 1207 dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr); 1208 hcsr &= ~H_RST; 1209 mei_hcsr_set(dev, hcsr); 1210 hcsr = mei_hcsr_read(dev); 1211 } 1212 1213 hcsr |= H_RST | H_IG | H_CSR_IS_MASK; 1214 1215 if (!intr_enable || mei_me_hw_use_polling(to_me_hw(dev))) 1216 hcsr &= ~H_CSR_IE_MASK; 1217 1218 dev->recvd_hw_ready = false; 1219 mei_hcsr_write(dev, hcsr); 1220 1221 /* 1222 * Host reads the H_CSR once to ensure that the 1223 * posted write to H_CSR completes. 1224 */ 1225 hcsr = mei_hcsr_read(dev); 1226 1227 if ((hcsr & H_RST) == 0) 1228 dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr); 1229 1230 if ((hcsr & H_RDY) == H_RDY) 1231 dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr); 1232 1233 if (!intr_enable) { 1234 mei_me_hw_reset_release(dev); 1235 if (hw->d0i3_supported) { 1236 ret = mei_me_d0i3_enter(dev); 1237 if (ret) 1238 return ret; 1239 } 1240 } 1241 return 0; 1242 } 1243 1244 /** 1245 * mei_me_irq_quick_handler - The ISR of the MEI device 1246 * 1247 * @irq: The irq number 1248 * @dev_id: pointer to the device structure 1249 * 1250 * Return: irqreturn_t 1251 */ 1252 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id) 1253 { 1254 struct mei_device *dev = (struct mei_device *)dev_id; 1255 u32 hcsr; 1256 1257 hcsr = mei_hcsr_read(dev); 1258 if (!me_intr_src(hcsr)) 1259 return IRQ_NONE; 1260 1261 dev_dbg(dev->dev, "interrupt source 0x%08X\n", me_intr_src(hcsr)); 1262 1263 /* disable interrupts on device */ 1264 me_intr_disable(dev, hcsr); 1265 return IRQ_WAKE_THREAD; 1266 } 1267 EXPORT_SYMBOL_GPL(mei_me_irq_quick_handler); 1268 1269 /** 1270 * mei_me_irq_thread_handler - function called after ISR to handle the interrupt 1271 * processing. 1272 * 1273 * @irq: The irq number 1274 * @dev_id: pointer to the device structure 1275 * 1276 * Return: irqreturn_t 1277 * 1278 */ 1279 irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id) 1280 { 1281 struct mei_device *dev = (struct mei_device *) dev_id; 1282 struct list_head cmpl_list; 1283 s32 slots; 1284 u32 hcsr; 1285 int rets = 0; 1286 1287 dev_dbg(dev->dev, "function called after ISR to handle the interrupt processing.\n"); 1288 /* initialize our complete list */ 1289 mutex_lock(&dev->device_lock); 1290 1291 hcsr = mei_hcsr_read(dev); 1292 me_intr_clear(dev, hcsr); 1293 1294 INIT_LIST_HEAD(&cmpl_list); 1295 1296 /* check if ME wants a reset */ 1297 if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) { 1298 dev_warn(dev->dev, "FW not ready: resetting: dev_state = %d pxp = %d\n", 1299 dev->dev_state, dev->pxp_mode); 1300 if (dev->dev_state == MEI_DEV_POWERING_DOWN || 1301 dev->dev_state == MEI_DEV_POWER_DOWN) 1302 mei_cl_all_disconnect(dev); 1303 else if (dev->dev_state != MEI_DEV_DISABLED) 1304 schedule_work(&dev->reset_work); 1305 goto end; 1306 } 1307 1308 if (mei_me_hw_is_resetting(dev)) 1309 mei_hcsr_set_hig(dev); 1310 1311 mei_me_pg_intr(dev, me_intr_src(hcsr)); 1312 1313 /* check if we need to start the dev */ 1314 if (!mei_host_is_ready(dev)) { 1315 if (mei_hw_is_ready(dev)) { 1316 dev_dbg(dev->dev, "we need to start the dev.\n"); 1317 dev->recvd_hw_ready = true; 1318 wake_up(&dev->wait_hw_ready); 1319 } else { 1320 dev_dbg(dev->dev, "Spurious Interrupt\n"); 1321 } 1322 goto end; 1323 } 1324 /* check slots available for reading */ 1325 slots = mei_count_full_read_slots(dev); 1326 while (slots > 0) { 1327 dev_dbg(dev->dev, "slots to read = %08x\n", slots); 1328 rets = mei_irq_read_handler(dev, &cmpl_list, &slots); 1329 /* There is a race between ME write and interrupt delivery: 1330 * Not all data is always available immediately after the 1331 * interrupt, so try to read again on the next interrupt. 1332 */ 1333 if (rets == -ENODATA) 1334 break; 1335 1336 if (rets) { 1337 dev_err(dev->dev, "mei_irq_read_handler ret = %d, state = %d.\n", 1338 rets, dev->dev_state); 1339 if (dev->dev_state != MEI_DEV_RESETTING && 1340 dev->dev_state != MEI_DEV_DISABLED && 1341 dev->dev_state != MEI_DEV_POWERING_DOWN && 1342 dev->dev_state != MEI_DEV_POWER_DOWN) 1343 schedule_work(&dev->reset_work); 1344 goto end; 1345 } 1346 } 1347 1348 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); 1349 1350 /* 1351 * During PG handshake only allowed write is the replay to the 1352 * PG exit message, so block calling write function 1353 * if the pg event is in PG handshake 1354 */ 1355 if (dev->pg_event != MEI_PG_EVENT_WAIT && 1356 dev->pg_event != MEI_PG_EVENT_RECEIVED) { 1357 rets = mei_irq_write_handler(dev, &cmpl_list); 1358 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); 1359 } 1360 1361 mei_irq_compl_handler(dev, &cmpl_list); 1362 1363 end: 1364 dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets); 1365 mei_me_intr_enable(dev); 1366 mutex_unlock(&dev->device_lock); 1367 return IRQ_HANDLED; 1368 } 1369 EXPORT_SYMBOL_GPL(mei_me_irq_thread_handler); 1370 1371 #define MEI_POLLING_TIMEOUT_ACTIVE 100 1372 #define MEI_POLLING_TIMEOUT_IDLE 500 1373 1374 /** 1375 * mei_me_polling_thread - interrupt register polling thread 1376 * 1377 * The thread monitors the interrupt source register and calls 1378 * mei_me_irq_thread_handler() to handle the firmware 1379 * input. 1380 * 1381 * The function polls in MEI_POLLING_TIMEOUT_ACTIVE timeout 1382 * in case there was an event, in idle case the polling 1383 * time increases yet again by MEI_POLLING_TIMEOUT_ACTIVE 1384 * up to MEI_POLLING_TIMEOUT_IDLE. 1385 * 1386 * @_dev: mei device 1387 * 1388 * Return: always 0 1389 */ 1390 int mei_me_polling_thread(void *_dev) 1391 { 1392 struct mei_device *dev = _dev; 1393 irqreturn_t irq_ret; 1394 long polling_timeout = MEI_POLLING_TIMEOUT_ACTIVE; 1395 1396 dev_dbg(dev->dev, "kernel thread is running\n"); 1397 while (!kthread_should_stop()) { 1398 struct mei_me_hw *hw = to_me_hw(dev); 1399 u32 hcsr; 1400 1401 wait_event_timeout(hw->wait_active, 1402 hw->is_active || kthread_should_stop(), 1403 msecs_to_jiffies(MEI_POLLING_TIMEOUT_IDLE)); 1404 1405 if (kthread_should_stop()) 1406 break; 1407 1408 hcsr = mei_hcsr_read(dev); 1409 if (me_intr_src(hcsr)) { 1410 polling_timeout = MEI_POLLING_TIMEOUT_ACTIVE; 1411 irq_ret = mei_me_irq_thread_handler(1, dev); 1412 if (irq_ret != IRQ_HANDLED) 1413 dev_err(dev->dev, "irq_ret %d\n", irq_ret); 1414 } else { 1415 /* 1416 * Increase timeout by MEI_POLLING_TIMEOUT_ACTIVE 1417 * up to MEI_POLLING_TIMEOUT_IDLE 1418 */ 1419 polling_timeout = clamp_val(polling_timeout + MEI_POLLING_TIMEOUT_ACTIVE, 1420 MEI_POLLING_TIMEOUT_ACTIVE, 1421 MEI_POLLING_TIMEOUT_IDLE); 1422 } 1423 1424 schedule_timeout_interruptible(msecs_to_jiffies(polling_timeout)); 1425 } 1426 1427 return 0; 1428 } 1429 EXPORT_SYMBOL_GPL(mei_me_polling_thread); 1430 1431 static const struct mei_hw_ops mei_me_hw_ops = { 1432 1433 .trc_status = mei_me_trc_status, 1434 .fw_status = mei_me_fw_status, 1435 .pg_state = mei_me_pg_state, 1436 1437 .host_is_ready = mei_me_host_is_ready, 1438 1439 .hw_is_ready = mei_me_hw_is_ready, 1440 .hw_reset = mei_me_hw_reset, 1441 .hw_config = mei_me_hw_config, 1442 .hw_start = mei_me_hw_start, 1443 1444 .pg_in_transition = mei_me_pg_in_transition, 1445 .pg_is_enabled = mei_me_pg_is_enabled, 1446 1447 .intr_clear = mei_me_intr_clear, 1448 .intr_enable = mei_me_intr_enable, 1449 .intr_disable = mei_me_intr_disable, 1450 .synchronize_irq = mei_me_synchronize_irq, 1451 1452 .hbuf_free_slots = mei_me_hbuf_empty_slots, 1453 .hbuf_is_ready = mei_me_hbuf_is_empty, 1454 .hbuf_depth = mei_me_hbuf_depth, 1455 1456 .write = mei_me_hbuf_write, 1457 1458 .rdbuf_full_slots = mei_me_count_full_read_slots, 1459 .read_hdr = mei_me_mecbrw_read, 1460 .read = mei_me_read_slots 1461 }; 1462 1463 /** 1464 * mei_me_fw_type_nm() - check for nm sku 1465 * 1466 * Read ME FW Status register to check for the Node Manager (NM) Firmware. 1467 * The NM FW is only signaled in PCI function 0. 1468 * __Note__: Deprecated by PCH8 and newer. 1469 * 1470 * @pdev: pci device 1471 * 1472 * Return: true in case of NM firmware 1473 */ 1474 static bool mei_me_fw_type_nm(const struct pci_dev *pdev) 1475 { 1476 u32 reg; 1477 unsigned int devfn; 1478 1479 devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0); 1480 pci_bus_read_config_dword(pdev->bus, devfn, PCI_CFG_HFS_2, ®); 1481 trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_2", PCI_CFG_HFS_2, reg); 1482 /* make sure that bit 9 (NM) is up and bit 10 (DM) is down */ 1483 return (reg & 0x600) == 0x200; 1484 } 1485 1486 #define MEI_CFG_FW_NM \ 1487 .quirk_probe = mei_me_fw_type_nm 1488 1489 /** 1490 * mei_me_fw_type_sps_4() - check for sps 4.0 sku 1491 * 1492 * Read ME FW Status register to check for SPS Firmware. 1493 * The SPS FW is only signaled in the PCI function 0. 1494 * __Note__: Deprecated by SPS 5.0 and newer. 1495 * 1496 * @pdev: pci device 1497 * 1498 * Return: true in case of SPS firmware 1499 */ 1500 static bool mei_me_fw_type_sps_4(const struct pci_dev *pdev) 1501 { 1502 u32 reg; 1503 unsigned int devfn; 1504 1505 devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0); 1506 pci_bus_read_config_dword(pdev->bus, devfn, PCI_CFG_HFS_1, ®); 1507 trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg); 1508 return (reg & PCI_CFG_HFS_1_OPMODE_MSK) == PCI_CFG_HFS_1_OPMODE_SPS; 1509 } 1510 1511 #define MEI_CFG_FW_SPS_4 \ 1512 .quirk_probe = mei_me_fw_type_sps_4 1513 1514 /** 1515 * mei_me_fw_type_sps_ign() - check for sps or ign sku 1516 * 1517 * Read ME FW Status register to check for SPS or IGN Firmware. 1518 * The SPS/IGN FW is only signaled in pci function 0 1519 * 1520 * @pdev: pci device 1521 * 1522 * Return: true in case of SPS/IGN firmware 1523 */ 1524 static bool mei_me_fw_type_sps_ign(const struct pci_dev *pdev) 1525 { 1526 u32 reg; 1527 u32 fw_type; 1528 unsigned int devfn; 1529 1530 devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0); 1531 pci_bus_read_config_dword(pdev->bus, devfn, PCI_CFG_HFS_3, ®); 1532 trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_3", PCI_CFG_HFS_3, reg); 1533 fw_type = (reg & PCI_CFG_HFS_3_FW_SKU_MSK); 1534 1535 dev_dbg(&pdev->dev, "fw type is %d\n", fw_type); 1536 1537 return fw_type == PCI_CFG_HFS_3_FW_SKU_IGN || 1538 fw_type == PCI_CFG_HFS_3_FW_SKU_SPS; 1539 } 1540 1541 #define MEI_CFG_KIND_ITOUCH \ 1542 .kind = "itouch" 1543 1544 #define MEI_CFG_TYPE_GSC \ 1545 .kind = "gsc" 1546 1547 #define MEI_CFG_TYPE_GSCFI \ 1548 .kind = "gscfi" 1549 1550 #define MEI_CFG_FW_SPS_IGN \ 1551 .quirk_probe = mei_me_fw_type_sps_ign 1552 1553 #define MEI_CFG_FW_VER_SUPP \ 1554 .fw_ver_supported = 1 1555 1556 #define MEI_CFG_ICH_HFS \ 1557 .fw_status.count = 0 1558 1559 #define MEI_CFG_ICH10_HFS \ 1560 .fw_status.count = 1, \ 1561 .fw_status.status[0] = PCI_CFG_HFS_1 1562 1563 #define MEI_CFG_PCH_HFS \ 1564 .fw_status.count = 2, \ 1565 .fw_status.status[0] = PCI_CFG_HFS_1, \ 1566 .fw_status.status[1] = PCI_CFG_HFS_2 1567 1568 #define MEI_CFG_PCH8_HFS \ 1569 .fw_status.count = 6, \ 1570 .fw_status.status[0] = PCI_CFG_HFS_1, \ 1571 .fw_status.status[1] = PCI_CFG_HFS_2, \ 1572 .fw_status.status[2] = PCI_CFG_HFS_3, \ 1573 .fw_status.status[3] = PCI_CFG_HFS_4, \ 1574 .fw_status.status[4] = PCI_CFG_HFS_5, \ 1575 .fw_status.status[5] = PCI_CFG_HFS_6 1576 1577 #define MEI_CFG_DMA_128 \ 1578 .dma_size[DMA_DSCR_HOST] = SZ_128K, \ 1579 .dma_size[DMA_DSCR_DEVICE] = SZ_128K, \ 1580 .dma_size[DMA_DSCR_CTRL] = PAGE_SIZE 1581 1582 #define MEI_CFG_TRC \ 1583 .hw_trc_supported = 1 1584 1585 /* ICH Legacy devices */ 1586 static const struct mei_cfg mei_me_ich_cfg = { 1587 MEI_CFG_ICH_HFS, 1588 }; 1589 1590 /* ICH devices */ 1591 static const struct mei_cfg mei_me_ich10_cfg = { 1592 MEI_CFG_ICH10_HFS, 1593 }; 1594 1595 /* PCH6 devices */ 1596 static const struct mei_cfg mei_me_pch6_cfg = { 1597 MEI_CFG_PCH_HFS, 1598 }; 1599 1600 /* PCH7 devices */ 1601 static const struct mei_cfg mei_me_pch7_cfg = { 1602 MEI_CFG_PCH_HFS, 1603 MEI_CFG_FW_VER_SUPP, 1604 }; 1605 1606 /* PCH Cougar Point and Patsburg with quirk for Node Manager exclusion */ 1607 static const struct mei_cfg mei_me_pch_cpt_pbg_cfg = { 1608 MEI_CFG_PCH_HFS, 1609 MEI_CFG_FW_VER_SUPP, 1610 MEI_CFG_FW_NM, 1611 }; 1612 1613 /* PCH8 Lynx Point and newer devices */ 1614 static const struct mei_cfg mei_me_pch8_cfg = { 1615 MEI_CFG_PCH8_HFS, 1616 MEI_CFG_FW_VER_SUPP, 1617 }; 1618 1619 /* PCH8 Lynx Point and newer devices - iTouch */ 1620 static const struct mei_cfg mei_me_pch8_itouch_cfg = { 1621 MEI_CFG_KIND_ITOUCH, 1622 MEI_CFG_PCH8_HFS, 1623 MEI_CFG_FW_VER_SUPP, 1624 }; 1625 1626 /* PCH8 Lynx Point with quirk for SPS Firmware exclusion */ 1627 static const struct mei_cfg mei_me_pch8_sps_4_cfg = { 1628 MEI_CFG_PCH8_HFS, 1629 MEI_CFG_FW_VER_SUPP, 1630 MEI_CFG_FW_SPS_4, 1631 }; 1632 1633 /* LBG with quirk for SPS (4.0) Firmware exclusion */ 1634 static const struct mei_cfg mei_me_pch12_sps_4_cfg = { 1635 MEI_CFG_PCH8_HFS, 1636 MEI_CFG_FW_VER_SUPP, 1637 MEI_CFG_FW_SPS_4, 1638 }; 1639 1640 /* Cannon Lake and newer devices */ 1641 static const struct mei_cfg mei_me_pch12_cfg = { 1642 MEI_CFG_PCH8_HFS, 1643 MEI_CFG_FW_VER_SUPP, 1644 MEI_CFG_DMA_128, 1645 }; 1646 1647 /* Cannon Lake with quirk for SPS 5.0 and newer Firmware exclusion */ 1648 static const struct mei_cfg mei_me_pch12_sps_cfg = { 1649 MEI_CFG_PCH8_HFS, 1650 MEI_CFG_FW_VER_SUPP, 1651 MEI_CFG_DMA_128, 1652 MEI_CFG_FW_SPS_IGN, 1653 }; 1654 1655 /* Cannon Lake itouch with quirk for SPS 5.0 and newer Firmware exclusion 1656 * w/o DMA support. 1657 */ 1658 static const struct mei_cfg mei_me_pch12_itouch_sps_cfg = { 1659 MEI_CFG_KIND_ITOUCH, 1660 MEI_CFG_PCH8_HFS, 1661 MEI_CFG_FW_VER_SUPP, 1662 MEI_CFG_FW_SPS_IGN, 1663 }; 1664 1665 /* Tiger Lake and newer devices */ 1666 static const struct mei_cfg mei_me_pch15_cfg = { 1667 MEI_CFG_PCH8_HFS, 1668 MEI_CFG_FW_VER_SUPP, 1669 MEI_CFG_DMA_128, 1670 MEI_CFG_TRC, 1671 }; 1672 1673 /* Tiger Lake with quirk for SPS 5.0 and newer Firmware exclusion */ 1674 static const struct mei_cfg mei_me_pch15_sps_cfg = { 1675 MEI_CFG_PCH8_HFS, 1676 MEI_CFG_FW_VER_SUPP, 1677 MEI_CFG_DMA_128, 1678 MEI_CFG_TRC, 1679 MEI_CFG_FW_SPS_IGN, 1680 }; 1681 1682 /* Graphics System Controller */ 1683 static const struct mei_cfg mei_me_gsc_cfg = { 1684 MEI_CFG_TYPE_GSC, 1685 MEI_CFG_PCH8_HFS, 1686 MEI_CFG_FW_VER_SUPP, 1687 }; 1688 1689 /* Graphics System Controller Firmware Interface */ 1690 static const struct mei_cfg mei_me_gscfi_cfg = { 1691 MEI_CFG_TYPE_GSCFI, 1692 MEI_CFG_PCH8_HFS, 1693 MEI_CFG_FW_VER_SUPP, 1694 }; 1695 1696 /* 1697 * mei_cfg_list - A list of platform platform specific configurations. 1698 * Note: has to be synchronized with enum mei_cfg_idx. 1699 */ 1700 static const struct mei_cfg *const mei_cfg_list[] = { 1701 [MEI_ME_UNDEF_CFG] = NULL, 1702 [MEI_ME_ICH_CFG] = &mei_me_ich_cfg, 1703 [MEI_ME_ICH10_CFG] = &mei_me_ich10_cfg, 1704 [MEI_ME_PCH6_CFG] = &mei_me_pch6_cfg, 1705 [MEI_ME_PCH7_CFG] = &mei_me_pch7_cfg, 1706 [MEI_ME_PCH_CPT_PBG_CFG] = &mei_me_pch_cpt_pbg_cfg, 1707 [MEI_ME_PCH8_CFG] = &mei_me_pch8_cfg, 1708 [MEI_ME_PCH8_ITOUCH_CFG] = &mei_me_pch8_itouch_cfg, 1709 [MEI_ME_PCH8_SPS_4_CFG] = &mei_me_pch8_sps_4_cfg, 1710 [MEI_ME_PCH12_CFG] = &mei_me_pch12_cfg, 1711 [MEI_ME_PCH12_SPS_4_CFG] = &mei_me_pch12_sps_4_cfg, 1712 [MEI_ME_PCH12_SPS_CFG] = &mei_me_pch12_sps_cfg, 1713 [MEI_ME_PCH12_SPS_ITOUCH_CFG] = &mei_me_pch12_itouch_sps_cfg, 1714 [MEI_ME_PCH15_CFG] = &mei_me_pch15_cfg, 1715 [MEI_ME_PCH15_SPS_CFG] = &mei_me_pch15_sps_cfg, 1716 [MEI_ME_GSC_CFG] = &mei_me_gsc_cfg, 1717 [MEI_ME_GSCFI_CFG] = &mei_me_gscfi_cfg, 1718 }; 1719 1720 const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx) 1721 { 1722 BUILD_BUG_ON(ARRAY_SIZE(mei_cfg_list) != MEI_ME_NUM_CFG); 1723 1724 if (idx >= MEI_ME_NUM_CFG) 1725 return NULL; 1726 1727 return mei_cfg_list[idx]; 1728 } 1729 EXPORT_SYMBOL_GPL(mei_me_get_cfg); 1730 1731 /** 1732 * mei_me_dev_init - allocates and initializes the mei device structure 1733 * 1734 * @parent: device associated with physical device (pci/platform) 1735 * @cfg: per device generation config 1736 * @slow_fw: configure longer timeouts as FW is slow 1737 * 1738 * Return: The mei_device pointer on success, NULL on failure. 1739 */ 1740 struct mei_device *mei_me_dev_init(struct device *parent, 1741 const struct mei_cfg *cfg, bool slow_fw) 1742 { 1743 struct mei_device *dev; 1744 struct mei_me_hw *hw; 1745 int i; 1746 1747 dev = devm_kzalloc(parent, sizeof(*dev) + sizeof(*hw), GFP_KERNEL); 1748 if (!dev) 1749 return NULL; 1750 1751 hw = to_me_hw(dev); 1752 1753 for (i = 0; i < DMA_DSCR_NUM; i++) 1754 dev->dr_dscr[i].size = cfg->dma_size[i]; 1755 1756 mei_device_init(dev, parent, slow_fw, &mei_me_hw_ops); 1757 hw->cfg = cfg; 1758 1759 dev->fw_f_fw_ver_supported = cfg->fw_ver_supported; 1760 1761 dev->kind = cfg->kind; 1762 1763 return dev; 1764 } 1765 EXPORT_SYMBOL_GPL(mei_me_dev_init); 1766