1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2012 Stefan Roese <sr@denx.de> 4 */ 5 6 #include <linux/device.h> 7 #include <linux/firmware.h> 8 #include <linux/module.h> 9 #include <linux/errno.h> 10 #include <linux/kernel.h> 11 #include <linux/spi/spi.h> 12 #include <linux/platform_device.h> 13 #include <linux/delay.h> 14 #include <asm/unaligned.h> 15 16 #define FIRMWARE_NAME "lattice-ecp3.bit" 17 18 /* 19 * The JTAG ID's of the supported FPGA's. The ID is 32bit wide 20 * reversed as noted in the manual. 21 */ 22 #define ID_ECP3_17 0xc2088080 23 #define ID_ECP3_35 0xc2048080 24 25 /* FPGA commands */ 26 #define FPGA_CMD_READ_ID 0x07 /* plus 24 bits */ 27 #define FPGA_CMD_READ_STATUS 0x09 /* plus 24 bits */ 28 #define FPGA_CMD_CLEAR 0x70 29 #define FPGA_CMD_REFRESH 0x71 30 #define FPGA_CMD_WRITE_EN 0x4a /* plus 2 bits */ 31 #define FPGA_CMD_WRITE_DIS 0x4f /* plus 8 bits */ 32 #define FPGA_CMD_WRITE_INC 0x41 /* plus 0 bits */ 33 34 /* 35 * The status register is 32bit revered, DONE is bit 17 from the TN1222.pdf 36 * (LatticeECP3 Slave SPI Port User's Guide) 37 */ 38 #define FPGA_STATUS_DONE 0x00004000 39 #define FPGA_STATUS_CLEARED 0x00010000 40 41 #define FPGA_CLEAR_TIMEOUT 5000 /* max. 5000ms for FPGA clear */ 42 #define FPGA_CLEAR_MSLEEP 10 43 #define FPGA_CLEAR_LOOP_COUNT (FPGA_CLEAR_TIMEOUT / FPGA_CLEAR_MSLEEP) 44 45 struct fpga_data { 46 struct completion fw_loaded; 47 }; 48 49 struct ecp3_dev { 50 u32 jedec_id; 51 char *name; 52 }; 53 54 static const struct ecp3_dev ecp3_dev[] = { 55 { 56 .jedec_id = ID_ECP3_17, 57 .name = "Lattice ECP3-17", 58 }, 59 { 60 .jedec_id = ID_ECP3_35, 61 .name = "Lattice ECP3-35", 62 }, 63 }; 64 65 static void firmware_load(const struct firmware *fw, void *context) 66 { 67 struct spi_device *spi = (struct spi_device *)context; 68 struct fpga_data *data = spi_get_drvdata(spi); 69 u8 *buffer; 70 int ret; 71 u8 txbuf[8]; 72 u8 rxbuf[8]; 73 int rx_len = 8; 74 int i; 75 u32 jedec_id; 76 u32 status; 77 78 if (fw == NULL) { 79 dev_err(&spi->dev, "Cannot load firmware, aborting\n"); 80 return; 81 } 82 83 if (fw->size == 0) { 84 dev_err(&spi->dev, "Error: Firmware size is 0!\n"); 85 return; 86 } 87 88 /* Fill dummy data (24 stuffing bits for commands) */ 89 txbuf[1] = 0x00; 90 txbuf[2] = 0x00; 91 txbuf[3] = 0x00; 92 93 /* Trying to speak with the FPGA via SPI... */ 94 txbuf[0] = FPGA_CMD_READ_ID; 95 ret = spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len); 96 jedec_id = get_unaligned_be32(&rxbuf[4]); 97 dev_dbg(&spi->dev, "FPGA JTAG ID=%08x\n", jedec_id); 98 99 for (i = 0; i < ARRAY_SIZE(ecp3_dev); i++) { 100 if (jedec_id == ecp3_dev[i].jedec_id) 101 break; 102 } 103 if (i == ARRAY_SIZE(ecp3_dev)) { 104 dev_err(&spi->dev, 105 "Error: No supported FPGA detected (JEDEC_ID=%08x)!\n", 106 jedec_id); 107 return; 108 } 109 110 dev_info(&spi->dev, "FPGA %s detected\n", ecp3_dev[i].name); 111 112 txbuf[0] = FPGA_CMD_READ_STATUS; 113 ret = spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len); 114 status = get_unaligned_be32(&rxbuf[4]); 115 dev_dbg(&spi->dev, "FPGA Status=%08x\n", status); 116 117 buffer = kzalloc(fw->size + 8, GFP_KERNEL); 118 if (!buffer) { 119 dev_err(&spi->dev, "Error: Can't allocate memory!\n"); 120 return; 121 } 122 123 /* 124 * Insert WRITE_INC command into stream (one SPI frame) 125 */ 126 buffer[0] = FPGA_CMD_WRITE_INC; 127 buffer[1] = 0xff; 128 buffer[2] = 0xff; 129 buffer[3] = 0xff; 130 memcpy(buffer + 4, fw->data, fw->size); 131 132 txbuf[0] = FPGA_CMD_REFRESH; 133 ret = spi_write(spi, txbuf, 4); 134 135 txbuf[0] = FPGA_CMD_WRITE_EN; 136 ret = spi_write(spi, txbuf, 4); 137 138 txbuf[0] = FPGA_CMD_CLEAR; 139 ret = spi_write(spi, txbuf, 4); 140 141 /* 142 * Wait for FPGA memory to become cleared 143 */ 144 for (i = 0; i < FPGA_CLEAR_LOOP_COUNT; i++) { 145 txbuf[0] = FPGA_CMD_READ_STATUS; 146 ret = spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len); 147 status = get_unaligned_be32(&rxbuf[4]); 148 if (status == FPGA_STATUS_CLEARED) 149 break; 150 151 msleep(FPGA_CLEAR_MSLEEP); 152 } 153 154 if (i == FPGA_CLEAR_LOOP_COUNT) { 155 dev_err(&spi->dev, 156 "Error: Timeout waiting for FPGA to clear (status=%08x)!\n", 157 status); 158 kfree(buffer); 159 return; 160 } 161 162 dev_info(&spi->dev, "Configuring the FPGA...\n"); 163 ret = spi_write(spi, buffer, fw->size + 8); 164 165 txbuf[0] = FPGA_CMD_WRITE_DIS; 166 ret = spi_write(spi, txbuf, 4); 167 168 txbuf[0] = FPGA_CMD_READ_STATUS; 169 ret = spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len); 170 status = get_unaligned_be32(&rxbuf[4]); 171 dev_dbg(&spi->dev, "FPGA Status=%08x\n", status); 172 173 /* Check result */ 174 if (status & FPGA_STATUS_DONE) 175 dev_info(&spi->dev, "FPGA successfully configured!\n"); 176 else 177 dev_info(&spi->dev, "FPGA not configured (DONE not set)\n"); 178 179 /* 180 * Don't forget to release the firmware again 181 */ 182 release_firmware(fw); 183 184 kfree(buffer); 185 186 complete(&data->fw_loaded); 187 } 188 189 static int lattice_ecp3_probe(struct spi_device *spi) 190 { 191 struct fpga_data *data; 192 int err; 193 194 data = devm_kzalloc(&spi->dev, sizeof(*data), GFP_KERNEL); 195 if (!data) { 196 dev_err(&spi->dev, "Memory allocation for fpga_data failed\n"); 197 return -ENOMEM; 198 } 199 spi_set_drvdata(spi, data); 200 201 init_completion(&data->fw_loaded); 202 err = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG, 203 FIRMWARE_NAME, &spi->dev, 204 GFP_KERNEL, spi, firmware_load); 205 if (err) { 206 dev_err(&spi->dev, "Firmware loading failed with %d!\n", err); 207 return err; 208 } 209 210 dev_info(&spi->dev, "FPGA bitstream configuration driver registered\n"); 211 212 return 0; 213 } 214 215 static int lattice_ecp3_remove(struct spi_device *spi) 216 { 217 struct fpga_data *data = spi_get_drvdata(spi); 218 219 wait_for_completion(&data->fw_loaded); 220 221 return 0; 222 } 223 224 static const struct spi_device_id lattice_ecp3_id[] = { 225 { "ecp3-17", 0 }, 226 { "ecp3-35", 0 }, 227 { } 228 }; 229 MODULE_DEVICE_TABLE(spi, lattice_ecp3_id); 230 231 static struct spi_driver lattice_ecp3_driver = { 232 .driver = { 233 .name = "lattice-ecp3", 234 }, 235 .probe = lattice_ecp3_probe, 236 .remove = lattice_ecp3_remove, 237 .id_table = lattice_ecp3_id, 238 }; 239 240 module_spi_driver(lattice_ecp3_driver); 241 242 MODULE_AUTHOR("Stefan Roese <sr@denx.de>"); 243 MODULE_DESCRIPTION("Lattice ECP3 FPGA configuration via SPI"); 244 MODULE_LICENSE("GPL"); 245 MODULE_FIRMWARE(FIRMWARE_NAME); 246