1 /*
2  * Copyright (C) 2012 Stefan Roese <sr@denx.de>
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License as published by
6  * the Free Software Foundation; either version 2 of the License, or
7  * (at your option) any later version.
8  */
9 
10 #include <linux/device.h>
11 #include <linux/firmware.h>
12 #include <linux/module.h>
13 #include <linux/errno.h>
14 #include <linux/kernel.h>
15 #include <linux/spi/spi.h>
16 #include <linux/platform_device.h>
17 #include <linux/delay.h>
18 
19 #define FIRMWARE_NAME	"lattice-ecp3.bit"
20 
21 /*
22  * The JTAG ID's of the supported FPGA's. The ID is 32bit wide
23  * reversed as noted in the manual.
24  */
25 #define ID_ECP3_17	0xc2088080
26 #define ID_ECP3_35	0xc2048080
27 
28 /* FPGA commands */
29 #define FPGA_CMD_READ_ID	0x07	/* plus 24 bits */
30 #define FPGA_CMD_READ_STATUS	0x09	/* plus 24 bits */
31 #define FPGA_CMD_CLEAR		0x70
32 #define FPGA_CMD_REFRESH	0x71
33 #define FPGA_CMD_WRITE_EN	0x4a	/* plus 2 bits */
34 #define FPGA_CMD_WRITE_DIS	0x4f	/* plus 8 bits */
35 #define FPGA_CMD_WRITE_INC	0x41	/* plus 0 bits */
36 
37 /*
38  * The status register is 32bit revered, DONE is bit 17 from the TN1222.pdf
39  * (LatticeECP3 Slave SPI Port User's Guide)
40  */
41 #define FPGA_STATUS_DONE	0x00004000
42 #define FPGA_STATUS_CLEARED	0x00010000
43 
44 #define FPGA_CLEAR_TIMEOUT	5000	/* max. 5000ms for FPGA clear */
45 #define FPGA_CLEAR_MSLEEP	10
46 #define FPGA_CLEAR_LOOP_COUNT	(FPGA_CLEAR_TIMEOUT / FPGA_CLEAR_MSLEEP)
47 
48 struct fpga_data {
49 	struct completion fw_loaded;
50 };
51 
52 struct ecp3_dev {
53 	u32 jedec_id;
54 	char *name;
55 };
56 
57 static const struct ecp3_dev ecp3_dev[] = {
58 	{
59 		.jedec_id = ID_ECP3_17,
60 		.name = "Lattice ECP3-17",
61 	},
62 	{
63 		.jedec_id = ID_ECP3_35,
64 		.name = "Lattice ECP3-35",
65 	},
66 };
67 
68 static void firmware_load(const struct firmware *fw, void *context)
69 {
70 	struct spi_device *spi = (struct spi_device *)context;
71 	struct fpga_data *data = spi_get_drvdata(spi);
72 	u8 *buffer;
73 	int ret;
74 	u8 txbuf[8];
75 	u8 rxbuf[8];
76 	int rx_len = 8;
77 	int i;
78 	u32 jedec_id;
79 	u32 status;
80 
81 	if (fw->size == 0) {
82 		dev_err(&spi->dev, "Error: Firmware size is 0!\n");
83 		return;
84 	}
85 
86 	/* Fill dummy data (24 stuffing bits for commands) */
87 	txbuf[1] = 0x00;
88 	txbuf[2] = 0x00;
89 	txbuf[3] = 0x00;
90 
91 	/* Trying to speak with the FPGA via SPI... */
92 	txbuf[0] = FPGA_CMD_READ_ID;
93 	ret = spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
94 	dev_dbg(&spi->dev, "FPGA JTAG ID=%08x\n", *(u32 *)&rxbuf[4]);
95 	jedec_id = *(u32 *)&rxbuf[4];
96 
97 	for (i = 0; i < ARRAY_SIZE(ecp3_dev); i++) {
98 		if (jedec_id == ecp3_dev[i].jedec_id)
99 			break;
100 	}
101 	if (i == ARRAY_SIZE(ecp3_dev)) {
102 		dev_err(&spi->dev,
103 			"Error: No supported FPGA detected (JEDEC_ID=%08x)!\n",
104 			jedec_id);
105 		return;
106 	}
107 
108 	dev_info(&spi->dev, "FPGA %s detected\n", ecp3_dev[i].name);
109 
110 	txbuf[0] = FPGA_CMD_READ_STATUS;
111 	ret = spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
112 	dev_dbg(&spi->dev, "FPGA Status=%08x\n", *(u32 *)&rxbuf[4]);
113 
114 	buffer = kzalloc(fw->size + 8, GFP_KERNEL);
115 	if (!buffer) {
116 		dev_err(&spi->dev, "Error: Can't allocate memory!\n");
117 		return;
118 	}
119 
120 	/*
121 	 * Insert WRITE_INC command into stream (one SPI frame)
122 	 */
123 	buffer[0] = FPGA_CMD_WRITE_INC;
124 	buffer[1] = 0xff;
125 	buffer[2] = 0xff;
126 	buffer[3] = 0xff;
127 	memcpy(buffer + 4, fw->data, fw->size);
128 
129 	txbuf[0] = FPGA_CMD_REFRESH;
130 	ret = spi_write(spi, txbuf, 4);
131 
132 	txbuf[0] = FPGA_CMD_WRITE_EN;
133 	ret = spi_write(spi, txbuf, 4);
134 
135 	txbuf[0] = FPGA_CMD_CLEAR;
136 	ret = spi_write(spi, txbuf, 4);
137 
138 	/*
139 	 * Wait for FPGA memory to become cleared
140 	 */
141 	for (i = 0; i < FPGA_CLEAR_LOOP_COUNT; i++) {
142 		txbuf[0] = FPGA_CMD_READ_STATUS;
143 		ret = spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
144 		status = *(u32 *)&rxbuf[4];
145 		if (status == FPGA_STATUS_CLEARED)
146 			break;
147 
148 		msleep(FPGA_CLEAR_MSLEEP);
149 	}
150 
151 	if (i == FPGA_CLEAR_LOOP_COUNT) {
152 		dev_err(&spi->dev,
153 			"Error: Timeout waiting for FPGA to clear (status=%08x)!\n",
154 			status);
155 		kfree(buffer);
156 		return;
157 	}
158 
159 	dev_info(&spi->dev, "Configuring the FPGA...\n");
160 	ret = spi_write(spi, buffer, fw->size + 8);
161 
162 	txbuf[0] = FPGA_CMD_WRITE_DIS;
163 	ret = spi_write(spi, txbuf, 4);
164 
165 	txbuf[0] = FPGA_CMD_READ_STATUS;
166 	ret = spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
167 	dev_dbg(&spi->dev, "FPGA Status=%08x\n", *(u32 *)&rxbuf[4]);
168 	status = *(u32 *)&rxbuf[4];
169 
170 	/* Check result */
171 	if (status & FPGA_STATUS_DONE)
172 		dev_info(&spi->dev, "FPGA successfully configured!\n");
173 	else
174 		dev_info(&spi->dev, "FPGA not configured (DONE not set)\n");
175 
176 	/*
177 	 * Don't forget to release the firmware again
178 	 */
179 	release_firmware(fw);
180 
181 	kfree(buffer);
182 
183 	complete(&data->fw_loaded);
184 }
185 
186 static int lattice_ecp3_probe(struct spi_device *spi)
187 {
188 	struct fpga_data *data;
189 	int err;
190 
191 	data = devm_kzalloc(&spi->dev, sizeof(*data), GFP_KERNEL);
192 	if (!data) {
193 		dev_err(&spi->dev, "Memory allocation for fpga_data failed\n");
194 		return -ENOMEM;
195 	}
196 	spi_set_drvdata(spi, data);
197 
198 	init_completion(&data->fw_loaded);
199 	err = request_firmware_nowait(THIS_MODULE, FW_ACTION_NOHOTPLUG,
200 				      FIRMWARE_NAME, &spi->dev,
201 				      GFP_KERNEL, spi, firmware_load);
202 	if (err) {
203 		dev_err(&spi->dev, "Firmware loading failed with %d!\n", err);
204 		return err;
205 	}
206 
207 	dev_info(&spi->dev, "FPGA bitstream configuration driver registered\n");
208 
209 	return 0;
210 }
211 
212 static int lattice_ecp3_remove(struct spi_device *spi)
213 {
214 	struct fpga_data *data = spi_get_drvdata(spi);
215 
216 	wait_for_completion(&data->fw_loaded);
217 
218 	return 0;
219 }
220 
221 static const struct spi_device_id lattice_ecp3_id[] = {
222 	{ "ecp3-17", 0 },
223 	{ "ecp3-35", 0 },
224 	{ }
225 };
226 MODULE_DEVICE_TABLE(spi, lattice_ecp3_id);
227 
228 static struct spi_driver lattice_ecp3_driver = {
229 	.driver = {
230 		.name = "lattice-ecp3",
231 		.owner = THIS_MODULE,
232 	},
233 	.probe = lattice_ecp3_probe,
234 	.remove = lattice_ecp3_remove,
235 	.id_table = lattice_ecp3_id,
236 };
237 
238 module_spi_driver(lattice_ecp3_driver);
239 
240 MODULE_AUTHOR("Stefan Roese <sr@denx.de>");
241 MODULE_DESCRIPTION("Lattice ECP3 FPGA configuration via SPI");
242 MODULE_LICENSE("GPL");
243