12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2781551dfSStefan Roese /* 3781551dfSStefan Roese * Copyright (C) 2012 Stefan Roese <sr@denx.de> 4781551dfSStefan Roese */ 5781551dfSStefan Roese 6781551dfSStefan Roese #include <linux/device.h> 7781551dfSStefan Roese #include <linux/firmware.h> 8781551dfSStefan Roese #include <linux/module.h> 9781551dfSStefan Roese #include <linux/errno.h> 10781551dfSStefan Roese #include <linux/kernel.h> 11781551dfSStefan Roese #include <linux/spi/spi.h> 12781551dfSStefan Roese #include <linux/platform_device.h> 13781551dfSStefan Roese #include <linux/delay.h> 14ee531142SJean-Michel Hautbois #include <asm/unaligned.h> 15781551dfSStefan Roese 16781551dfSStefan Roese #define FIRMWARE_NAME "lattice-ecp3.bit" 17781551dfSStefan Roese 18781551dfSStefan Roese /* 19781551dfSStefan Roese * The JTAG ID's of the supported FPGA's. The ID is 32bit wide 20781551dfSStefan Roese * reversed as noted in the manual. 21781551dfSStefan Roese */ 22781551dfSStefan Roese #define ID_ECP3_17 0xc2088080 23781551dfSStefan Roese #define ID_ECP3_35 0xc2048080 24781551dfSStefan Roese 25781551dfSStefan Roese /* FPGA commands */ 26781551dfSStefan Roese #define FPGA_CMD_READ_ID 0x07 /* plus 24 bits */ 27781551dfSStefan Roese #define FPGA_CMD_READ_STATUS 0x09 /* plus 24 bits */ 28781551dfSStefan Roese #define FPGA_CMD_CLEAR 0x70 29781551dfSStefan Roese #define FPGA_CMD_REFRESH 0x71 30781551dfSStefan Roese #define FPGA_CMD_WRITE_EN 0x4a /* plus 2 bits */ 31781551dfSStefan Roese #define FPGA_CMD_WRITE_DIS 0x4f /* plus 8 bits */ 32781551dfSStefan Roese #define FPGA_CMD_WRITE_INC 0x41 /* plus 0 bits */ 33781551dfSStefan Roese 34781551dfSStefan Roese /* 35781551dfSStefan Roese * The status register is 32bit revered, DONE is bit 17 from the TN1222.pdf 36781551dfSStefan Roese * (LatticeECP3 Slave SPI Port User's Guide) 37781551dfSStefan Roese */ 38781551dfSStefan Roese #define FPGA_STATUS_DONE 0x00004000 39781551dfSStefan Roese #define FPGA_STATUS_CLEARED 0x00010000 40781551dfSStefan Roese 41781551dfSStefan Roese #define FPGA_CLEAR_TIMEOUT 5000 /* max. 5000ms for FPGA clear */ 42781551dfSStefan Roese #define FPGA_CLEAR_MSLEEP 10 43781551dfSStefan Roese #define FPGA_CLEAR_LOOP_COUNT (FPGA_CLEAR_TIMEOUT / FPGA_CLEAR_MSLEEP) 44781551dfSStefan Roese 45781551dfSStefan Roese struct fpga_data { 46781551dfSStefan Roese struct completion fw_loaded; 47781551dfSStefan Roese }; 48781551dfSStefan Roese 49781551dfSStefan Roese struct ecp3_dev { 50781551dfSStefan Roese u32 jedec_id; 51781551dfSStefan Roese char *name; 52781551dfSStefan Roese }; 53781551dfSStefan Roese 54781551dfSStefan Roese static const struct ecp3_dev ecp3_dev[] = { 55781551dfSStefan Roese { 56781551dfSStefan Roese .jedec_id = ID_ECP3_17, 57781551dfSStefan Roese .name = "Lattice ECP3-17", 58781551dfSStefan Roese }, 59781551dfSStefan Roese { 60781551dfSStefan Roese .jedec_id = ID_ECP3_35, 61781551dfSStefan Roese .name = "Lattice ECP3-35", 62781551dfSStefan Roese }, 63781551dfSStefan Roese }; 64781551dfSStefan Roese 65781551dfSStefan Roese static void firmware_load(const struct firmware *fw, void *context) 66781551dfSStefan Roese { 67781551dfSStefan Roese struct spi_device *spi = (struct spi_device *)context; 68a864ec76SJingoo Han struct fpga_data *data = spi_get_drvdata(spi); 69781551dfSStefan Roese u8 *buffer; 70781551dfSStefan Roese u8 txbuf[8]; 71781551dfSStefan Roese u8 rxbuf[8]; 72781551dfSStefan Roese int rx_len = 8; 73781551dfSStefan Roese int i; 74781551dfSStefan Roese u32 jedec_id; 75781551dfSStefan Roese u32 status; 76781551dfSStefan Roese 773f0d97d9SJean-Michel Hautbois if (fw == NULL) { 783f0d97d9SJean-Michel Hautbois dev_err(&spi->dev, "Cannot load firmware, aborting\n"); 79*fcee5ce5SWei Yongjun goto out; 803f0d97d9SJean-Michel Hautbois } 813f0d97d9SJean-Michel Hautbois 82781551dfSStefan Roese if (fw->size == 0) { 83781551dfSStefan Roese dev_err(&spi->dev, "Error: Firmware size is 0!\n"); 84*fcee5ce5SWei Yongjun goto out; 85781551dfSStefan Roese } 86781551dfSStefan Roese 87781551dfSStefan Roese /* Fill dummy data (24 stuffing bits for commands) */ 88781551dfSStefan Roese txbuf[1] = 0x00; 89781551dfSStefan Roese txbuf[2] = 0x00; 90781551dfSStefan Roese txbuf[3] = 0x00; 91781551dfSStefan Roese 92781551dfSStefan Roese /* Trying to speak with the FPGA via SPI... */ 93781551dfSStefan Roese txbuf[0] = FPGA_CMD_READ_ID; 948bc056e8SLee Jones spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len); 95ee531142SJean-Michel Hautbois jedec_id = get_unaligned_be32(&rxbuf[4]); 96ee531142SJean-Michel Hautbois dev_dbg(&spi->dev, "FPGA JTAG ID=%08x\n", jedec_id); 97781551dfSStefan Roese 98781551dfSStefan Roese for (i = 0; i < ARRAY_SIZE(ecp3_dev); i++) { 99781551dfSStefan Roese if (jedec_id == ecp3_dev[i].jedec_id) 100781551dfSStefan Roese break; 101781551dfSStefan Roese } 102781551dfSStefan Roese if (i == ARRAY_SIZE(ecp3_dev)) { 103781551dfSStefan Roese dev_err(&spi->dev, 104781551dfSStefan Roese "Error: No supported FPGA detected (JEDEC_ID=%08x)!\n", 105781551dfSStefan Roese jedec_id); 106*fcee5ce5SWei Yongjun goto out; 107781551dfSStefan Roese } 108781551dfSStefan Roese 109781551dfSStefan Roese dev_info(&spi->dev, "FPGA %s detected\n", ecp3_dev[i].name); 110781551dfSStefan Roese 111781551dfSStefan Roese txbuf[0] = FPGA_CMD_READ_STATUS; 1128bc056e8SLee Jones spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len); 113ee531142SJean-Michel Hautbois status = get_unaligned_be32(&rxbuf[4]); 114ee531142SJean-Michel Hautbois dev_dbg(&spi->dev, "FPGA Status=%08x\n", status); 115781551dfSStefan Roese 116781551dfSStefan Roese buffer = kzalloc(fw->size + 8, GFP_KERNEL); 117781551dfSStefan Roese if (!buffer) { 118781551dfSStefan Roese dev_err(&spi->dev, "Error: Can't allocate memory!\n"); 119*fcee5ce5SWei Yongjun goto out; 120781551dfSStefan Roese } 121781551dfSStefan Roese 122781551dfSStefan Roese /* 123781551dfSStefan Roese * Insert WRITE_INC command into stream (one SPI frame) 124781551dfSStefan Roese */ 125781551dfSStefan Roese buffer[0] = FPGA_CMD_WRITE_INC; 126781551dfSStefan Roese buffer[1] = 0xff; 127781551dfSStefan Roese buffer[2] = 0xff; 128781551dfSStefan Roese buffer[3] = 0xff; 129781551dfSStefan Roese memcpy(buffer + 4, fw->data, fw->size); 130781551dfSStefan Roese 131781551dfSStefan Roese txbuf[0] = FPGA_CMD_REFRESH; 1328bc056e8SLee Jones spi_write(spi, txbuf, 4); 133781551dfSStefan Roese 134781551dfSStefan Roese txbuf[0] = FPGA_CMD_WRITE_EN; 1358bc056e8SLee Jones spi_write(spi, txbuf, 4); 136781551dfSStefan Roese 137781551dfSStefan Roese txbuf[0] = FPGA_CMD_CLEAR; 1388bc056e8SLee Jones spi_write(spi, txbuf, 4); 139781551dfSStefan Roese 140781551dfSStefan Roese /* 141781551dfSStefan Roese * Wait for FPGA memory to become cleared 142781551dfSStefan Roese */ 143781551dfSStefan Roese for (i = 0; i < FPGA_CLEAR_LOOP_COUNT; i++) { 144781551dfSStefan Roese txbuf[0] = FPGA_CMD_READ_STATUS; 1458bc056e8SLee Jones spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len); 146ee531142SJean-Michel Hautbois status = get_unaligned_be32(&rxbuf[4]); 147781551dfSStefan Roese if (status == FPGA_STATUS_CLEARED) 148781551dfSStefan Roese break; 149781551dfSStefan Roese 150781551dfSStefan Roese msleep(FPGA_CLEAR_MSLEEP); 151781551dfSStefan Roese } 152781551dfSStefan Roese 153781551dfSStefan Roese if (i == FPGA_CLEAR_LOOP_COUNT) { 154781551dfSStefan Roese dev_err(&spi->dev, 155781551dfSStefan Roese "Error: Timeout waiting for FPGA to clear (status=%08x)!\n", 156781551dfSStefan Roese status); 157781551dfSStefan Roese kfree(buffer); 158*fcee5ce5SWei Yongjun goto out; 159781551dfSStefan Roese } 160781551dfSStefan Roese 161781551dfSStefan Roese dev_info(&spi->dev, "Configuring the FPGA...\n"); 1628bc056e8SLee Jones spi_write(spi, buffer, fw->size + 8); 163781551dfSStefan Roese 164781551dfSStefan Roese txbuf[0] = FPGA_CMD_WRITE_DIS; 1658bc056e8SLee Jones spi_write(spi, txbuf, 4); 166781551dfSStefan Roese 167781551dfSStefan Roese txbuf[0] = FPGA_CMD_READ_STATUS; 1688bc056e8SLee Jones spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len); 169ee531142SJean-Michel Hautbois status = get_unaligned_be32(&rxbuf[4]); 170ee531142SJean-Michel Hautbois dev_dbg(&spi->dev, "FPGA Status=%08x\n", status); 171781551dfSStefan Roese 172781551dfSStefan Roese /* Check result */ 173781551dfSStefan Roese if (status & FPGA_STATUS_DONE) 1748b513d0cSMasanari Iida dev_info(&spi->dev, "FPGA successfully configured!\n"); 175781551dfSStefan Roese else 176781551dfSStefan Roese dev_info(&spi->dev, "FPGA not configured (DONE not set)\n"); 177781551dfSStefan Roese 178781551dfSStefan Roese /* 179781551dfSStefan Roese * Don't forget to release the firmware again 180781551dfSStefan Roese */ 181781551dfSStefan Roese release_firmware(fw); 182781551dfSStefan Roese 183781551dfSStefan Roese kfree(buffer); 184*fcee5ce5SWei Yongjun out: 185781551dfSStefan Roese complete(&data->fw_loaded); 186781551dfSStefan Roese } 187781551dfSStefan Roese 1888292ac21SGreg Kroah-Hartman static int lattice_ecp3_probe(struct spi_device *spi) 189781551dfSStefan Roese { 190781551dfSStefan Roese struct fpga_data *data; 191781551dfSStefan Roese int err; 192781551dfSStefan Roese 193781551dfSStefan Roese data = devm_kzalloc(&spi->dev, sizeof(*data), GFP_KERNEL); 194781551dfSStefan Roese if (!data) { 195781551dfSStefan Roese dev_err(&spi->dev, "Memory allocation for fpga_data failed\n"); 196781551dfSStefan Roese return -ENOMEM; 197781551dfSStefan Roese } 198781551dfSStefan Roese spi_set_drvdata(spi, data); 199781551dfSStefan Roese 200781551dfSStefan Roese init_completion(&data->fw_loaded); 2010733d839SShawn Guo err = request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT, 202781551dfSStefan Roese FIRMWARE_NAME, &spi->dev, 203781551dfSStefan Roese GFP_KERNEL, spi, firmware_load); 204781551dfSStefan Roese if (err) { 205781551dfSStefan Roese dev_err(&spi->dev, "Firmware loading failed with %d!\n", err); 206781551dfSStefan Roese return err; 207781551dfSStefan Roese } 208781551dfSStefan Roese 209781551dfSStefan Roese dev_info(&spi->dev, "FPGA bitstream configuration driver registered\n"); 210781551dfSStefan Roese 211781551dfSStefan Roese return 0; 212781551dfSStefan Roese } 213781551dfSStefan Roese 2148292ac21SGreg Kroah-Hartman static int lattice_ecp3_remove(struct spi_device *spi) 215781551dfSStefan Roese { 216781551dfSStefan Roese struct fpga_data *data = spi_get_drvdata(spi); 217781551dfSStefan Roese 218781551dfSStefan Roese wait_for_completion(&data->fw_loaded); 219781551dfSStefan Roese 220781551dfSStefan Roese return 0; 221781551dfSStefan Roese } 222781551dfSStefan Roese 2238292ac21SGreg Kroah-Hartman static const struct spi_device_id lattice_ecp3_id[] = { 224781551dfSStefan Roese { "ecp3-17", 0 }, 225781551dfSStefan Roese { "ecp3-35", 0 }, 226781551dfSStefan Roese { } 227781551dfSStefan Roese }; 228781551dfSStefan Roese MODULE_DEVICE_TABLE(spi, lattice_ecp3_id); 229781551dfSStefan Roese 230781551dfSStefan Roese static struct spi_driver lattice_ecp3_driver = { 231781551dfSStefan Roese .driver = { 232781551dfSStefan Roese .name = "lattice-ecp3", 233781551dfSStefan Roese }, 234781551dfSStefan Roese .probe = lattice_ecp3_probe, 2358292ac21SGreg Kroah-Hartman .remove = lattice_ecp3_remove, 236781551dfSStefan Roese .id_table = lattice_ecp3_id, 237781551dfSStefan Roese }; 238781551dfSStefan Roese 239781551dfSStefan Roese module_spi_driver(lattice_ecp3_driver); 240781551dfSStefan Roese 241781551dfSStefan Roese MODULE_AUTHOR("Stefan Roese <sr@denx.de>"); 242781551dfSStefan Roese MODULE_DESCRIPTION("Lattice ECP3 FPGA configuration via SPI"); 243781551dfSStefan Roese MODULE_LICENSE("GPL"); 244322d3f6aSTakashi Iwai MODULE_FIRMWARE(FIRMWARE_NAME); 245