1 /* 2 * linux/drivers/char/hpilo.h 3 * 4 * Copyright (C) 2008 Hewlett-Packard Development Company, L.P. 5 * David Altobelli <david.altobelli@hp.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #ifndef __HPILO_H 12 #define __HPILO_H 13 14 #define ILO_NAME "hpilo" 15 16 /* max number of open channel control blocks per device, hw limited to 32 */ 17 #define MAX_CCB 8 18 /* max number of supported devices */ 19 #define MAX_ILO_DEV 1 20 /* max number of files */ 21 #define MAX_OPEN (MAX_CCB * MAX_ILO_DEV) 22 /* total wait time in usec */ 23 #define MAX_WAIT_TIME 10000 24 /* per spin wait time in usec */ 25 #define WAIT_TIME 10 26 /* spin counter for open/close delay */ 27 #define MAX_WAIT (MAX_WAIT_TIME / WAIT_TIME) 28 29 /* 30 * Per device, used to track global memory allocations. 31 */ 32 struct ilo_hwinfo { 33 /* mmio registers on device */ 34 char __iomem *mmio_vaddr; 35 36 /* doorbell registers on device */ 37 char __iomem *db_vaddr; 38 39 /* shared memory on device used for channel control blocks */ 40 char __iomem *ram_vaddr; 41 42 /* files corresponding to this device */ 43 struct ccb_data *ccb_alloc[MAX_CCB]; 44 45 struct pci_dev *ilo_dev; 46 47 spinlock_t alloc_lock; 48 spinlock_t fifo_lock; 49 50 struct cdev cdev; 51 }; 52 53 /* offset from mmio_vaddr */ 54 #define DB_OUT 0xD4 55 /* DB_OUT reset bit */ 56 #define DB_RESET 26 57 58 /* 59 * Channel control block. Used to manage hardware queues. 60 * The format must match hw's version. The hw ccb is 128 bytes, 61 * but the context area shouldn't be touched by the driver. 62 */ 63 #define ILOSW_CCB_SZ 64 64 #define ILOHW_CCB_SZ 128 65 struct ccb { 66 union { 67 char *send_fifobar; 68 u64 padding1; 69 } ccb_u1; 70 union { 71 char *send_desc; 72 u64 padding2; 73 } ccb_u2; 74 u64 send_ctrl; 75 76 union { 77 char *recv_fifobar; 78 u64 padding3; 79 } ccb_u3; 80 union { 81 char *recv_desc; 82 u64 padding4; 83 } ccb_u4; 84 u64 recv_ctrl; 85 86 union { 87 char __iomem *db_base; 88 u64 padding5; 89 } ccb_u5; 90 91 u64 channel; 92 93 /* unused context area (64 bytes) */ 94 }; 95 96 /* ccb queue parameters */ 97 #define SENDQ 1 98 #define RECVQ 2 99 #define NR_QENTRY 4 100 #define L2_QENTRY_SZ 12 101 102 /* ccb ctrl bitfields */ 103 #define CTRL_BITPOS_L2SZ 0 104 #define CTRL_BITPOS_FIFOINDEXMASK 4 105 #define CTRL_BITPOS_DESCLIMIT 18 106 #define CTRL_BITPOS_A 30 107 #define CTRL_BITPOS_G 31 108 109 /* ccb doorbell macros */ 110 #define L2_DB_SIZE 14 111 #define ONE_DB_SIZE (1 << L2_DB_SIZE) 112 113 /* 114 * Per fd structure used to track the ccb allocated to that dev file. 115 */ 116 struct ccb_data { 117 /* software version of ccb, using virtual addrs */ 118 struct ccb driver_ccb; 119 120 /* hardware version of ccb, using physical addrs */ 121 struct ccb ilo_ccb; 122 123 /* hardware ccb is written to this shared mapped device memory */ 124 struct ccb __iomem *mapped_ccb; 125 126 /* dma'able memory used for send/recv queues */ 127 void *dma_va; 128 dma_addr_t dma_pa; 129 size_t dma_size; 130 131 /* pointer to hardware device info */ 132 struct ilo_hwinfo *ilo_hw; 133 134 /* usage count, to allow for shared ccb's */ 135 int ccb_cnt; 136 137 /* open wanted exclusive access to this ccb */ 138 int ccb_excl; 139 }; 140 141 /* 142 * FIFO queue structure, shared with hw. 143 */ 144 #define ILO_START_ALIGN 4096 145 #define ILO_CACHE_SZ 128 146 struct fifo { 147 u64 nrents; /* user requested number of fifo entries */ 148 u64 imask; /* mask to extract valid fifo index */ 149 u64 merge; /* O/C bits to merge in during enqueue operation */ 150 u64 reset; /* set to non-zero when the target device resets */ 151 u8 pad_0[ILO_CACHE_SZ - (sizeof(u64) * 4)]; 152 153 u64 head; 154 u8 pad_1[ILO_CACHE_SZ - (sizeof(u64))]; 155 156 u64 tail; 157 u8 pad_2[ILO_CACHE_SZ - (sizeof(u64))]; 158 159 u64 fifobar[1]; 160 }; 161 162 /* convert between struct fifo, and the fifobar, which is saved in the ccb */ 163 #define FIFOHANDLESIZE (sizeof(struct fifo) - sizeof(u64)) 164 #define FIFOBARTOHANDLE(_fifo) \ 165 ((struct fifo *)(((char *)(_fifo)) - FIFOHANDLESIZE)) 166 167 /* the number of qwords to consume from the entry descriptor */ 168 #define ENTRY_BITPOS_QWORDS 0 169 /* descriptor index number (within a specified queue) */ 170 #define ENTRY_BITPOS_DESCRIPTOR 10 171 /* state bit, fifo entry consumed by consumer */ 172 #define ENTRY_BITPOS_C 22 173 /* state bit, fifo entry is occupied */ 174 #define ENTRY_BITPOS_O 23 175 176 #define ENTRY_BITS_QWORDS 10 177 #define ENTRY_BITS_DESCRIPTOR 12 178 #define ENTRY_BITS_C 1 179 #define ENTRY_BITS_O 1 180 #define ENTRY_BITS_TOTAL \ 181 (ENTRY_BITS_C + ENTRY_BITS_O + \ 182 ENTRY_BITS_QWORDS + ENTRY_BITS_DESCRIPTOR) 183 184 /* extract various entry fields */ 185 #define ENTRY_MASK ((1 << ENTRY_BITS_TOTAL) - 1) 186 #define ENTRY_MASK_C (((1 << ENTRY_BITS_C) - 1) << ENTRY_BITPOS_C) 187 #define ENTRY_MASK_O (((1 << ENTRY_BITS_O) - 1) << ENTRY_BITPOS_O) 188 #define ENTRY_MASK_QWORDS \ 189 (((1 << ENTRY_BITS_QWORDS) - 1) << ENTRY_BITPOS_QWORDS) 190 #define ENTRY_MASK_DESCRIPTOR \ 191 (((1 << ENTRY_BITS_DESCRIPTOR) - 1) << ENTRY_BITPOS_DESCRIPTOR) 192 193 #define ENTRY_MASK_NOSTATE (ENTRY_MASK >> (ENTRY_BITS_C + ENTRY_BITS_O)) 194 195 #endif /* __HPILO_H */ 196