1 // SPDX-License-Identifier: GPL-2.0-only 2 /** 3 * IBM Accelerator Family 'GenWQE' 4 * 5 * (C) Copyright IBM Corp. 2013 6 * 7 * Author: Frank Haverkamp <haver@linux.vnet.ibm.com> 8 * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com> 9 * Author: Michael Jung <mijung@gmx.net> 10 * Author: Michael Ruettger <michael@ibmra.de> 11 */ 12 13 /* 14 * Miscelanous functionality used in the other GenWQE driver parts. 15 */ 16 17 #include <linux/kernel.h> 18 #include <linux/sched.h> 19 #include <linux/vmalloc.h> 20 #include <linux/page-flags.h> 21 #include <linux/scatterlist.h> 22 #include <linux/hugetlb.h> 23 #include <linux/iommu.h> 24 #include <linux/pci.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/ctype.h> 27 #include <linux/module.h> 28 #include <linux/platform_device.h> 29 #include <linux/delay.h> 30 #include <asm/pgtable.h> 31 32 #include "genwqe_driver.h" 33 #include "card_base.h" 34 #include "card_ddcb.h" 35 36 /** 37 * __genwqe_writeq() - Write 64-bit register 38 * @cd: genwqe device descriptor 39 * @byte_offs: byte offset within BAR 40 * @val: 64-bit value 41 * 42 * Return: 0 if success; < 0 if error 43 */ 44 int __genwqe_writeq(struct genwqe_dev *cd, u64 byte_offs, u64 val) 45 { 46 struct pci_dev *pci_dev = cd->pci_dev; 47 48 if (cd->err_inject & GENWQE_INJECT_HARDWARE_FAILURE) 49 return -EIO; 50 51 if (cd->mmio == NULL) 52 return -EIO; 53 54 if (pci_channel_offline(pci_dev)) 55 return -EIO; 56 57 __raw_writeq((__force u64)cpu_to_be64(val), cd->mmio + byte_offs); 58 return 0; 59 } 60 61 /** 62 * __genwqe_readq() - Read 64-bit register 63 * @cd: genwqe device descriptor 64 * @byte_offs: offset within BAR 65 * 66 * Return: value from register 67 */ 68 u64 __genwqe_readq(struct genwqe_dev *cd, u64 byte_offs) 69 { 70 if (cd->err_inject & GENWQE_INJECT_HARDWARE_FAILURE) 71 return 0xffffffffffffffffull; 72 73 if ((cd->err_inject & GENWQE_INJECT_GFIR_FATAL) && 74 (byte_offs == IO_SLC_CFGREG_GFIR)) 75 return 0x000000000000ffffull; 76 77 if ((cd->err_inject & GENWQE_INJECT_GFIR_INFO) && 78 (byte_offs == IO_SLC_CFGREG_GFIR)) 79 return 0x00000000ffff0000ull; 80 81 if (cd->mmio == NULL) 82 return 0xffffffffffffffffull; 83 84 return be64_to_cpu((__force __be64)__raw_readq(cd->mmio + byte_offs)); 85 } 86 87 /** 88 * __genwqe_writel() - Write 32-bit register 89 * @cd: genwqe device descriptor 90 * @byte_offs: byte offset within BAR 91 * @val: 32-bit value 92 * 93 * Return: 0 if success; < 0 if error 94 */ 95 int __genwqe_writel(struct genwqe_dev *cd, u64 byte_offs, u32 val) 96 { 97 struct pci_dev *pci_dev = cd->pci_dev; 98 99 if (cd->err_inject & GENWQE_INJECT_HARDWARE_FAILURE) 100 return -EIO; 101 102 if (cd->mmio == NULL) 103 return -EIO; 104 105 if (pci_channel_offline(pci_dev)) 106 return -EIO; 107 108 __raw_writel((__force u32)cpu_to_be32(val), cd->mmio + byte_offs); 109 return 0; 110 } 111 112 /** 113 * __genwqe_readl() - Read 32-bit register 114 * @cd: genwqe device descriptor 115 * @byte_offs: offset within BAR 116 * 117 * Return: Value from register 118 */ 119 u32 __genwqe_readl(struct genwqe_dev *cd, u64 byte_offs) 120 { 121 if (cd->err_inject & GENWQE_INJECT_HARDWARE_FAILURE) 122 return 0xffffffff; 123 124 if (cd->mmio == NULL) 125 return 0xffffffff; 126 127 return be32_to_cpu((__force __be32)__raw_readl(cd->mmio + byte_offs)); 128 } 129 130 /** 131 * genwqe_read_app_id() - Extract app_id 132 * 133 * app_unitcfg need to be filled with valid data first 134 */ 135 int genwqe_read_app_id(struct genwqe_dev *cd, char *app_name, int len) 136 { 137 int i, j; 138 u32 app_id = (u32)cd->app_unitcfg; 139 140 memset(app_name, 0, len); 141 for (i = 0, j = 0; j < min(len, 4); j++) { 142 char ch = (char)((app_id >> (24 - j*8)) & 0xff); 143 144 if (ch == ' ') 145 continue; 146 app_name[i++] = isprint(ch) ? ch : 'X'; 147 } 148 return i; 149 } 150 151 /** 152 * genwqe_init_crc32() - Prepare a lookup table for fast crc32 calculations 153 * 154 * Existing kernel functions seem to use a different polynom, 155 * therefore we could not use them here. 156 * 157 * Genwqe's Polynomial = 0x20044009 158 */ 159 #define CRC32_POLYNOMIAL 0x20044009 160 static u32 crc32_tab[256]; /* crc32 lookup table */ 161 162 void genwqe_init_crc32(void) 163 { 164 int i, j; 165 u32 crc; 166 167 for (i = 0; i < 256; i++) { 168 crc = i << 24; 169 for (j = 0; j < 8; j++) { 170 if (crc & 0x80000000) 171 crc = (crc << 1) ^ CRC32_POLYNOMIAL; 172 else 173 crc = (crc << 1); 174 } 175 crc32_tab[i] = crc; 176 } 177 } 178 179 /** 180 * genwqe_crc32() - Generate 32-bit crc as required for DDCBs 181 * @buff: pointer to data buffer 182 * @len: length of data for calculation 183 * @init: initial crc (0xffffffff at start) 184 * 185 * polynomial = x^32 * + x^29 + x^18 + x^14 + x^3 + 1 (0x20044009) 186 187 * Example: 4 bytes 0x01 0x02 0x03 0x04 with init=0xffffffff should 188 * result in a crc32 of 0xf33cb7d3. 189 * 190 * The existing kernel crc functions did not cover this polynom yet. 191 * 192 * Return: crc32 checksum. 193 */ 194 u32 genwqe_crc32(u8 *buff, size_t len, u32 init) 195 { 196 int i; 197 u32 crc; 198 199 crc = init; 200 while (len--) { 201 i = ((crc >> 24) ^ *buff++) & 0xFF; 202 crc = (crc << 8) ^ crc32_tab[i]; 203 } 204 return crc; 205 } 206 207 void *__genwqe_alloc_consistent(struct genwqe_dev *cd, size_t size, 208 dma_addr_t *dma_handle) 209 { 210 if (get_order(size) >= MAX_ORDER) 211 return NULL; 212 213 return dma_alloc_coherent(&cd->pci_dev->dev, size, dma_handle, 214 GFP_KERNEL); 215 } 216 217 void __genwqe_free_consistent(struct genwqe_dev *cd, size_t size, 218 void *vaddr, dma_addr_t dma_handle) 219 { 220 if (vaddr == NULL) 221 return; 222 223 dma_free_coherent(&cd->pci_dev->dev, size, vaddr, dma_handle); 224 } 225 226 static void genwqe_unmap_pages(struct genwqe_dev *cd, dma_addr_t *dma_list, 227 int num_pages) 228 { 229 int i; 230 struct pci_dev *pci_dev = cd->pci_dev; 231 232 for (i = 0; (i < num_pages) && (dma_list[i] != 0x0); i++) { 233 pci_unmap_page(pci_dev, dma_list[i], 234 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 235 dma_list[i] = 0x0; 236 } 237 } 238 239 static int genwqe_map_pages(struct genwqe_dev *cd, 240 struct page **page_list, int num_pages, 241 dma_addr_t *dma_list) 242 { 243 int i; 244 struct pci_dev *pci_dev = cd->pci_dev; 245 246 /* establish DMA mapping for requested pages */ 247 for (i = 0; i < num_pages; i++) { 248 dma_addr_t daddr; 249 250 dma_list[i] = 0x0; 251 daddr = pci_map_page(pci_dev, page_list[i], 252 0, /* map_offs */ 253 PAGE_SIZE, 254 PCI_DMA_BIDIRECTIONAL); /* FIXME rd/rw */ 255 256 if (pci_dma_mapping_error(pci_dev, daddr)) { 257 dev_err(&pci_dev->dev, 258 "[%s] err: no dma addr daddr=%016llx!\n", 259 __func__, (long long)daddr); 260 goto err; 261 } 262 263 dma_list[i] = daddr; 264 } 265 return 0; 266 267 err: 268 genwqe_unmap_pages(cd, dma_list, num_pages); 269 return -EIO; 270 } 271 272 static int genwqe_sgl_size(int num_pages) 273 { 274 int len, num_tlb = num_pages / 7; 275 276 len = sizeof(struct sg_entry) * (num_pages+num_tlb + 1); 277 return roundup(len, PAGE_SIZE); 278 } 279 280 /** 281 * genwqe_alloc_sync_sgl() - Allocate memory for sgl and overlapping pages 282 * 283 * Allocates memory for sgl and overlapping pages. Pages which might 284 * overlap other user-space memory blocks are being cached for DMAs, 285 * such that we do not run into syncronization issues. Data is copied 286 * from user-space into the cached pages. 287 */ 288 int genwqe_alloc_sync_sgl(struct genwqe_dev *cd, struct genwqe_sgl *sgl, 289 void __user *user_addr, size_t user_size, int write) 290 { 291 int ret = -ENOMEM; 292 struct pci_dev *pci_dev = cd->pci_dev; 293 294 sgl->fpage_offs = offset_in_page((unsigned long)user_addr); 295 sgl->fpage_size = min_t(size_t, PAGE_SIZE-sgl->fpage_offs, user_size); 296 sgl->nr_pages = DIV_ROUND_UP(sgl->fpage_offs + user_size, PAGE_SIZE); 297 sgl->lpage_size = (user_size - sgl->fpage_size) % PAGE_SIZE; 298 299 dev_dbg(&pci_dev->dev, "[%s] uaddr=%p usize=%8ld nr_pages=%ld fpage_offs=%lx fpage_size=%ld lpage_size=%ld\n", 300 __func__, user_addr, user_size, sgl->nr_pages, 301 sgl->fpage_offs, sgl->fpage_size, sgl->lpage_size); 302 303 sgl->user_addr = user_addr; 304 sgl->user_size = user_size; 305 sgl->write = write; 306 sgl->sgl_size = genwqe_sgl_size(sgl->nr_pages); 307 308 if (get_order(sgl->sgl_size) > MAX_ORDER) { 309 dev_err(&pci_dev->dev, 310 "[%s] err: too much memory requested!\n", __func__); 311 return ret; 312 } 313 314 sgl->sgl = __genwqe_alloc_consistent(cd, sgl->sgl_size, 315 &sgl->sgl_dma_addr); 316 if (sgl->sgl == NULL) { 317 dev_err(&pci_dev->dev, 318 "[%s] err: no memory available!\n", __func__); 319 return ret; 320 } 321 322 /* Only use buffering on incomplete pages */ 323 if ((sgl->fpage_size != 0) && (sgl->fpage_size != PAGE_SIZE)) { 324 sgl->fpage = __genwqe_alloc_consistent(cd, PAGE_SIZE, 325 &sgl->fpage_dma_addr); 326 if (sgl->fpage == NULL) 327 goto err_out; 328 329 /* Sync with user memory */ 330 if (copy_from_user(sgl->fpage + sgl->fpage_offs, 331 user_addr, sgl->fpage_size)) { 332 ret = -EFAULT; 333 goto err_out; 334 } 335 } 336 if (sgl->lpage_size != 0) { 337 sgl->lpage = __genwqe_alloc_consistent(cd, PAGE_SIZE, 338 &sgl->lpage_dma_addr); 339 if (sgl->lpage == NULL) 340 goto err_out1; 341 342 /* Sync with user memory */ 343 if (copy_from_user(sgl->lpage, user_addr + user_size - 344 sgl->lpage_size, sgl->lpage_size)) { 345 ret = -EFAULT; 346 goto err_out2; 347 } 348 } 349 return 0; 350 351 err_out2: 352 __genwqe_free_consistent(cd, PAGE_SIZE, sgl->lpage, 353 sgl->lpage_dma_addr); 354 sgl->lpage = NULL; 355 sgl->lpage_dma_addr = 0; 356 err_out1: 357 __genwqe_free_consistent(cd, PAGE_SIZE, sgl->fpage, 358 sgl->fpage_dma_addr); 359 sgl->fpage = NULL; 360 sgl->fpage_dma_addr = 0; 361 err_out: 362 __genwqe_free_consistent(cd, sgl->sgl_size, sgl->sgl, 363 sgl->sgl_dma_addr); 364 sgl->sgl = NULL; 365 sgl->sgl_dma_addr = 0; 366 sgl->sgl_size = 0; 367 368 return ret; 369 } 370 371 int genwqe_setup_sgl(struct genwqe_dev *cd, struct genwqe_sgl *sgl, 372 dma_addr_t *dma_list) 373 { 374 int i = 0, j = 0, p; 375 unsigned long dma_offs, map_offs; 376 dma_addr_t prev_daddr = 0; 377 struct sg_entry *s, *last_s = NULL; 378 size_t size = sgl->user_size; 379 380 dma_offs = 128; /* next block if needed/dma_offset */ 381 map_offs = sgl->fpage_offs; /* offset in first page */ 382 383 s = &sgl->sgl[0]; /* first set of 8 entries */ 384 p = 0; /* page */ 385 while (p < sgl->nr_pages) { 386 dma_addr_t daddr; 387 unsigned int size_to_map; 388 389 /* always write the chaining entry, cleanup is done later */ 390 j = 0; 391 s[j].target_addr = cpu_to_be64(sgl->sgl_dma_addr + dma_offs); 392 s[j].len = cpu_to_be32(128); 393 s[j].flags = cpu_to_be32(SG_CHAINED); 394 j++; 395 396 while (j < 8) { 397 /* DMA mapping for requested page, offs, size */ 398 size_to_map = min(size, PAGE_SIZE - map_offs); 399 400 if ((p == 0) && (sgl->fpage != NULL)) { 401 daddr = sgl->fpage_dma_addr + map_offs; 402 403 } else if ((p == sgl->nr_pages - 1) && 404 (sgl->lpage != NULL)) { 405 daddr = sgl->lpage_dma_addr; 406 } else { 407 daddr = dma_list[p] + map_offs; 408 } 409 410 size -= size_to_map; 411 map_offs = 0; 412 413 if (prev_daddr == daddr) { 414 u32 prev_len = be32_to_cpu(last_s->len); 415 416 /* pr_info("daddr combining: " 417 "%016llx/%08x -> %016llx\n", 418 prev_daddr, prev_len, daddr); */ 419 420 last_s->len = cpu_to_be32(prev_len + 421 size_to_map); 422 423 p++; /* process next page */ 424 if (p == sgl->nr_pages) 425 goto fixup; /* nothing to do */ 426 427 prev_daddr = daddr + size_to_map; 428 continue; 429 } 430 431 /* start new entry */ 432 s[j].target_addr = cpu_to_be64(daddr); 433 s[j].len = cpu_to_be32(size_to_map); 434 s[j].flags = cpu_to_be32(SG_DATA); 435 prev_daddr = daddr + size_to_map; 436 last_s = &s[j]; 437 j++; 438 439 p++; /* process next page */ 440 if (p == sgl->nr_pages) 441 goto fixup; /* nothing to do */ 442 } 443 dma_offs += 128; 444 s += 8; /* continue 8 elements further */ 445 } 446 fixup: 447 if (j == 1) { /* combining happened on last entry! */ 448 s -= 8; /* full shift needed on previous sgl block */ 449 j = 7; /* shift all elements */ 450 } 451 452 for (i = 0; i < j; i++) /* move elements 1 up */ 453 s[i] = s[i + 1]; 454 455 s[i].target_addr = cpu_to_be64(0); 456 s[i].len = cpu_to_be32(0); 457 s[i].flags = cpu_to_be32(SG_END_LIST); 458 return 0; 459 } 460 461 /** 462 * genwqe_free_sync_sgl() - Free memory for sgl and overlapping pages 463 * 464 * After the DMA transfer has been completed we free the memory for 465 * the sgl and the cached pages. Data is being transferred from cached 466 * pages into user-space buffers. 467 */ 468 int genwqe_free_sync_sgl(struct genwqe_dev *cd, struct genwqe_sgl *sgl) 469 { 470 int rc = 0; 471 size_t offset; 472 unsigned long res; 473 struct pci_dev *pci_dev = cd->pci_dev; 474 475 if (sgl->fpage) { 476 if (sgl->write) { 477 res = copy_to_user(sgl->user_addr, 478 sgl->fpage + sgl->fpage_offs, sgl->fpage_size); 479 if (res) { 480 dev_err(&pci_dev->dev, 481 "[%s] err: copying fpage! (res=%lu)\n", 482 __func__, res); 483 rc = -EFAULT; 484 } 485 } 486 __genwqe_free_consistent(cd, PAGE_SIZE, sgl->fpage, 487 sgl->fpage_dma_addr); 488 sgl->fpage = NULL; 489 sgl->fpage_dma_addr = 0; 490 } 491 if (sgl->lpage) { 492 if (sgl->write) { 493 offset = sgl->user_size - sgl->lpage_size; 494 res = copy_to_user(sgl->user_addr + offset, sgl->lpage, 495 sgl->lpage_size); 496 if (res) { 497 dev_err(&pci_dev->dev, 498 "[%s] err: copying lpage! (res=%lu)\n", 499 __func__, res); 500 rc = -EFAULT; 501 } 502 } 503 __genwqe_free_consistent(cd, PAGE_SIZE, sgl->lpage, 504 sgl->lpage_dma_addr); 505 sgl->lpage = NULL; 506 sgl->lpage_dma_addr = 0; 507 } 508 __genwqe_free_consistent(cd, sgl->sgl_size, sgl->sgl, 509 sgl->sgl_dma_addr); 510 511 sgl->sgl = NULL; 512 sgl->sgl_dma_addr = 0x0; 513 sgl->sgl_size = 0; 514 return rc; 515 } 516 517 /** 518 * genwqe_free_user_pages() - Give pinned pages back 519 * 520 * Documentation of get_user_pages is in mm/gup.c: 521 * 522 * If the page is written to, set_page_dirty (or set_page_dirty_lock, 523 * as appropriate) must be called after the page is finished with, and 524 * before put_page is called. 525 */ 526 static int genwqe_free_user_pages(struct page **page_list, 527 unsigned int nr_pages, int dirty) 528 { 529 unsigned int i; 530 531 for (i = 0; i < nr_pages; i++) { 532 if (page_list[i] != NULL) { 533 if (dirty) 534 set_page_dirty_lock(page_list[i]); 535 put_page(page_list[i]); 536 } 537 } 538 return 0; 539 } 540 541 /** 542 * genwqe_user_vmap() - Map user-space memory to virtual kernel memory 543 * @cd: pointer to genwqe device 544 * @m: mapping params 545 * @uaddr: user virtual address 546 * @size: size of memory to be mapped 547 * 548 * We need to think about how we could speed this up. Of course it is 549 * not a good idea to do this over and over again, like we are 550 * currently doing it. Nevertheless, I am curious where on the path 551 * the performance is spend. Most probably within the memory 552 * allocation functions, but maybe also in the DMA mapping code. 553 * 554 * Restrictions: The maximum size of the possible mapping currently depends 555 * on the amount of memory we can get using kzalloc() for the 556 * page_list and pci_alloc_consistent for the sg_list. 557 * The sg_list is currently itself not scattered, which could 558 * be fixed with some effort. The page_list must be split into 559 * PAGE_SIZE chunks too. All that will make the complicated 560 * code more complicated. 561 * 562 * Return: 0 if success 563 */ 564 int genwqe_user_vmap(struct genwqe_dev *cd, struct dma_mapping *m, void *uaddr, 565 unsigned long size) 566 { 567 int rc = -EINVAL; 568 unsigned long data, offs; 569 struct pci_dev *pci_dev = cd->pci_dev; 570 571 if ((uaddr == NULL) || (size == 0)) { 572 m->size = 0; /* mark unused and not added */ 573 return -EINVAL; 574 } 575 m->u_vaddr = uaddr; 576 m->size = size; 577 578 /* determine space needed for page_list. */ 579 data = (unsigned long)uaddr; 580 offs = offset_in_page(data); 581 m->nr_pages = DIV_ROUND_UP(offs + size, PAGE_SIZE); 582 583 m->page_list = kcalloc(m->nr_pages, 584 sizeof(struct page *) + sizeof(dma_addr_t), 585 GFP_KERNEL); 586 if (!m->page_list) { 587 dev_err(&pci_dev->dev, "err: alloc page_list failed\n"); 588 m->nr_pages = 0; 589 m->u_vaddr = NULL; 590 m->size = 0; /* mark unused and not added */ 591 return -ENOMEM; 592 } 593 m->dma_list = (dma_addr_t *)(m->page_list + m->nr_pages); 594 595 /* pin user pages in memory */ 596 rc = get_user_pages_fast(data & PAGE_MASK, /* page aligned addr */ 597 m->nr_pages, 598 m->write ? FOLL_WRITE : 0, /* readable/writable */ 599 m->page_list); /* ptrs to pages */ 600 if (rc < 0) 601 goto fail_get_user_pages; 602 603 /* assumption: get_user_pages can be killed by signals. */ 604 if (rc < m->nr_pages) { 605 genwqe_free_user_pages(m->page_list, rc, m->write); 606 rc = -EFAULT; 607 goto fail_get_user_pages; 608 } 609 610 rc = genwqe_map_pages(cd, m->page_list, m->nr_pages, m->dma_list); 611 if (rc != 0) 612 goto fail_free_user_pages; 613 614 return 0; 615 616 fail_free_user_pages: 617 genwqe_free_user_pages(m->page_list, m->nr_pages, m->write); 618 619 fail_get_user_pages: 620 kfree(m->page_list); 621 m->page_list = NULL; 622 m->dma_list = NULL; 623 m->nr_pages = 0; 624 m->u_vaddr = NULL; 625 m->size = 0; /* mark unused and not added */ 626 return rc; 627 } 628 629 /** 630 * genwqe_user_vunmap() - Undo mapping of user-space mem to virtual kernel 631 * memory 632 * @cd: pointer to genwqe device 633 * @m: mapping params 634 */ 635 int genwqe_user_vunmap(struct genwqe_dev *cd, struct dma_mapping *m) 636 { 637 struct pci_dev *pci_dev = cd->pci_dev; 638 639 if (!dma_mapping_used(m)) { 640 dev_err(&pci_dev->dev, "[%s] err: mapping %p not used!\n", 641 __func__, m); 642 return -EINVAL; 643 } 644 645 if (m->dma_list) 646 genwqe_unmap_pages(cd, m->dma_list, m->nr_pages); 647 648 if (m->page_list) { 649 genwqe_free_user_pages(m->page_list, m->nr_pages, m->write); 650 651 kfree(m->page_list); 652 m->page_list = NULL; 653 m->dma_list = NULL; 654 m->nr_pages = 0; 655 } 656 657 m->u_vaddr = NULL; 658 m->size = 0; /* mark as unused and not added */ 659 return 0; 660 } 661 662 /** 663 * genwqe_card_type() - Get chip type SLU Configuration Register 664 * @cd: pointer to the genwqe device descriptor 665 * Return: 0: Altera Stratix-IV 230 666 * 1: Altera Stratix-IV 530 667 * 2: Altera Stratix-V A4 668 * 3: Altera Stratix-V A7 669 */ 670 u8 genwqe_card_type(struct genwqe_dev *cd) 671 { 672 u64 card_type = cd->slu_unitcfg; 673 674 return (u8)((card_type & IO_SLU_UNITCFG_TYPE_MASK) >> 20); 675 } 676 677 /** 678 * genwqe_card_reset() - Reset the card 679 * @cd: pointer to the genwqe device descriptor 680 */ 681 int genwqe_card_reset(struct genwqe_dev *cd) 682 { 683 u64 softrst; 684 struct pci_dev *pci_dev = cd->pci_dev; 685 686 if (!genwqe_is_privileged(cd)) 687 return -ENODEV; 688 689 /* new SL */ 690 __genwqe_writeq(cd, IO_SLC_CFGREG_SOFTRESET, 0x1ull); 691 msleep(1000); 692 __genwqe_readq(cd, IO_HSU_FIR_CLR); 693 __genwqe_readq(cd, IO_APP_FIR_CLR); 694 __genwqe_readq(cd, IO_SLU_FIR_CLR); 695 696 /* 697 * Read-modify-write to preserve the stealth bits 698 * 699 * For SL >= 039, Stealth WE bit allows removing 700 * the read-modify-wrote. 701 * r-m-w may require a mask 0x3C to avoid hitting hard 702 * reset again for error reset (should be 0, chicken). 703 */ 704 softrst = __genwqe_readq(cd, IO_SLC_CFGREG_SOFTRESET) & 0x3cull; 705 __genwqe_writeq(cd, IO_SLC_CFGREG_SOFTRESET, softrst | 0x2ull); 706 707 /* give ERRORRESET some time to finish */ 708 msleep(50); 709 710 if (genwqe_need_err_masking(cd)) { 711 dev_info(&pci_dev->dev, 712 "[%s] masking errors for old bitstreams\n", __func__); 713 __genwqe_writeq(cd, IO_SLC_MISC_DEBUG, 0x0aull); 714 } 715 return 0; 716 } 717 718 int genwqe_read_softreset(struct genwqe_dev *cd) 719 { 720 u64 bitstream; 721 722 if (!genwqe_is_privileged(cd)) 723 return -ENODEV; 724 725 bitstream = __genwqe_readq(cd, IO_SLU_BITSTREAM) & 0x1; 726 cd->softreset = (bitstream == 0) ? 0x8ull : 0xcull; 727 return 0; 728 } 729 730 /** 731 * genwqe_set_interrupt_capability() - Configure MSI capability structure 732 * @cd: pointer to the device 733 * Return: 0 if no error 734 */ 735 int genwqe_set_interrupt_capability(struct genwqe_dev *cd, int count) 736 { 737 int rc; 738 739 rc = pci_alloc_irq_vectors(cd->pci_dev, 1, count, PCI_IRQ_MSI); 740 if (rc < 0) 741 return rc; 742 return 0; 743 } 744 745 /** 746 * genwqe_reset_interrupt_capability() - Undo genwqe_set_interrupt_capability() 747 * @cd: pointer to the device 748 */ 749 void genwqe_reset_interrupt_capability(struct genwqe_dev *cd) 750 { 751 pci_free_irq_vectors(cd->pci_dev); 752 } 753 754 /** 755 * set_reg_idx() - Fill array with data. Ignore illegal offsets. 756 * @cd: card device 757 * @r: debug register array 758 * @i: index to desired entry 759 * @m: maximum possible entries 760 * @addr: addr which is read 761 * @index: index in debug array 762 * @val: read value 763 */ 764 static int set_reg_idx(struct genwqe_dev *cd, struct genwqe_reg *r, 765 unsigned int *i, unsigned int m, u32 addr, u32 idx, 766 u64 val) 767 { 768 if (WARN_ON_ONCE(*i >= m)) 769 return -EFAULT; 770 771 r[*i].addr = addr; 772 r[*i].idx = idx; 773 r[*i].val = val; 774 ++*i; 775 return 0; 776 } 777 778 static int set_reg(struct genwqe_dev *cd, struct genwqe_reg *r, 779 unsigned int *i, unsigned int m, u32 addr, u64 val) 780 { 781 return set_reg_idx(cd, r, i, m, addr, 0, val); 782 } 783 784 int genwqe_read_ffdc_regs(struct genwqe_dev *cd, struct genwqe_reg *regs, 785 unsigned int max_regs, int all) 786 { 787 unsigned int i, j, idx = 0; 788 u32 ufir_addr, ufec_addr, sfir_addr, sfec_addr; 789 u64 gfir, sluid, appid, ufir, ufec, sfir, sfec; 790 791 /* Global FIR */ 792 gfir = __genwqe_readq(cd, IO_SLC_CFGREG_GFIR); 793 set_reg(cd, regs, &idx, max_regs, IO_SLC_CFGREG_GFIR, gfir); 794 795 /* UnitCfg for SLU */ 796 sluid = __genwqe_readq(cd, IO_SLU_UNITCFG); /* 0x00000000 */ 797 set_reg(cd, regs, &idx, max_regs, IO_SLU_UNITCFG, sluid); 798 799 /* UnitCfg for APP */ 800 appid = __genwqe_readq(cd, IO_APP_UNITCFG); /* 0x02000000 */ 801 set_reg(cd, regs, &idx, max_regs, IO_APP_UNITCFG, appid); 802 803 /* Check all chip Units */ 804 for (i = 0; i < GENWQE_MAX_UNITS; i++) { 805 806 /* Unit FIR */ 807 ufir_addr = (i << 24) | 0x008; 808 ufir = __genwqe_readq(cd, ufir_addr); 809 set_reg(cd, regs, &idx, max_regs, ufir_addr, ufir); 810 811 /* Unit FEC */ 812 ufec_addr = (i << 24) | 0x018; 813 ufec = __genwqe_readq(cd, ufec_addr); 814 set_reg(cd, regs, &idx, max_regs, ufec_addr, ufec); 815 816 for (j = 0; j < 64; j++) { 817 /* wherever there is a primary 1, read the 2ndary */ 818 if (!all && (!(ufir & (1ull << j)))) 819 continue; 820 821 sfir_addr = (i << 24) | (0x100 + 8 * j); 822 sfir = __genwqe_readq(cd, sfir_addr); 823 set_reg(cd, regs, &idx, max_regs, sfir_addr, sfir); 824 825 sfec_addr = (i << 24) | (0x300 + 8 * j); 826 sfec = __genwqe_readq(cd, sfec_addr); 827 set_reg(cd, regs, &idx, max_regs, sfec_addr, sfec); 828 } 829 } 830 831 /* fill with invalid data until end */ 832 for (i = idx; i < max_regs; i++) { 833 regs[i].addr = 0xffffffff; 834 regs[i].val = 0xffffffffffffffffull; 835 } 836 return idx; 837 } 838 839 /** 840 * genwqe_ffdc_buff_size() - Calculates the number of dump registers 841 */ 842 int genwqe_ffdc_buff_size(struct genwqe_dev *cd, int uid) 843 { 844 int entries = 0, ring, traps, traces, trace_entries; 845 u32 eevptr_addr, l_addr, d_len, d_type; 846 u64 eevptr, val, addr; 847 848 eevptr_addr = GENWQE_UID_OFFS(uid) | IO_EXTENDED_ERROR_POINTER; 849 eevptr = __genwqe_readq(cd, eevptr_addr); 850 851 if ((eevptr != 0x0) && (eevptr != -1ull)) { 852 l_addr = GENWQE_UID_OFFS(uid) | eevptr; 853 854 while (1) { 855 val = __genwqe_readq(cd, l_addr); 856 857 if ((val == 0x0) || (val == -1ull)) 858 break; 859 860 /* 38:24 */ 861 d_len = (val & 0x0000007fff000000ull) >> 24; 862 863 /* 39 */ 864 d_type = (val & 0x0000008000000000ull) >> 36; 865 866 if (d_type) { /* repeat */ 867 entries += d_len; 868 } else { /* size in bytes! */ 869 entries += d_len >> 3; 870 } 871 872 l_addr += 8; 873 } 874 } 875 876 for (ring = 0; ring < 8; ring++) { 877 addr = GENWQE_UID_OFFS(uid) | IO_EXTENDED_DIAG_MAP(ring); 878 val = __genwqe_readq(cd, addr); 879 880 if ((val == 0x0ull) || (val == -1ull)) 881 continue; 882 883 traps = (val >> 24) & 0xff; 884 traces = (val >> 16) & 0xff; 885 trace_entries = val & 0xffff; 886 887 entries += traps + (traces * trace_entries); 888 } 889 return entries; 890 } 891 892 /** 893 * genwqe_ffdc_buff_read() - Implements LogoutExtendedErrorRegisters procedure 894 */ 895 int genwqe_ffdc_buff_read(struct genwqe_dev *cd, int uid, 896 struct genwqe_reg *regs, unsigned int max_regs) 897 { 898 int i, traps, traces, trace, trace_entries, trace_entry, ring; 899 unsigned int idx = 0; 900 u32 eevptr_addr, l_addr, d_addr, d_len, d_type; 901 u64 eevptr, e, val, addr; 902 903 eevptr_addr = GENWQE_UID_OFFS(uid) | IO_EXTENDED_ERROR_POINTER; 904 eevptr = __genwqe_readq(cd, eevptr_addr); 905 906 if ((eevptr != 0x0) && (eevptr != 0xffffffffffffffffull)) { 907 l_addr = GENWQE_UID_OFFS(uid) | eevptr; 908 while (1) { 909 e = __genwqe_readq(cd, l_addr); 910 if ((e == 0x0) || (e == 0xffffffffffffffffull)) 911 break; 912 913 d_addr = (e & 0x0000000000ffffffull); /* 23:0 */ 914 d_len = (e & 0x0000007fff000000ull) >> 24; /* 38:24 */ 915 d_type = (e & 0x0000008000000000ull) >> 36; /* 39 */ 916 d_addr |= GENWQE_UID_OFFS(uid); 917 918 if (d_type) { 919 for (i = 0; i < (int)d_len; i++) { 920 val = __genwqe_readq(cd, d_addr); 921 set_reg_idx(cd, regs, &idx, max_regs, 922 d_addr, i, val); 923 } 924 } else { 925 d_len >>= 3; /* Size in bytes! */ 926 for (i = 0; i < (int)d_len; i++, d_addr += 8) { 927 val = __genwqe_readq(cd, d_addr); 928 set_reg_idx(cd, regs, &idx, max_regs, 929 d_addr, 0, val); 930 } 931 } 932 l_addr += 8; 933 } 934 } 935 936 /* 937 * To save time, there are only 6 traces poplulated on Uid=2, 938 * Ring=1. each with iters=512. 939 */ 940 for (ring = 0; ring < 8; ring++) { /* 0 is fls, 1 is fds, 941 2...7 are ASI rings */ 942 addr = GENWQE_UID_OFFS(uid) | IO_EXTENDED_DIAG_MAP(ring); 943 val = __genwqe_readq(cd, addr); 944 945 if ((val == 0x0ull) || (val == -1ull)) 946 continue; 947 948 traps = (val >> 24) & 0xff; /* Number of Traps */ 949 traces = (val >> 16) & 0xff; /* Number of Traces */ 950 trace_entries = val & 0xffff; /* Entries per trace */ 951 952 /* Note: This is a combined loop that dumps both the traps */ 953 /* (for the trace == 0 case) as well as the traces 1 to */ 954 /* 'traces'. */ 955 for (trace = 0; trace <= traces; trace++) { 956 u32 diag_sel = 957 GENWQE_EXTENDED_DIAG_SELECTOR(ring, trace); 958 959 addr = (GENWQE_UID_OFFS(uid) | 960 IO_EXTENDED_DIAG_SELECTOR); 961 __genwqe_writeq(cd, addr, diag_sel); 962 963 for (trace_entry = 0; 964 trace_entry < (trace ? trace_entries : traps); 965 trace_entry++) { 966 addr = (GENWQE_UID_OFFS(uid) | 967 IO_EXTENDED_DIAG_READ_MBX); 968 val = __genwqe_readq(cd, addr); 969 set_reg_idx(cd, regs, &idx, max_regs, addr, 970 (diag_sel<<16) | trace_entry, val); 971 } 972 } 973 } 974 return 0; 975 } 976 977 /** 978 * genwqe_write_vreg() - Write register in virtual window 979 * 980 * Note, these registers are only accessible to the PF through the 981 * VF-window. It is not intended for the VF to access. 982 */ 983 int genwqe_write_vreg(struct genwqe_dev *cd, u32 reg, u64 val, int func) 984 { 985 __genwqe_writeq(cd, IO_PF_SLC_VIRTUAL_WINDOW, func & 0xf); 986 __genwqe_writeq(cd, reg, val); 987 return 0; 988 } 989 990 /** 991 * genwqe_read_vreg() - Read register in virtual window 992 * 993 * Note, these registers are only accessible to the PF through the 994 * VF-window. It is not intended for the VF to access. 995 */ 996 u64 genwqe_read_vreg(struct genwqe_dev *cd, u32 reg, int func) 997 { 998 __genwqe_writeq(cd, IO_PF_SLC_VIRTUAL_WINDOW, func & 0xf); 999 return __genwqe_readq(cd, reg); 1000 } 1001 1002 /** 1003 * genwqe_base_clock_frequency() - Deteremine base clock frequency of the card 1004 * 1005 * Note: From a design perspective it turned out to be a bad idea to 1006 * use codes here to specifiy the frequency/speed values. An old 1007 * driver cannot understand new codes and is therefore always a 1008 * problem. Better is to measure out the value or put the 1009 * speed/frequency directly into a register which is always a valid 1010 * value for old as well as for new software. 1011 * 1012 * Return: Card clock in MHz 1013 */ 1014 int genwqe_base_clock_frequency(struct genwqe_dev *cd) 1015 { 1016 u16 speed; /* MHz MHz MHz MHz */ 1017 static const int speed_grade[] = { 250, 200, 166, 175 }; 1018 1019 speed = (u16)((cd->slu_unitcfg >> 28) & 0x0full); 1020 if (speed >= ARRAY_SIZE(speed_grade)) 1021 return 0; /* illegal value */ 1022 1023 return speed_grade[speed]; 1024 } 1025 1026 /** 1027 * genwqe_stop_traps() - Stop traps 1028 * 1029 * Before reading out the analysis data, we need to stop the traps. 1030 */ 1031 void genwqe_stop_traps(struct genwqe_dev *cd) 1032 { 1033 __genwqe_writeq(cd, IO_SLC_MISC_DEBUG_SET, 0xcull); 1034 } 1035 1036 /** 1037 * genwqe_start_traps() - Start traps 1038 * 1039 * After having read the data, we can/must enable the traps again. 1040 */ 1041 void genwqe_start_traps(struct genwqe_dev *cd) 1042 { 1043 __genwqe_writeq(cd, IO_SLC_MISC_DEBUG_CLR, 0xcull); 1044 1045 if (genwqe_need_err_masking(cd)) 1046 __genwqe_writeq(cd, IO_SLC_MISC_DEBUG, 0x0aull); 1047 } 1048