1 /** 2 * IBM Accelerator Family 'GenWQE' 3 * 4 * (C) Copyright IBM Corp. 2013 5 * 6 * Author: Frank Haverkamp <haver@linux.vnet.ibm.com> 7 * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com> 8 * Author: Michael Jung <mijung@de.ibm.com> 9 * Author: Michael Ruettger <michael@ibmra.de> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License (version 2 only) 13 * as published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 */ 20 21 /* 22 * Miscelanous functionality used in the other GenWQE driver parts. 23 */ 24 25 #include <linux/kernel.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/sched.h> 28 #include <linux/vmalloc.h> 29 #include <linux/page-flags.h> 30 #include <linux/scatterlist.h> 31 #include <linux/hugetlb.h> 32 #include <linux/iommu.h> 33 #include <linux/delay.h> 34 #include <linux/pci.h> 35 #include <linux/dma-mapping.h> 36 #include <linux/ctype.h> 37 #include <linux/module.h> 38 #include <linux/platform_device.h> 39 #include <linux/delay.h> 40 #include <asm/pgtable.h> 41 42 #include "genwqe_driver.h" 43 #include "card_base.h" 44 #include "card_ddcb.h" 45 46 /** 47 * __genwqe_writeq() - Write 64-bit register 48 * @cd: genwqe device descriptor 49 * @byte_offs: byte offset within BAR 50 * @val: 64-bit value 51 * 52 * Return: 0 if success; < 0 if error 53 */ 54 int __genwqe_writeq(struct genwqe_dev *cd, u64 byte_offs, u64 val) 55 { 56 if (cd->err_inject & GENWQE_INJECT_HARDWARE_FAILURE) 57 return -EIO; 58 59 if (cd->mmio == NULL) 60 return -EIO; 61 62 __raw_writeq((__force u64)cpu_to_be64(val), cd->mmio + byte_offs); 63 return 0; 64 } 65 66 /** 67 * __genwqe_readq() - Read 64-bit register 68 * @cd: genwqe device descriptor 69 * @byte_offs: offset within BAR 70 * 71 * Return: value from register 72 */ 73 u64 __genwqe_readq(struct genwqe_dev *cd, u64 byte_offs) 74 { 75 if (cd->err_inject & GENWQE_INJECT_HARDWARE_FAILURE) 76 return 0xffffffffffffffffull; 77 78 if ((cd->err_inject & GENWQE_INJECT_GFIR_FATAL) && 79 (byte_offs == IO_SLC_CFGREG_GFIR)) 80 return 0x000000000000ffffull; 81 82 if ((cd->err_inject & GENWQE_INJECT_GFIR_INFO) && 83 (byte_offs == IO_SLC_CFGREG_GFIR)) 84 return 0x00000000ffff0000ull; 85 86 if (cd->mmio == NULL) 87 return 0xffffffffffffffffull; 88 89 return be64_to_cpu((__force __be64)__raw_readq(cd->mmio + byte_offs)); 90 } 91 92 /** 93 * __genwqe_writel() - Write 32-bit register 94 * @cd: genwqe device descriptor 95 * @byte_offs: byte offset within BAR 96 * @val: 32-bit value 97 * 98 * Return: 0 if success; < 0 if error 99 */ 100 int __genwqe_writel(struct genwqe_dev *cd, u64 byte_offs, u32 val) 101 { 102 if (cd->err_inject & GENWQE_INJECT_HARDWARE_FAILURE) 103 return -EIO; 104 105 if (cd->mmio == NULL) 106 return -EIO; 107 108 __raw_writel((__force u32)cpu_to_be32(val), cd->mmio + byte_offs); 109 return 0; 110 } 111 112 /** 113 * __genwqe_readl() - Read 32-bit register 114 * @cd: genwqe device descriptor 115 * @byte_offs: offset within BAR 116 * 117 * Return: Value from register 118 */ 119 u32 __genwqe_readl(struct genwqe_dev *cd, u64 byte_offs) 120 { 121 if (cd->err_inject & GENWQE_INJECT_HARDWARE_FAILURE) 122 return 0xffffffff; 123 124 if (cd->mmio == NULL) 125 return 0xffffffff; 126 127 return be32_to_cpu((__force __be32)__raw_readl(cd->mmio + byte_offs)); 128 } 129 130 /** 131 * genwqe_read_app_id() - Extract app_id 132 * 133 * app_unitcfg need to be filled with valid data first 134 */ 135 int genwqe_read_app_id(struct genwqe_dev *cd, char *app_name, int len) 136 { 137 int i, j; 138 u32 app_id = (u32)cd->app_unitcfg; 139 140 memset(app_name, 0, len); 141 for (i = 0, j = 0; j < min(len, 4); j++) { 142 char ch = (char)((app_id >> (24 - j*8)) & 0xff); 143 if (ch == ' ') 144 continue; 145 app_name[i++] = isprint(ch) ? ch : 'X'; 146 } 147 return i; 148 } 149 150 /** 151 * genwqe_init_crc32() - Prepare a lookup table for fast crc32 calculations 152 * 153 * Existing kernel functions seem to use a different polynom, 154 * therefore we could not use them here. 155 * 156 * Genwqe's Polynomial = 0x20044009 157 */ 158 #define CRC32_POLYNOMIAL 0x20044009 159 static u32 crc32_tab[256]; /* crc32 lookup table */ 160 161 void genwqe_init_crc32(void) 162 { 163 int i, j; 164 u32 crc; 165 166 for (i = 0; i < 256; i++) { 167 crc = i << 24; 168 for (j = 0; j < 8; j++) { 169 if (crc & 0x80000000) 170 crc = (crc << 1) ^ CRC32_POLYNOMIAL; 171 else 172 crc = (crc << 1); 173 } 174 crc32_tab[i] = crc; 175 } 176 } 177 178 /** 179 * genwqe_crc32() - Generate 32-bit crc as required for DDCBs 180 * @buff: pointer to data buffer 181 * @len: length of data for calculation 182 * @init: initial crc (0xffffffff at start) 183 * 184 * polynomial = x^32 * + x^29 + x^18 + x^14 + x^3 + 1 (0x20044009) 185 186 * Example: 4 bytes 0x01 0x02 0x03 0x04 with init=0xffffffff should 187 * result in a crc32 of 0xf33cb7d3. 188 * 189 * The existing kernel crc functions did not cover this polynom yet. 190 * 191 * Return: crc32 checksum. 192 */ 193 u32 genwqe_crc32(u8 *buff, size_t len, u32 init) 194 { 195 int i; 196 u32 crc; 197 198 crc = init; 199 while (len--) { 200 i = ((crc >> 24) ^ *buff++) & 0xFF; 201 crc = (crc << 8) ^ crc32_tab[i]; 202 } 203 return crc; 204 } 205 206 void *__genwqe_alloc_consistent(struct genwqe_dev *cd, size_t size, 207 dma_addr_t *dma_handle) 208 { 209 if (get_order(size) > MAX_ORDER) 210 return NULL; 211 212 return pci_alloc_consistent(cd->pci_dev, size, dma_handle); 213 } 214 215 void __genwqe_free_consistent(struct genwqe_dev *cd, size_t size, 216 void *vaddr, dma_addr_t dma_handle) 217 { 218 if (vaddr == NULL) 219 return; 220 221 pci_free_consistent(cd->pci_dev, size, vaddr, dma_handle); 222 } 223 224 static void genwqe_unmap_pages(struct genwqe_dev *cd, dma_addr_t *dma_list, 225 int num_pages) 226 { 227 int i; 228 struct pci_dev *pci_dev = cd->pci_dev; 229 230 for (i = 0; (i < num_pages) && (dma_list[i] != 0x0); i++) { 231 pci_unmap_page(pci_dev, dma_list[i], 232 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 233 dma_list[i] = 0x0; 234 } 235 } 236 237 static int genwqe_map_pages(struct genwqe_dev *cd, 238 struct page **page_list, int num_pages, 239 dma_addr_t *dma_list) 240 { 241 int i; 242 struct pci_dev *pci_dev = cd->pci_dev; 243 244 /* establish DMA mapping for requested pages */ 245 for (i = 0; i < num_pages; i++) { 246 dma_addr_t daddr; 247 248 dma_list[i] = 0x0; 249 daddr = pci_map_page(pci_dev, page_list[i], 250 0, /* map_offs */ 251 PAGE_SIZE, 252 PCI_DMA_BIDIRECTIONAL); /* FIXME rd/rw */ 253 254 if (pci_dma_mapping_error(pci_dev, daddr)) { 255 dev_err(&pci_dev->dev, 256 "[%s] err: no dma addr daddr=%016llx!\n", 257 __func__, (long long)daddr); 258 goto err; 259 } 260 261 dma_list[i] = daddr; 262 } 263 return 0; 264 265 err: 266 genwqe_unmap_pages(cd, dma_list, num_pages); 267 return -EIO; 268 } 269 270 static int genwqe_sgl_size(int num_pages) 271 { 272 int len, num_tlb = num_pages / 7; 273 274 len = sizeof(struct sg_entry) * (num_pages+num_tlb + 1); 275 return roundup(len, PAGE_SIZE); 276 } 277 278 struct sg_entry *genwqe_alloc_sgl(struct genwqe_dev *cd, int num_pages, 279 dma_addr_t *dma_addr, size_t *sgl_size) 280 { 281 struct pci_dev *pci_dev = cd->pci_dev; 282 struct sg_entry *sgl; 283 284 *sgl_size = genwqe_sgl_size(num_pages); 285 if (get_order(*sgl_size) > MAX_ORDER) { 286 dev_err(&pci_dev->dev, 287 "[%s] err: too much memory requested!\n", __func__); 288 return NULL; 289 } 290 291 sgl = __genwqe_alloc_consistent(cd, *sgl_size, dma_addr); 292 if (sgl == NULL) { 293 dev_err(&pci_dev->dev, 294 "[%s] err: no memory available!\n", __func__); 295 return NULL; 296 } 297 298 return sgl; 299 } 300 301 int genwqe_setup_sgl(struct genwqe_dev *cd, 302 unsigned long offs, 303 unsigned long size, 304 struct sg_entry *sgl, 305 dma_addr_t dma_addr, size_t sgl_size, 306 dma_addr_t *dma_list, int page_offs, int num_pages) 307 { 308 int i = 0, j = 0, p; 309 unsigned long dma_offs, map_offs; 310 struct pci_dev *pci_dev = cd->pci_dev; 311 dma_addr_t prev_daddr = 0; 312 struct sg_entry *s, *last_s = NULL; 313 314 /* sanity checks */ 315 if (offs > PAGE_SIZE) { 316 dev_err(&pci_dev->dev, 317 "[%s] too large start offs %08lx\n", __func__, offs); 318 return -EFAULT; 319 } 320 if (sgl_size < genwqe_sgl_size(num_pages)) { 321 dev_err(&pci_dev->dev, 322 "[%s] sgl_size too small %08lx for %d pages\n", 323 __func__, sgl_size, num_pages); 324 return -EFAULT; 325 } 326 327 dma_offs = 128; /* next block if needed/dma_offset */ 328 map_offs = offs; /* offset in first page */ 329 330 s = &sgl[0]; /* first set of 8 entries */ 331 p = 0; /* page */ 332 while (p < num_pages) { 333 dma_addr_t daddr; 334 unsigned int size_to_map; 335 336 /* always write the chaining entry, cleanup is done later */ 337 j = 0; 338 s[j].target_addr = cpu_to_be64(dma_addr + dma_offs); 339 s[j].len = cpu_to_be32(128); 340 s[j].flags = cpu_to_be32(SG_CHAINED); 341 j++; 342 343 while (j < 8) { 344 /* DMA mapping for requested page, offs, size */ 345 size_to_map = min(size, PAGE_SIZE - map_offs); 346 daddr = dma_list[page_offs + p] + map_offs; 347 size -= size_to_map; 348 map_offs = 0; 349 350 if (prev_daddr == daddr) { 351 u32 prev_len = be32_to_cpu(last_s->len); 352 353 /* pr_info("daddr combining: " 354 "%016llx/%08x -> %016llx\n", 355 prev_daddr, prev_len, daddr); */ 356 357 last_s->len = cpu_to_be32(prev_len + 358 size_to_map); 359 360 p++; /* process next page */ 361 if (p == num_pages) 362 goto fixup; /* nothing to do */ 363 364 prev_daddr = daddr + size_to_map; 365 continue; 366 } 367 368 /* start new entry */ 369 s[j].target_addr = cpu_to_be64(daddr); 370 s[j].len = cpu_to_be32(size_to_map); 371 s[j].flags = cpu_to_be32(SG_DATA); 372 prev_daddr = daddr + size_to_map; 373 last_s = &s[j]; 374 j++; 375 376 p++; /* process next page */ 377 if (p == num_pages) 378 goto fixup; /* nothing to do */ 379 } 380 dma_offs += 128; 381 s += 8; /* continue 8 elements further */ 382 } 383 fixup: 384 if (j == 1) { /* combining happend on last entry! */ 385 s -= 8; /* full shift needed on previous sgl block */ 386 j = 7; /* shift all elements */ 387 } 388 389 for (i = 0; i < j; i++) /* move elements 1 up */ 390 s[i] = s[i + 1]; 391 392 s[i].target_addr = cpu_to_be64(0); 393 s[i].len = cpu_to_be32(0); 394 s[i].flags = cpu_to_be32(SG_END_LIST); 395 return 0; 396 } 397 398 void genwqe_free_sgl(struct genwqe_dev *cd, struct sg_entry *sg_list, 399 dma_addr_t dma_addr, size_t size) 400 { 401 __genwqe_free_consistent(cd, size, sg_list, dma_addr); 402 } 403 404 /** 405 * free_user_pages() - Give pinned pages back 406 * 407 * Documentation of get_user_pages is in mm/memory.c: 408 * 409 * If the page is written to, set_page_dirty (or set_page_dirty_lock, 410 * as appropriate) must be called after the page is finished with, and 411 * before put_page is called. 412 * 413 * FIXME Could be of use to others and might belong in the generic 414 * code, if others agree. E.g. 415 * ll_free_user_pages in drivers/staging/lustre/lustre/llite/rw26.c 416 * ceph_put_page_vector in net/ceph/pagevec.c 417 * maybe more? 418 */ 419 static int free_user_pages(struct page **page_list, unsigned int nr_pages, 420 int dirty) 421 { 422 unsigned int i; 423 424 for (i = 0; i < nr_pages; i++) { 425 if (page_list[i] != NULL) { 426 if (dirty) 427 set_page_dirty_lock(page_list[i]); 428 put_page(page_list[i]); 429 } 430 } 431 return 0; 432 } 433 434 /** 435 * genwqe_user_vmap() - Map user-space memory to virtual kernel memory 436 * @cd: pointer to genwqe device 437 * @m: mapping params 438 * @uaddr: user virtual address 439 * @size: size of memory to be mapped 440 * 441 * We need to think about how we could speed this up. Of course it is 442 * not a good idea to do this over and over again, like we are 443 * currently doing it. Nevertheless, I am curious where on the path 444 * the performance is spend. Most probably within the memory 445 * allocation functions, but maybe also in the DMA mapping code. 446 * 447 * Restrictions: The maximum size of the possible mapping currently depends 448 * on the amount of memory we can get using kzalloc() for the 449 * page_list and pci_alloc_consistent for the sg_list. 450 * The sg_list is currently itself not scattered, which could 451 * be fixed with some effort. The page_list must be split into 452 * PAGE_SIZE chunks too. All that will make the complicated 453 * code more complicated. 454 * 455 * Return: 0 if success 456 */ 457 int genwqe_user_vmap(struct genwqe_dev *cd, struct dma_mapping *m, void *uaddr, 458 unsigned long size, struct ddcb_requ *req) 459 { 460 int rc = -EINVAL; 461 unsigned long data, offs; 462 struct pci_dev *pci_dev = cd->pci_dev; 463 464 if ((uaddr == NULL) || (size == 0)) { 465 m->size = 0; /* mark unused and not added */ 466 return -EINVAL; 467 } 468 m->u_vaddr = uaddr; 469 m->size = size; 470 471 /* determine space needed for page_list. */ 472 data = (unsigned long)uaddr; 473 offs = offset_in_page(data); 474 m->nr_pages = DIV_ROUND_UP(offs + size, PAGE_SIZE); 475 476 m->page_list = kcalloc(m->nr_pages, 477 sizeof(struct page *) + sizeof(dma_addr_t), 478 GFP_KERNEL); 479 if (!m->page_list) { 480 dev_err(&pci_dev->dev, "err: alloc page_list failed\n"); 481 m->nr_pages = 0; 482 m->u_vaddr = NULL; 483 m->size = 0; /* mark unused and not added */ 484 return -ENOMEM; 485 } 486 m->dma_list = (dma_addr_t *)(m->page_list + m->nr_pages); 487 488 /* pin user pages in memory */ 489 rc = get_user_pages_fast(data & PAGE_MASK, /* page aligned addr */ 490 m->nr_pages, 491 1, /* write by caller */ 492 m->page_list); /* ptrs to pages */ 493 494 /* assumption: get_user_pages can be killed by signals. */ 495 if (rc < m->nr_pages) { 496 free_user_pages(m->page_list, rc, 0); 497 rc = -EFAULT; 498 goto fail_get_user_pages; 499 } 500 501 rc = genwqe_map_pages(cd, m->page_list, m->nr_pages, m->dma_list); 502 if (rc != 0) 503 goto fail_free_user_pages; 504 505 return 0; 506 507 fail_free_user_pages: 508 free_user_pages(m->page_list, m->nr_pages, 0); 509 510 fail_get_user_pages: 511 kfree(m->page_list); 512 m->page_list = NULL; 513 m->dma_list = NULL; 514 m->nr_pages = 0; 515 m->u_vaddr = NULL; 516 m->size = 0; /* mark unused and not added */ 517 return rc; 518 } 519 520 /** 521 * genwqe_user_vunmap() - Undo mapping of user-space mem to virtual kernel 522 * memory 523 * @cd: pointer to genwqe device 524 * @m: mapping params 525 */ 526 int genwqe_user_vunmap(struct genwqe_dev *cd, struct dma_mapping *m, 527 struct ddcb_requ *req) 528 { 529 struct pci_dev *pci_dev = cd->pci_dev; 530 531 if (!dma_mapping_used(m)) { 532 dev_err(&pci_dev->dev, "[%s] err: mapping %p not used!\n", 533 __func__, m); 534 return -EINVAL; 535 } 536 537 if (m->dma_list) 538 genwqe_unmap_pages(cd, m->dma_list, m->nr_pages); 539 540 if (m->page_list) { 541 free_user_pages(m->page_list, m->nr_pages, 1); 542 543 kfree(m->page_list); 544 m->page_list = NULL; 545 m->dma_list = NULL; 546 m->nr_pages = 0; 547 } 548 549 m->u_vaddr = NULL; 550 m->size = 0; /* mark as unused and not added */ 551 return 0; 552 } 553 554 /** 555 * genwqe_card_type() - Get chip type SLU Configuration Register 556 * @cd: pointer to the genwqe device descriptor 557 * Return: 0: Altera Stratix-IV 230 558 * 1: Altera Stratix-IV 530 559 * 2: Altera Stratix-V A4 560 * 3: Altera Stratix-V A7 561 */ 562 u8 genwqe_card_type(struct genwqe_dev *cd) 563 { 564 u64 card_type = cd->slu_unitcfg; 565 return (u8)((card_type & IO_SLU_UNITCFG_TYPE_MASK) >> 20); 566 } 567 568 /** 569 * genwqe_card_reset() - Reset the card 570 * @cd: pointer to the genwqe device descriptor 571 */ 572 int genwqe_card_reset(struct genwqe_dev *cd) 573 { 574 u64 softrst; 575 struct pci_dev *pci_dev = cd->pci_dev; 576 577 if (!genwqe_is_privileged(cd)) 578 return -ENODEV; 579 580 /* new SL */ 581 __genwqe_writeq(cd, IO_SLC_CFGREG_SOFTRESET, 0x1ull); 582 msleep(1000); 583 __genwqe_readq(cd, IO_HSU_FIR_CLR); 584 __genwqe_readq(cd, IO_APP_FIR_CLR); 585 __genwqe_readq(cd, IO_SLU_FIR_CLR); 586 587 /* 588 * Read-modify-write to preserve the stealth bits 589 * 590 * For SL >= 039, Stealth WE bit allows removing 591 * the read-modify-wrote. 592 * r-m-w may require a mask 0x3C to avoid hitting hard 593 * reset again for error reset (should be 0, chicken). 594 */ 595 softrst = __genwqe_readq(cd, IO_SLC_CFGREG_SOFTRESET) & 0x3cull; 596 __genwqe_writeq(cd, IO_SLC_CFGREG_SOFTRESET, softrst | 0x2ull); 597 598 /* give ERRORRESET some time to finish */ 599 msleep(50); 600 601 if (genwqe_need_err_masking(cd)) { 602 dev_info(&pci_dev->dev, 603 "[%s] masking errors for old bitstreams\n", __func__); 604 __genwqe_writeq(cd, IO_SLC_MISC_DEBUG, 0x0aull); 605 } 606 return 0; 607 } 608 609 int genwqe_read_softreset(struct genwqe_dev *cd) 610 { 611 u64 bitstream; 612 613 if (!genwqe_is_privileged(cd)) 614 return -ENODEV; 615 616 bitstream = __genwqe_readq(cd, IO_SLU_BITSTREAM) & 0x1; 617 cd->softreset = (bitstream == 0) ? 0x8ull : 0xcull; 618 return 0; 619 } 620 621 /** 622 * genwqe_set_interrupt_capability() - Configure MSI capability structure 623 * @cd: pointer to the device 624 * Return: 0 if no error 625 */ 626 int genwqe_set_interrupt_capability(struct genwqe_dev *cd, int count) 627 { 628 int rc; 629 struct pci_dev *pci_dev = cd->pci_dev; 630 631 rc = pci_enable_msi_block(pci_dev, count); 632 if (rc == 0) 633 cd->flags |= GENWQE_FLAG_MSI_ENABLED; 634 return rc; 635 } 636 637 /** 638 * genwqe_reset_interrupt_capability() - Undo genwqe_set_interrupt_capability() 639 * @cd: pointer to the device 640 */ 641 void genwqe_reset_interrupt_capability(struct genwqe_dev *cd) 642 { 643 struct pci_dev *pci_dev = cd->pci_dev; 644 645 if (cd->flags & GENWQE_FLAG_MSI_ENABLED) { 646 pci_disable_msi(pci_dev); 647 cd->flags &= ~GENWQE_FLAG_MSI_ENABLED; 648 } 649 } 650 651 /** 652 * set_reg_idx() - Fill array with data. Ignore illegal offsets. 653 * @cd: card device 654 * @r: debug register array 655 * @i: index to desired entry 656 * @m: maximum possible entries 657 * @addr: addr which is read 658 * @index: index in debug array 659 * @val: read value 660 */ 661 static int set_reg_idx(struct genwqe_dev *cd, struct genwqe_reg *r, 662 unsigned int *i, unsigned int m, u32 addr, u32 idx, 663 u64 val) 664 { 665 if (WARN_ON_ONCE(*i >= m)) 666 return -EFAULT; 667 668 r[*i].addr = addr; 669 r[*i].idx = idx; 670 r[*i].val = val; 671 ++*i; 672 return 0; 673 } 674 675 static int set_reg(struct genwqe_dev *cd, struct genwqe_reg *r, 676 unsigned int *i, unsigned int m, u32 addr, u64 val) 677 { 678 return set_reg_idx(cd, r, i, m, addr, 0, val); 679 } 680 681 int genwqe_read_ffdc_regs(struct genwqe_dev *cd, struct genwqe_reg *regs, 682 unsigned int max_regs, int all) 683 { 684 unsigned int i, j, idx = 0; 685 u32 ufir_addr, ufec_addr, sfir_addr, sfec_addr; 686 u64 gfir, sluid, appid, ufir, ufec, sfir, sfec; 687 688 /* Global FIR */ 689 gfir = __genwqe_readq(cd, IO_SLC_CFGREG_GFIR); 690 set_reg(cd, regs, &idx, max_regs, IO_SLC_CFGREG_GFIR, gfir); 691 692 /* UnitCfg for SLU */ 693 sluid = __genwqe_readq(cd, IO_SLU_UNITCFG); /* 0x00000000 */ 694 set_reg(cd, regs, &idx, max_regs, IO_SLU_UNITCFG, sluid); 695 696 /* UnitCfg for APP */ 697 appid = __genwqe_readq(cd, IO_APP_UNITCFG); /* 0x02000000 */ 698 set_reg(cd, regs, &idx, max_regs, IO_APP_UNITCFG, appid); 699 700 /* Check all chip Units */ 701 for (i = 0; i < GENWQE_MAX_UNITS; i++) { 702 703 /* Unit FIR */ 704 ufir_addr = (i << 24) | 0x008; 705 ufir = __genwqe_readq(cd, ufir_addr); 706 set_reg(cd, regs, &idx, max_regs, ufir_addr, ufir); 707 708 /* Unit FEC */ 709 ufec_addr = (i << 24) | 0x018; 710 ufec = __genwqe_readq(cd, ufec_addr); 711 set_reg(cd, regs, &idx, max_regs, ufec_addr, ufec); 712 713 for (j = 0; j < 64; j++) { 714 /* wherever there is a primary 1, read the 2ndary */ 715 if (!all && (!(ufir & (1ull << j)))) 716 continue; 717 718 sfir_addr = (i << 24) | (0x100 + 8 * j); 719 sfir = __genwqe_readq(cd, sfir_addr); 720 set_reg(cd, regs, &idx, max_regs, sfir_addr, sfir); 721 722 sfec_addr = (i << 24) | (0x300 + 8 * j); 723 sfec = __genwqe_readq(cd, sfec_addr); 724 set_reg(cd, regs, &idx, max_regs, sfec_addr, sfec); 725 } 726 } 727 728 /* fill with invalid data until end */ 729 for (i = idx; i < max_regs; i++) { 730 regs[i].addr = 0xffffffff; 731 regs[i].val = 0xffffffffffffffffull; 732 } 733 return idx; 734 } 735 736 /** 737 * genwqe_ffdc_buff_size() - Calculates the number of dump registers 738 */ 739 int genwqe_ffdc_buff_size(struct genwqe_dev *cd, int uid) 740 { 741 int entries = 0, ring, traps, traces, trace_entries; 742 u32 eevptr_addr, l_addr, d_len, d_type; 743 u64 eevptr, val, addr; 744 745 eevptr_addr = GENWQE_UID_OFFS(uid) | IO_EXTENDED_ERROR_POINTER; 746 eevptr = __genwqe_readq(cd, eevptr_addr); 747 748 if ((eevptr != 0x0) && (eevptr != -1ull)) { 749 l_addr = GENWQE_UID_OFFS(uid) | eevptr; 750 751 while (1) { 752 val = __genwqe_readq(cd, l_addr); 753 754 if ((val == 0x0) || (val == -1ull)) 755 break; 756 757 /* 38:24 */ 758 d_len = (val & 0x0000007fff000000ull) >> 24; 759 760 /* 39 */ 761 d_type = (val & 0x0000008000000000ull) >> 36; 762 763 if (d_type) { /* repeat */ 764 entries += d_len; 765 } else { /* size in bytes! */ 766 entries += d_len >> 3; 767 } 768 769 l_addr += 8; 770 } 771 } 772 773 for (ring = 0; ring < 8; ring++) { 774 addr = GENWQE_UID_OFFS(uid) | IO_EXTENDED_DIAG_MAP(ring); 775 val = __genwqe_readq(cd, addr); 776 777 if ((val == 0x0ull) || (val == -1ull)) 778 continue; 779 780 traps = (val >> 24) & 0xff; 781 traces = (val >> 16) & 0xff; 782 trace_entries = val & 0xffff; 783 784 entries += traps + (traces * trace_entries); 785 } 786 return entries; 787 } 788 789 /** 790 * genwqe_ffdc_buff_read() - Implements LogoutExtendedErrorRegisters procedure 791 */ 792 int genwqe_ffdc_buff_read(struct genwqe_dev *cd, int uid, 793 struct genwqe_reg *regs, unsigned int max_regs) 794 { 795 int i, traps, traces, trace, trace_entries, trace_entry, ring; 796 unsigned int idx = 0; 797 u32 eevptr_addr, l_addr, d_addr, d_len, d_type; 798 u64 eevptr, e, val, addr; 799 800 eevptr_addr = GENWQE_UID_OFFS(uid) | IO_EXTENDED_ERROR_POINTER; 801 eevptr = __genwqe_readq(cd, eevptr_addr); 802 803 if ((eevptr != 0x0) && (eevptr != 0xffffffffffffffffull)) { 804 l_addr = GENWQE_UID_OFFS(uid) | eevptr; 805 while (1) { 806 e = __genwqe_readq(cd, l_addr); 807 if ((e == 0x0) || (e == 0xffffffffffffffffull)) 808 break; 809 810 d_addr = (e & 0x0000000000ffffffull); /* 23:0 */ 811 d_len = (e & 0x0000007fff000000ull) >> 24; /* 38:24 */ 812 d_type = (e & 0x0000008000000000ull) >> 36; /* 39 */ 813 d_addr |= GENWQE_UID_OFFS(uid); 814 815 if (d_type) { 816 for (i = 0; i < (int)d_len; i++) { 817 val = __genwqe_readq(cd, d_addr); 818 set_reg_idx(cd, regs, &idx, max_regs, 819 d_addr, i, val); 820 } 821 } else { 822 d_len >>= 3; /* Size in bytes! */ 823 for (i = 0; i < (int)d_len; i++, d_addr += 8) { 824 val = __genwqe_readq(cd, d_addr); 825 set_reg_idx(cd, regs, &idx, max_regs, 826 d_addr, 0, val); 827 } 828 } 829 l_addr += 8; 830 } 831 } 832 833 /* 834 * To save time, there are only 6 traces poplulated on Uid=2, 835 * Ring=1. each with iters=512. 836 */ 837 for (ring = 0; ring < 8; ring++) { /* 0 is fls, 1 is fds, 838 2...7 are ASI rings */ 839 addr = GENWQE_UID_OFFS(uid) | IO_EXTENDED_DIAG_MAP(ring); 840 val = __genwqe_readq(cd, addr); 841 842 if ((val == 0x0ull) || (val == -1ull)) 843 continue; 844 845 traps = (val >> 24) & 0xff; /* Number of Traps */ 846 traces = (val >> 16) & 0xff; /* Number of Traces */ 847 trace_entries = val & 0xffff; /* Entries per trace */ 848 849 /* Note: This is a combined loop that dumps both the traps */ 850 /* (for the trace == 0 case) as well as the traces 1 to */ 851 /* 'traces'. */ 852 for (trace = 0; trace <= traces; trace++) { 853 u32 diag_sel = 854 GENWQE_EXTENDED_DIAG_SELECTOR(ring, trace); 855 856 addr = (GENWQE_UID_OFFS(uid) | 857 IO_EXTENDED_DIAG_SELECTOR); 858 __genwqe_writeq(cd, addr, diag_sel); 859 860 for (trace_entry = 0; 861 trace_entry < (trace ? trace_entries : traps); 862 trace_entry++) { 863 addr = (GENWQE_UID_OFFS(uid) | 864 IO_EXTENDED_DIAG_READ_MBX); 865 val = __genwqe_readq(cd, addr); 866 set_reg_idx(cd, regs, &idx, max_regs, addr, 867 (diag_sel<<16) | trace_entry, val); 868 } 869 } 870 } 871 return 0; 872 } 873 874 /** 875 * genwqe_write_vreg() - Write register in virtual window 876 * 877 * Note, these registers are only accessible to the PF through the 878 * VF-window. It is not intended for the VF to access. 879 */ 880 int genwqe_write_vreg(struct genwqe_dev *cd, u32 reg, u64 val, int func) 881 { 882 __genwqe_writeq(cd, IO_PF_SLC_VIRTUAL_WINDOW, func & 0xf); 883 __genwqe_writeq(cd, reg, val); 884 return 0; 885 } 886 887 /** 888 * genwqe_read_vreg() - Read register in virtual window 889 * 890 * Note, these registers are only accessible to the PF through the 891 * VF-window. It is not intended for the VF to access. 892 */ 893 u64 genwqe_read_vreg(struct genwqe_dev *cd, u32 reg, int func) 894 { 895 __genwqe_writeq(cd, IO_PF_SLC_VIRTUAL_WINDOW, func & 0xf); 896 return __genwqe_readq(cd, reg); 897 } 898 899 /** 900 * genwqe_base_clock_frequency() - Deteremine base clock frequency of the card 901 * 902 * Note: From a design perspective it turned out to be a bad idea to 903 * use codes here to specifiy the frequency/speed values. An old 904 * driver cannot understand new codes and is therefore always a 905 * problem. Better is to measure out the value or put the 906 * speed/frequency directly into a register which is always a valid 907 * value for old as well as for new software. 908 * 909 * Return: Card clock in MHz 910 */ 911 int genwqe_base_clock_frequency(struct genwqe_dev *cd) 912 { 913 u16 speed; /* MHz MHz MHz MHz */ 914 static const int speed_grade[] = { 250, 200, 166, 175 }; 915 916 speed = (u16)((cd->slu_unitcfg >> 28) & 0x0full); 917 if (speed >= ARRAY_SIZE(speed_grade)) 918 return 0; /* illegal value */ 919 920 return speed_grade[speed]; 921 } 922 923 /** 924 * genwqe_stop_traps() - Stop traps 925 * 926 * Before reading out the analysis data, we need to stop the traps. 927 */ 928 void genwqe_stop_traps(struct genwqe_dev *cd) 929 { 930 __genwqe_writeq(cd, IO_SLC_MISC_DEBUG_SET, 0xcull); 931 } 932 933 /** 934 * genwqe_start_traps() - Start traps 935 * 936 * After having read the data, we can/must enable the traps again. 937 */ 938 void genwqe_start_traps(struct genwqe_dev *cd) 939 { 940 __genwqe_writeq(cd, IO_SLC_MISC_DEBUG_CLR, 0xcull); 941 942 if (genwqe_need_err_masking(cd)) 943 __genwqe_writeq(cd, IO_SLC_MISC_DEBUG, 0x0aull); 944 } 945