1 #ifndef __CARD_BASE_H__ 2 #define __CARD_BASE_H__ 3 4 /** 5 * IBM Accelerator Family 'GenWQE' 6 * 7 * (C) Copyright IBM Corp. 2013 8 * 9 * Author: Frank Haverkamp <haver@linux.vnet.ibm.com> 10 * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com> 11 * Author: Michael Jung <mijung@gmx.net> 12 * Author: Michael Ruettger <michael@ibmra.de> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License (version 2 only) 16 * as published by the Free Software Foundation. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 */ 23 24 /* 25 * Interfaces within the GenWQE module. Defines genwqe_card and 26 * ddcb_queue as well as ddcb_requ. 27 */ 28 29 #include <linux/kernel.h> 30 #include <linux/types.h> 31 #include <linux/cdev.h> 32 #include <linux/stringify.h> 33 #include <linux/pci.h> 34 #include <linux/semaphore.h> 35 #include <linux/uaccess.h> 36 #include <linux/io.h> 37 #include <linux/debugfs.h> 38 #include <linux/slab.h> 39 40 #include <linux/genwqe/genwqe_card.h> 41 #include "genwqe_driver.h" 42 43 #define GENWQE_MSI_IRQS 4 /* Just one supported, no MSIx */ 44 45 #define GENWQE_MAX_VFS 15 /* maximum 15 VFs are possible */ 46 #define GENWQE_MAX_FUNCS 16 /* 1 PF and 15 VFs */ 47 #define GENWQE_CARD_NO_MAX (16 * GENWQE_MAX_FUNCS) 48 49 /* Compile parameters, some of them appear in debugfs for later adjustment */ 50 #define GENWQE_DDCB_MAX 32 /* DDCBs on the work-queue */ 51 #define GENWQE_POLLING_ENABLED 0 /* in case of irqs not working */ 52 #define GENWQE_DDCB_SOFTWARE_TIMEOUT 10 /* timeout per DDCB in seconds */ 53 #define GENWQE_KILL_TIMEOUT 8 /* time until process gets killed */ 54 #define GENWQE_VF_JOBTIMEOUT_MSEC 250 /* 250 msec */ 55 #define GENWQE_PF_JOBTIMEOUT_MSEC 8000 /* 8 sec should be ok */ 56 #define GENWQE_HEALTH_CHECK_INTERVAL 4 /* <= 0: disabled */ 57 58 /* Sysfs attribute groups used when we create the genwqe device */ 59 extern const struct attribute_group *genwqe_attribute_groups[]; 60 61 /* 62 * Config space for Genwqe5 A7: 63 * 00:[14 10 4b 04]40 00 10 00[00 00 00 12]00 00 00 00 64 * 10: 0c 00 00 f0 07 3c 00 00 00 00 00 00 00 00 00 00 65 * 20: 00 00 00 00 00 00 00 00 00 00 00 00[14 10 4b 04] 66 * 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 00 00 00 67 */ 68 #define PCI_DEVICE_GENWQE 0x044b /* Genwqe DeviceID */ 69 70 #define PCI_SUBSYSTEM_ID_GENWQE5 0x035f /* Genwqe A5 Subsystem-ID */ 71 #define PCI_SUBSYSTEM_ID_GENWQE5_NEW 0x044b /* Genwqe A5 Subsystem-ID */ 72 #define PCI_CLASSCODE_GENWQE5 0x1200 /* UNKNOWN */ 73 74 #define PCI_SUBVENDOR_ID_IBM_SRIOV 0x0000 75 #define PCI_SUBSYSTEM_ID_GENWQE5_SRIOV 0x0000 /* Genwqe A5 Subsystem-ID */ 76 #define PCI_CLASSCODE_GENWQE5_SRIOV 0x1200 /* UNKNOWN */ 77 78 #define GENWQE_SLU_ARCH_REQ 2 /* Required SLU architecture level */ 79 80 /** 81 * struct genwqe_reg - Genwqe data dump functionality 82 */ 83 struct genwqe_reg { 84 u32 addr; 85 u32 idx; 86 u64 val; 87 }; 88 89 /* 90 * enum genwqe_dbg_type - Specify chip unit to dump/debug 91 */ 92 enum genwqe_dbg_type { 93 GENWQE_DBG_UNIT0 = 0, /* captured before prev errs cleared */ 94 GENWQE_DBG_UNIT1 = 1, 95 GENWQE_DBG_UNIT2 = 2, 96 GENWQE_DBG_UNIT3 = 3, 97 GENWQE_DBG_UNIT4 = 4, 98 GENWQE_DBG_UNIT5 = 5, 99 GENWQE_DBG_UNIT6 = 6, 100 GENWQE_DBG_UNIT7 = 7, 101 GENWQE_DBG_REGS = 8, 102 GENWQE_DBG_DMA = 9, 103 GENWQE_DBG_UNITS = 10, /* max number of possible debug units */ 104 }; 105 106 /* Software error injection to simulate card failures */ 107 #define GENWQE_INJECT_HARDWARE_FAILURE 0x00000001 /* injects -1 reg reads */ 108 #define GENWQE_INJECT_BUS_RESET_FAILURE 0x00000002 /* pci_bus_reset fail */ 109 #define GENWQE_INJECT_GFIR_FATAL 0x00000004 /* GFIR = 0x0000ffff */ 110 #define GENWQE_INJECT_GFIR_INFO 0x00000008 /* GFIR = 0xffff0000 */ 111 112 /* 113 * Genwqe card description and management data. 114 * 115 * Error-handling in case of card malfunction 116 * ------------------------------------------ 117 * 118 * If the card is detected to be defective the outside environment 119 * will cause the PCI layer to call deinit (the cleanup function for 120 * probe). This is the same effect like doing a unbind/bind operation 121 * on the card. 122 * 123 * The genwqe card driver implements a health checking thread which 124 * verifies the card function. If this detects a problem the cards 125 * device is being shutdown and restarted again, along with a reset of 126 * the card and queue. 127 * 128 * All functions accessing the card device return either -EIO or -ENODEV 129 * code to indicate the malfunction to the user. The user has to close 130 * the file descriptor and open a new one, once the card becomes 131 * available again. 132 * 133 * If the open file descriptor is setup to receive SIGIO, the signal is 134 * genereated for the application which has to provide a handler to 135 * react on it. If the application does not close the open 136 * file descriptor a SIGKILL is send to enforce freeing the cards 137 * resources. 138 * 139 * I did not find a different way to prevent kernel problems due to 140 * reference counters for the cards character devices getting out of 141 * sync. The character device deallocation does not block, even if 142 * there is still an open file descriptor pending. If this pending 143 * descriptor is closed, the data structures used by the character 144 * device is reinstantiated, which will lead to the reference counter 145 * dropping below the allowed values. 146 * 147 * Card recovery 148 * ------------- 149 * 150 * To test the internal driver recovery the following command can be used: 151 * sudo sh -c 'echo 0xfffff > /sys/class/genwqe/genwqe0_card/err_inject' 152 */ 153 154 155 /** 156 * struct dma_mapping_type - Mapping type definition 157 * 158 * To avoid memcpying data arround we use user memory directly. To do 159 * this we need to pin/swap-in the memory and request a DMA address 160 * for it. 161 */ 162 enum dma_mapping_type { 163 GENWQE_MAPPING_RAW = 0, /* contignous memory buffer */ 164 GENWQE_MAPPING_SGL_TEMP, /* sglist dynamically used */ 165 GENWQE_MAPPING_SGL_PINNED, /* sglist used with pinning */ 166 }; 167 168 /** 169 * struct dma_mapping - Information about memory mappings done by the driver 170 */ 171 struct dma_mapping { 172 enum dma_mapping_type type; 173 174 void *u_vaddr; /* user-space vaddr/non-aligned */ 175 void *k_vaddr; /* kernel-space vaddr/non-aligned */ 176 dma_addr_t dma_addr; /* physical DMA address */ 177 178 struct page **page_list; /* list of pages used by user buff */ 179 dma_addr_t *dma_list; /* list of dma addresses per page */ 180 unsigned int nr_pages; /* number of pages */ 181 unsigned int size; /* size in bytes */ 182 183 struct list_head card_list; /* list of usr_maps for card */ 184 struct list_head pin_list; /* list of pinned memory for dev */ 185 int write; /* writable map? useful in unmapping */ 186 }; 187 188 static inline void genwqe_mapping_init(struct dma_mapping *m, 189 enum dma_mapping_type type) 190 { 191 memset(m, 0, sizeof(*m)); 192 m->type = type; 193 m->write = 1; /* Assume the maps we create are R/W */ 194 } 195 196 /** 197 * struct ddcb_queue - DDCB queue data 198 * @ddcb_max: Number of DDCBs on the queue 199 * @ddcb_next: Next free DDCB 200 * @ddcb_act: Next DDCB supposed to finish 201 * @ddcb_seq: Sequence number of last DDCB 202 * @ddcbs_in_flight: Currently enqueued DDCBs 203 * @ddcbs_completed: Number of already completed DDCBs 204 * @return_on_busy: Number of -EBUSY returns on full queue 205 * @wait_on_busy: Number of waits on full queue 206 * @ddcb_daddr: DMA address of first DDCB in the queue 207 * @ddcb_vaddr: Kernel virtual address of first DDCB in the queue 208 * @ddcb_req: Associated requests (one per DDCB) 209 * @ddcb_waitqs: Associated wait queues (one per DDCB) 210 * @ddcb_lock: Lock to protect queuing operations 211 * @ddcb_waitq: Wait on next DDCB finishing 212 */ 213 214 struct ddcb_queue { 215 int ddcb_max; /* amount of DDCBs */ 216 int ddcb_next; /* next available DDCB num */ 217 int ddcb_act; /* DDCB to be processed */ 218 u16 ddcb_seq; /* slc seq num */ 219 unsigned int ddcbs_in_flight; /* number of ddcbs in processing */ 220 unsigned int ddcbs_completed; 221 unsigned int ddcbs_max_in_flight; 222 unsigned int return_on_busy; /* how many times -EBUSY? */ 223 unsigned int wait_on_busy; 224 225 dma_addr_t ddcb_daddr; /* DMA address */ 226 struct ddcb *ddcb_vaddr; /* kernel virtual addr for DDCBs */ 227 struct ddcb_requ **ddcb_req; /* ddcb processing parameter */ 228 wait_queue_head_t *ddcb_waitqs; /* waitqueue per ddcb */ 229 230 spinlock_t ddcb_lock; /* exclusive access to queue */ 231 wait_queue_head_t busy_waitq; /* wait for ddcb processing */ 232 233 /* registers or the respective queue to be used */ 234 u32 IO_QUEUE_CONFIG; 235 u32 IO_QUEUE_STATUS; 236 u32 IO_QUEUE_SEGMENT; 237 u32 IO_QUEUE_INITSQN; 238 u32 IO_QUEUE_WRAP; 239 u32 IO_QUEUE_OFFSET; 240 u32 IO_QUEUE_WTIME; 241 u32 IO_QUEUE_ERRCNTS; 242 u32 IO_QUEUE_LRW; 243 }; 244 245 /* 246 * GFIR, SLU_UNITCFG, APP_UNITCFG 247 * 8 Units with FIR/FEC + 64 * 2ndary FIRS/FEC. 248 */ 249 #define GENWQE_FFDC_REGS (3 + (8 * (2 + 2 * 64))) 250 251 struct genwqe_ffdc { 252 unsigned int entries; 253 struct genwqe_reg *regs; 254 }; 255 256 /** 257 * struct genwqe_dev - GenWQE device information 258 * @card_state: Card operation state, see above 259 * @ffdc: First Failure Data Capture buffers for each unit 260 * @card_thread: Working thread to operate the DDCB queue 261 * @card_waitq: Wait queue used in card_thread 262 * @queue: DDCB queue 263 * @health_thread: Card monitoring thread (only for PFs) 264 * @health_waitq: Wait queue used in health_thread 265 * @pci_dev: Associated PCI device (function) 266 * @mmio: Base address of 64-bit register space 267 * @mmio_len: Length of register area 268 * @file_lock: Lock to protect access to file_list 269 * @file_list: List of all processes with open GenWQE file descriptors 270 * 271 * This struct contains all information needed to communicate with a 272 * GenWQE card. It is initialized when a GenWQE device is found and 273 * destroyed when it goes away. It holds data to maintain the queue as 274 * well as data needed to feed the user interfaces. 275 */ 276 struct genwqe_dev { 277 enum genwqe_card_state card_state; 278 spinlock_t print_lock; 279 280 int card_idx; /* card index 0..CARD_NO_MAX-1 */ 281 u64 flags; /* general flags */ 282 283 /* FFDC data gathering */ 284 struct genwqe_ffdc ffdc[GENWQE_DBG_UNITS]; 285 286 /* DDCB workqueue */ 287 struct task_struct *card_thread; 288 wait_queue_head_t queue_waitq; 289 struct ddcb_queue queue; /* genwqe DDCB queue */ 290 unsigned int irqs_processed; 291 292 /* Card health checking thread */ 293 struct task_struct *health_thread; 294 wait_queue_head_t health_waitq; 295 296 int use_platform_recovery; /* use platform recovery mechanisms */ 297 298 /* char device */ 299 dev_t devnum_genwqe; /* major/minor num card */ 300 struct class *class_genwqe; /* reference to class object */ 301 struct device *dev; /* for device creation */ 302 struct cdev cdev_genwqe; /* char device for card */ 303 304 struct dentry *debugfs_root; /* debugfs card root directory */ 305 struct dentry *debugfs_genwqe; /* debugfs driver root directory */ 306 307 /* pci resources */ 308 struct pci_dev *pci_dev; /* PCI device */ 309 void __iomem *mmio; /* BAR-0 MMIO start */ 310 unsigned long mmio_len; 311 int num_vfs; 312 u32 vf_jobtimeout_msec[GENWQE_MAX_VFS]; 313 int is_privileged; /* access to all regs possible */ 314 315 /* config regs which we need often */ 316 u64 slu_unitcfg; 317 u64 app_unitcfg; 318 u64 softreset; 319 u64 err_inject; 320 u64 last_gfir; 321 char app_name[5]; 322 323 spinlock_t file_lock; /* lock for open files */ 324 struct list_head file_list; /* list of open files */ 325 326 /* debugfs parameters */ 327 int ddcb_software_timeout; /* wait until DDCB times out */ 328 int skip_recovery; /* circumvention if recovery fails */ 329 int kill_timeout; /* wait after sending SIGKILL */ 330 }; 331 332 /** 333 * enum genwqe_requ_state - State of a DDCB execution request 334 */ 335 enum genwqe_requ_state { 336 GENWQE_REQU_NEW = 0, 337 GENWQE_REQU_ENQUEUED = 1, 338 GENWQE_REQU_TAPPED = 2, 339 GENWQE_REQU_FINISHED = 3, 340 GENWQE_REQU_STATE_MAX, 341 }; 342 343 /** 344 * struct genwqe_sgl - Scatter gather list describing user-space memory 345 * @sgl: scatter gather list needs to be 128 byte aligned 346 * @sgl_dma_addr: dma address of sgl 347 * @sgl_size: size of area used for sgl 348 * @user_addr: user-space address of memory area 349 * @user_size: size of user-space memory area 350 * @page: buffer for partial pages if needed 351 * @page_dma_addr: dma address partial pages 352 * @write: should we write it back to userspace? 353 */ 354 struct genwqe_sgl { 355 dma_addr_t sgl_dma_addr; 356 struct sg_entry *sgl; 357 size_t sgl_size; /* size of sgl */ 358 359 void __user *user_addr; /* user-space base-address */ 360 size_t user_size; /* size of memory area */ 361 362 int write; 363 364 unsigned long nr_pages; 365 unsigned long fpage_offs; 366 size_t fpage_size; 367 size_t lpage_size; 368 369 void *fpage; 370 dma_addr_t fpage_dma_addr; 371 372 void *lpage; 373 dma_addr_t lpage_dma_addr; 374 }; 375 376 int genwqe_alloc_sync_sgl(struct genwqe_dev *cd, struct genwqe_sgl *sgl, 377 void __user *user_addr, size_t user_size, int write); 378 379 int genwqe_setup_sgl(struct genwqe_dev *cd, struct genwqe_sgl *sgl, 380 dma_addr_t *dma_list); 381 382 int genwqe_free_sync_sgl(struct genwqe_dev *cd, struct genwqe_sgl *sgl); 383 384 /** 385 * struct ddcb_requ - Kernel internal representation of the DDCB request 386 * @cmd: User space representation of the DDCB execution request 387 */ 388 struct ddcb_requ { 389 /* kernel specific content */ 390 enum genwqe_requ_state req_state; /* request status */ 391 int num; /* ddcb_no for this request */ 392 struct ddcb_queue *queue; /* associated queue */ 393 394 struct dma_mapping dma_mappings[DDCB_FIXUPS]; 395 struct genwqe_sgl sgls[DDCB_FIXUPS]; 396 397 /* kernel/user shared content */ 398 struct genwqe_ddcb_cmd cmd; /* ddcb_no for this request */ 399 struct genwqe_debug_data debug_data; 400 }; 401 402 /** 403 * struct genwqe_file - Information for open GenWQE devices 404 */ 405 struct genwqe_file { 406 struct genwqe_dev *cd; 407 struct genwqe_driver *client; 408 struct file *filp; 409 410 struct fasync_struct *async_queue; 411 struct task_struct *owner; 412 struct list_head list; /* entry in list of open files */ 413 414 spinlock_t map_lock; /* lock for dma_mappings */ 415 struct list_head map_list; /* list of dma_mappings */ 416 417 spinlock_t pin_lock; /* lock for pinned memory */ 418 struct list_head pin_list; /* list of pinned memory */ 419 }; 420 421 int genwqe_setup_service_layer(struct genwqe_dev *cd); /* for PF only */ 422 int genwqe_finish_queue(struct genwqe_dev *cd); 423 int genwqe_release_service_layer(struct genwqe_dev *cd); 424 425 /** 426 * genwqe_get_slu_id() - Read Service Layer Unit Id 427 * Return: 0x00: Development code 428 * 0x01: SLC1 (old) 429 * 0x02: SLC2 (sept2012) 430 * 0x03: SLC2 (feb2013, generic driver) 431 */ 432 static inline int genwqe_get_slu_id(struct genwqe_dev *cd) 433 { 434 return (int)((cd->slu_unitcfg >> 32) & 0xff); 435 } 436 437 int genwqe_ddcbs_in_flight(struct genwqe_dev *cd); 438 439 u8 genwqe_card_type(struct genwqe_dev *cd); 440 int genwqe_card_reset(struct genwqe_dev *cd); 441 int genwqe_set_interrupt_capability(struct genwqe_dev *cd, int count); 442 void genwqe_reset_interrupt_capability(struct genwqe_dev *cd); 443 444 int genwqe_device_create(struct genwqe_dev *cd); 445 int genwqe_device_remove(struct genwqe_dev *cd); 446 447 /* debugfs */ 448 int genwqe_init_debugfs(struct genwqe_dev *cd); 449 void genqwe_exit_debugfs(struct genwqe_dev *cd); 450 451 int genwqe_read_softreset(struct genwqe_dev *cd); 452 453 /* Hardware Circumventions */ 454 int genwqe_recovery_on_fatal_gfir_required(struct genwqe_dev *cd); 455 int genwqe_flash_readback_fails(struct genwqe_dev *cd); 456 457 /** 458 * genwqe_write_vreg() - Write register in VF window 459 * @cd: genwqe device 460 * @reg: register address 461 * @val: value to write 462 * @func: 0: PF, 1: VF0, ..., 15: VF14 463 */ 464 int genwqe_write_vreg(struct genwqe_dev *cd, u32 reg, u64 val, int func); 465 466 /** 467 * genwqe_read_vreg() - Read register in VF window 468 * @cd: genwqe device 469 * @reg: register address 470 * @func: 0: PF, 1: VF0, ..., 15: VF14 471 * 472 * Return: content of the register 473 */ 474 u64 genwqe_read_vreg(struct genwqe_dev *cd, u32 reg, int func); 475 476 /* FFDC Buffer Management */ 477 int genwqe_ffdc_buff_size(struct genwqe_dev *cd, int unit_id); 478 int genwqe_ffdc_buff_read(struct genwqe_dev *cd, int unit_id, 479 struct genwqe_reg *regs, unsigned int max_regs); 480 int genwqe_read_ffdc_regs(struct genwqe_dev *cd, struct genwqe_reg *regs, 481 unsigned int max_regs, int all); 482 int genwqe_ffdc_dump_dma(struct genwqe_dev *cd, 483 struct genwqe_reg *regs, unsigned int max_regs); 484 485 int genwqe_init_debug_data(struct genwqe_dev *cd, 486 struct genwqe_debug_data *d); 487 488 void genwqe_init_crc32(void); 489 int genwqe_read_app_id(struct genwqe_dev *cd, char *app_name, int len); 490 491 /* Memory allocation/deallocation; dma address handling */ 492 int genwqe_user_vmap(struct genwqe_dev *cd, struct dma_mapping *m, 493 void *uaddr, unsigned long size); 494 495 int genwqe_user_vunmap(struct genwqe_dev *cd, struct dma_mapping *m); 496 497 static inline bool dma_mapping_used(struct dma_mapping *m) 498 { 499 if (!m) 500 return 0; 501 return m->size != 0; 502 } 503 504 /** 505 * __genwqe_execute_ddcb() - Execute DDCB request with addr translation 506 * 507 * This function will do the address translation changes to the DDCBs 508 * according to the definitions required by the ATS field. It looks up 509 * the memory allocation buffer or does vmap/vunmap for the respective 510 * user-space buffers, inclusive page pinning and scatter gather list 511 * buildup and teardown. 512 */ 513 int __genwqe_execute_ddcb(struct genwqe_dev *cd, 514 struct genwqe_ddcb_cmd *cmd, unsigned int f_flags); 515 516 /** 517 * __genwqe_execute_raw_ddcb() - Execute DDCB request without addr translation 518 * 519 * This version will not do address translation or any modification of 520 * the DDCB data. It is used e.g. for the MoveFlash DDCB which is 521 * entirely prepared by the driver itself. That means the appropriate 522 * DMA addresses are already in the DDCB and do not need any 523 * modification. 524 */ 525 int __genwqe_execute_raw_ddcb(struct genwqe_dev *cd, 526 struct genwqe_ddcb_cmd *cmd, 527 unsigned int f_flags); 528 int __genwqe_enqueue_ddcb(struct genwqe_dev *cd, 529 struct ddcb_requ *req, 530 unsigned int f_flags); 531 532 int __genwqe_wait_ddcb(struct genwqe_dev *cd, struct ddcb_requ *req); 533 int __genwqe_purge_ddcb(struct genwqe_dev *cd, struct ddcb_requ *req); 534 535 /* register access */ 536 int __genwqe_writeq(struct genwqe_dev *cd, u64 byte_offs, u64 val); 537 u64 __genwqe_readq(struct genwqe_dev *cd, u64 byte_offs); 538 int __genwqe_writel(struct genwqe_dev *cd, u64 byte_offs, u32 val); 539 u32 __genwqe_readl(struct genwqe_dev *cd, u64 byte_offs); 540 541 void *__genwqe_alloc_consistent(struct genwqe_dev *cd, size_t size, 542 dma_addr_t *dma_handle); 543 void __genwqe_free_consistent(struct genwqe_dev *cd, size_t size, 544 void *vaddr, dma_addr_t dma_handle); 545 546 /* Base clock frequency in MHz */ 547 int genwqe_base_clock_frequency(struct genwqe_dev *cd); 548 549 /* Before FFDC is captured the traps should be stopped. */ 550 void genwqe_stop_traps(struct genwqe_dev *cd); 551 void genwqe_start_traps(struct genwqe_dev *cd); 552 553 /* Hardware circumvention */ 554 bool genwqe_need_err_masking(struct genwqe_dev *cd); 555 556 /** 557 * genwqe_is_privileged() - Determine operation mode for PCI function 558 * 559 * On Intel with SRIOV support we see: 560 * PF: is_physfn = 1 is_virtfn = 0 561 * VF: is_physfn = 0 is_virtfn = 1 562 * 563 * On Systems with no SRIOV support _and_ virtualized systems we get: 564 * is_physfn = 0 is_virtfn = 0 565 * 566 * Other vendors have individual pci device ids to distinguish between 567 * virtual function drivers and physical function drivers. GenWQE 568 * unfortunately has just on pci device id for both, VFs and PF. 569 * 570 * The following code is used to distinguish if the card is running in 571 * privileged mode, either as true PF or in a virtualized system with 572 * full register access e.g. currently on PowerPC. 573 * 574 * if (pci_dev->is_virtfn) 575 * cd->is_privileged = 0; 576 * else 577 * cd->is_privileged = (__genwqe_readq(cd, IO_SLU_BITSTREAM) 578 * != IO_ILLEGAL_VALUE); 579 */ 580 static inline int genwqe_is_privileged(struct genwqe_dev *cd) 581 { 582 return cd->is_privileged; 583 } 584 585 #endif /* __CARD_BASE_H__ */ 586