1 #ifndef __CARD_BASE_H__ 2 #define __CARD_BASE_H__ 3 4 /** 5 * IBM Accelerator Family 'GenWQE' 6 * 7 * (C) Copyright IBM Corp. 2013 8 * 9 * Author: Frank Haverkamp <haver@linux.vnet.ibm.com> 10 * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com> 11 * Author: Michael Jung <mijung@gmx.net> 12 * Author: Michael Ruettger <michael@ibmra.de> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License (version 2 only) 16 * as published by the Free Software Foundation. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 */ 23 24 /* 25 * Interfaces within the GenWQE module. Defines genwqe_card and 26 * ddcb_queue as well as ddcb_requ. 27 */ 28 29 #include <linux/kernel.h> 30 #include <linux/types.h> 31 #include <linux/cdev.h> 32 #include <linux/stringify.h> 33 #include <linux/pci.h> 34 #include <linux/semaphore.h> 35 #include <linux/uaccess.h> 36 #include <linux/io.h> 37 #include <linux/debugfs.h> 38 #include <linux/slab.h> 39 40 #include <linux/genwqe/genwqe_card.h> 41 #include "genwqe_driver.h" 42 43 #define GENWQE_MSI_IRQS 4 /* Just one supported, no MSIx */ 44 45 #define GENWQE_MAX_VFS 15 /* maximum 15 VFs are possible */ 46 #define GENWQE_MAX_FUNCS 16 /* 1 PF and 15 VFs */ 47 #define GENWQE_CARD_NO_MAX (16 * GENWQE_MAX_FUNCS) 48 49 /* Compile parameters, some of them appear in debugfs for later adjustment */ 50 #define genwqe_ddcb_max 32 /* DDCBs on the work-queue */ 51 #define genwqe_polling_enabled 0 /* in case of irqs not working */ 52 #define genwqe_ddcb_software_timeout 10 /* timeout per DDCB in seconds */ 53 #define genwqe_kill_timeout 8 /* time until process gets killed */ 54 #define genwqe_vf_jobtimeout_msec 250 /* 250 msec */ 55 #define genwqe_pf_jobtimeout_msec 8000 /* 8 sec should be ok */ 56 #define genwqe_health_check_interval 4 /* <= 0: disabled */ 57 58 /* Sysfs attribute groups used when we create the genwqe device */ 59 extern const struct attribute_group *genwqe_attribute_groups[]; 60 61 /* 62 * Config space for Genwqe5 A7: 63 * 00:[14 10 4b 04]40 00 10 00[00 00 00 12]00 00 00 00 64 * 10: 0c 00 00 f0 07 3c 00 00 00 00 00 00 00 00 00 00 65 * 20: 00 00 00 00 00 00 00 00 00 00 00 00[14 10 4b 04] 66 * 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 00 00 00 67 */ 68 #define PCI_DEVICE_GENWQE 0x044b /* Genwqe DeviceID */ 69 70 #define PCI_SUBSYSTEM_ID_GENWQE5 0x035f /* Genwqe A5 Subsystem-ID */ 71 #define PCI_SUBSYSTEM_ID_GENWQE5_NEW 0x044b /* Genwqe A5 Subsystem-ID */ 72 #define PCI_CLASSCODE_GENWQE5 0x1200 /* UNKNOWN */ 73 74 #define PCI_SUBVENDOR_ID_IBM_SRIOV 0x0000 75 #define PCI_SUBSYSTEM_ID_GENWQE5_SRIOV 0x0000 /* Genwqe A5 Subsystem-ID */ 76 #define PCI_CLASSCODE_GENWQE5_SRIOV 0x1200 /* UNKNOWN */ 77 78 #define GENWQE_SLU_ARCH_REQ 2 /* Required SLU architecture level */ 79 80 /** 81 * struct genwqe_reg - Genwqe data dump functionality 82 */ 83 struct genwqe_reg { 84 u32 addr; 85 u32 idx; 86 u64 val; 87 }; 88 89 /* 90 * enum genwqe_dbg_type - Specify chip unit to dump/debug 91 */ 92 enum genwqe_dbg_type { 93 GENWQE_DBG_UNIT0 = 0, /* captured before prev errs cleared */ 94 GENWQE_DBG_UNIT1 = 1, 95 GENWQE_DBG_UNIT2 = 2, 96 GENWQE_DBG_UNIT3 = 3, 97 GENWQE_DBG_UNIT4 = 4, 98 GENWQE_DBG_UNIT5 = 5, 99 GENWQE_DBG_UNIT6 = 6, 100 GENWQE_DBG_UNIT7 = 7, 101 GENWQE_DBG_REGS = 8, 102 GENWQE_DBG_DMA = 9, 103 GENWQE_DBG_UNITS = 10, /* max number of possible debug units */ 104 }; 105 106 /* Software error injection to simulate card failures */ 107 #define GENWQE_INJECT_HARDWARE_FAILURE 0x00000001 /* injects -1 reg reads */ 108 #define GENWQE_INJECT_BUS_RESET_FAILURE 0x00000002 /* pci_bus_reset fail */ 109 #define GENWQE_INJECT_GFIR_FATAL 0x00000004 /* GFIR = 0x0000ffff */ 110 #define GENWQE_INJECT_GFIR_INFO 0x00000008 /* GFIR = 0xffff0000 */ 111 112 /* 113 * Genwqe card description and management data. 114 * 115 * Error-handling in case of card malfunction 116 * ------------------------------------------ 117 * 118 * If the card is detected to be defective the outside environment 119 * will cause the PCI layer to call deinit (the cleanup function for 120 * probe). This is the same effect like doing a unbind/bind operation 121 * on the card. 122 * 123 * The genwqe card driver implements a health checking thread which 124 * verifies the card function. If this detects a problem the cards 125 * device is being shutdown and restarted again, along with a reset of 126 * the card and queue. 127 * 128 * All functions accessing the card device return either -EIO or -ENODEV 129 * code to indicate the malfunction to the user. The user has to close 130 * the file descriptor and open a new one, once the card becomes 131 * available again. 132 * 133 * If the open file descriptor is setup to receive SIGIO, the signal is 134 * genereated for the application which has to provide a handler to 135 * react on it. If the application does not close the open 136 * file descriptor a SIGKILL is send to enforce freeing the cards 137 * resources. 138 * 139 * I did not find a different way to prevent kernel problems due to 140 * reference counters for the cards character devices getting out of 141 * sync. The character device deallocation does not block, even if 142 * there is still an open file descriptor pending. If this pending 143 * descriptor is closed, the data structures used by the character 144 * device is reinstantiated, which will lead to the reference counter 145 * dropping below the allowed values. 146 * 147 * Card recovery 148 * ------------- 149 * 150 * To test the internal driver recovery the following command can be used: 151 * sudo sh -c 'echo 0xfffff > /sys/class/genwqe/genwqe0_card/err_inject' 152 */ 153 154 155 /** 156 * struct dma_mapping_type - Mapping type definition 157 * 158 * To avoid memcpying data arround we use user memory directly. To do 159 * this we need to pin/swap-in the memory and request a DMA address 160 * for it. 161 */ 162 enum dma_mapping_type { 163 GENWQE_MAPPING_RAW = 0, /* contignous memory buffer */ 164 GENWQE_MAPPING_SGL_TEMP, /* sglist dynamically used */ 165 GENWQE_MAPPING_SGL_PINNED, /* sglist used with pinning */ 166 }; 167 168 /** 169 * struct dma_mapping - Information about memory mappings done by the driver 170 */ 171 struct dma_mapping { 172 enum dma_mapping_type type; 173 174 void *u_vaddr; /* user-space vaddr/non-aligned */ 175 void *k_vaddr; /* kernel-space vaddr/non-aligned */ 176 dma_addr_t dma_addr; /* physical DMA address */ 177 178 struct page **page_list; /* list of pages used by user buff */ 179 dma_addr_t *dma_list; /* list of dma addresses per page */ 180 unsigned int nr_pages; /* number of pages */ 181 unsigned int size; /* size in bytes */ 182 183 struct list_head card_list; /* list of usr_maps for card */ 184 struct list_head pin_list; /* list of pinned memory for dev */ 185 }; 186 187 static inline void genwqe_mapping_init(struct dma_mapping *m, 188 enum dma_mapping_type type) 189 { 190 memset(m, 0, sizeof(*m)); 191 m->type = type; 192 } 193 194 /** 195 * struct ddcb_queue - DDCB queue data 196 * @ddcb_max: Number of DDCBs on the queue 197 * @ddcb_next: Next free DDCB 198 * @ddcb_act: Next DDCB supposed to finish 199 * @ddcb_seq: Sequence number of last DDCB 200 * @ddcbs_in_flight: Currently enqueued DDCBs 201 * @ddcbs_completed: Number of already completed DDCBs 202 * @return_on_busy: Number of -EBUSY returns on full queue 203 * @wait_on_busy: Number of waits on full queue 204 * @ddcb_daddr: DMA address of first DDCB in the queue 205 * @ddcb_vaddr: Kernel virtual address of first DDCB in the queue 206 * @ddcb_req: Associated requests (one per DDCB) 207 * @ddcb_waitqs: Associated wait queues (one per DDCB) 208 * @ddcb_lock: Lock to protect queuing operations 209 * @ddcb_waitq: Wait on next DDCB finishing 210 */ 211 212 struct ddcb_queue { 213 int ddcb_max; /* amount of DDCBs */ 214 int ddcb_next; /* next available DDCB num */ 215 int ddcb_act; /* DDCB to be processed */ 216 u16 ddcb_seq; /* slc seq num */ 217 unsigned int ddcbs_in_flight; /* number of ddcbs in processing */ 218 unsigned int ddcbs_completed; 219 unsigned int ddcbs_max_in_flight; 220 unsigned int return_on_busy; /* how many times -EBUSY? */ 221 unsigned int wait_on_busy; 222 223 dma_addr_t ddcb_daddr; /* DMA address */ 224 struct ddcb *ddcb_vaddr; /* kernel virtual addr for DDCBs */ 225 struct ddcb_requ **ddcb_req; /* ddcb processing parameter */ 226 wait_queue_head_t *ddcb_waitqs; /* waitqueue per ddcb */ 227 228 spinlock_t ddcb_lock; /* exclusive access to queue */ 229 wait_queue_head_t busy_waitq; /* wait for ddcb processing */ 230 231 /* registers or the respective queue to be used */ 232 u32 IO_QUEUE_CONFIG; 233 u32 IO_QUEUE_STATUS; 234 u32 IO_QUEUE_SEGMENT; 235 u32 IO_QUEUE_INITSQN; 236 u32 IO_QUEUE_WRAP; 237 u32 IO_QUEUE_OFFSET; 238 u32 IO_QUEUE_WTIME; 239 u32 IO_QUEUE_ERRCNTS; 240 u32 IO_QUEUE_LRW; 241 }; 242 243 /* 244 * GFIR, SLU_UNITCFG, APP_UNITCFG 245 * 8 Units with FIR/FEC + 64 * 2ndary FIRS/FEC. 246 */ 247 #define GENWQE_FFDC_REGS (3 + (8 * (2 + 2 * 64))) 248 249 struct genwqe_ffdc { 250 unsigned int entries; 251 struct genwqe_reg *regs; 252 }; 253 254 /** 255 * struct genwqe_dev - GenWQE device information 256 * @card_state: Card operation state, see above 257 * @ffdc: First Failure Data Capture buffers for each unit 258 * @card_thread: Working thread to operate the DDCB queue 259 * @card_waitq: Wait queue used in card_thread 260 * @queue: DDCB queue 261 * @health_thread: Card monitoring thread (only for PFs) 262 * @health_waitq: Wait queue used in health_thread 263 * @pci_dev: Associated PCI device (function) 264 * @mmio: Base address of 64-bit register space 265 * @mmio_len: Length of register area 266 * @file_lock: Lock to protect access to file_list 267 * @file_list: List of all processes with open GenWQE file descriptors 268 * 269 * This struct contains all information needed to communicate with a 270 * GenWQE card. It is initialized when a GenWQE device is found and 271 * destroyed when it goes away. It holds data to maintain the queue as 272 * well as data needed to feed the user interfaces. 273 */ 274 struct genwqe_dev { 275 enum genwqe_card_state card_state; 276 spinlock_t print_lock; 277 278 int card_idx; /* card index 0..CARD_NO_MAX-1 */ 279 u64 flags; /* general flags */ 280 281 /* FFDC data gathering */ 282 struct genwqe_ffdc ffdc[GENWQE_DBG_UNITS]; 283 284 /* DDCB workqueue */ 285 struct task_struct *card_thread; 286 wait_queue_head_t queue_waitq; 287 struct ddcb_queue queue; /* genwqe DDCB queue */ 288 unsigned int irqs_processed; 289 290 /* Card health checking thread */ 291 struct task_struct *health_thread; 292 wait_queue_head_t health_waitq; 293 294 int use_platform_recovery; /* use platform recovery mechanisms */ 295 296 /* char device */ 297 dev_t devnum_genwqe; /* major/minor num card */ 298 struct class *class_genwqe; /* reference to class object */ 299 struct device *dev; /* for device creation */ 300 struct cdev cdev_genwqe; /* char device for card */ 301 302 struct dentry *debugfs_root; /* debugfs card root directory */ 303 struct dentry *debugfs_genwqe; /* debugfs driver root directory */ 304 305 /* pci resources */ 306 struct pci_dev *pci_dev; /* PCI device */ 307 void __iomem *mmio; /* BAR-0 MMIO start */ 308 unsigned long mmio_len; 309 int num_vfs; 310 u32 vf_jobtimeout_msec[GENWQE_MAX_VFS]; 311 int is_privileged; /* access to all regs possible */ 312 313 /* config regs which we need often */ 314 u64 slu_unitcfg; 315 u64 app_unitcfg; 316 u64 softreset; 317 u64 err_inject; 318 u64 last_gfir; 319 char app_name[5]; 320 321 spinlock_t file_lock; /* lock for open files */ 322 struct list_head file_list; /* list of open files */ 323 324 /* debugfs parameters */ 325 int ddcb_software_timeout; /* wait until DDCB times out */ 326 int skip_recovery; /* circumvention if recovery fails */ 327 int kill_timeout; /* wait after sending SIGKILL */ 328 }; 329 330 /** 331 * enum genwqe_requ_state - State of a DDCB execution request 332 */ 333 enum genwqe_requ_state { 334 GENWQE_REQU_NEW = 0, 335 GENWQE_REQU_ENQUEUED = 1, 336 GENWQE_REQU_TAPPED = 2, 337 GENWQE_REQU_FINISHED = 3, 338 GENWQE_REQU_STATE_MAX, 339 }; 340 341 /** 342 * struct genwqe_sgl - Scatter gather list describing user-space memory 343 * @sgl: scatter gather list needs to be 128 byte aligned 344 * @sgl_dma_addr: dma address of sgl 345 * @sgl_size: size of area used for sgl 346 * @user_addr: user-space address of memory area 347 * @user_size: size of user-space memory area 348 * @page: buffer for partial pages if needed 349 * @page_dma_addr: dma address partial pages 350 */ 351 struct genwqe_sgl { 352 dma_addr_t sgl_dma_addr; 353 struct sg_entry *sgl; 354 size_t sgl_size; /* size of sgl */ 355 356 void __user *user_addr; /* user-space base-address */ 357 size_t user_size; /* size of memory area */ 358 359 unsigned long nr_pages; 360 unsigned long fpage_offs; 361 size_t fpage_size; 362 size_t lpage_size; 363 364 void *fpage; 365 dma_addr_t fpage_dma_addr; 366 367 void *lpage; 368 dma_addr_t lpage_dma_addr; 369 }; 370 371 int genwqe_alloc_sync_sgl(struct genwqe_dev *cd, struct genwqe_sgl *sgl, 372 void __user *user_addr, size_t user_size); 373 374 int genwqe_setup_sgl(struct genwqe_dev *cd, struct genwqe_sgl *sgl, 375 dma_addr_t *dma_list); 376 377 int genwqe_free_sync_sgl(struct genwqe_dev *cd, struct genwqe_sgl *sgl); 378 379 /** 380 * struct ddcb_requ - Kernel internal representation of the DDCB request 381 * @cmd: User space representation of the DDCB execution request 382 */ 383 struct ddcb_requ { 384 /* kernel specific content */ 385 enum genwqe_requ_state req_state; /* request status */ 386 int num; /* ddcb_no for this request */ 387 struct ddcb_queue *queue; /* associated queue */ 388 389 struct dma_mapping dma_mappings[DDCB_FIXUPS]; 390 struct genwqe_sgl sgls[DDCB_FIXUPS]; 391 392 /* kernel/user shared content */ 393 struct genwqe_ddcb_cmd cmd; /* ddcb_no for this request */ 394 struct genwqe_debug_data debug_data; 395 }; 396 397 /** 398 * struct genwqe_file - Information for open GenWQE devices 399 */ 400 struct genwqe_file { 401 struct genwqe_dev *cd; 402 struct genwqe_driver *client; 403 struct file *filp; 404 405 struct fasync_struct *async_queue; 406 struct task_struct *owner; 407 struct list_head list; /* entry in list of open files */ 408 409 spinlock_t map_lock; /* lock for dma_mappings */ 410 struct list_head map_list; /* list of dma_mappings */ 411 412 spinlock_t pin_lock; /* lock for pinned memory */ 413 struct list_head pin_list; /* list of pinned memory */ 414 }; 415 416 int genwqe_setup_service_layer(struct genwqe_dev *cd); /* for PF only */ 417 int genwqe_finish_queue(struct genwqe_dev *cd); 418 int genwqe_release_service_layer(struct genwqe_dev *cd); 419 420 /** 421 * genwqe_get_slu_id() - Read Service Layer Unit Id 422 * Return: 0x00: Development code 423 * 0x01: SLC1 (old) 424 * 0x02: SLC2 (sept2012) 425 * 0x03: SLC2 (feb2013, generic driver) 426 */ 427 static inline int genwqe_get_slu_id(struct genwqe_dev *cd) 428 { 429 return (int)((cd->slu_unitcfg >> 32) & 0xff); 430 } 431 432 int genwqe_ddcbs_in_flight(struct genwqe_dev *cd); 433 434 u8 genwqe_card_type(struct genwqe_dev *cd); 435 int genwqe_card_reset(struct genwqe_dev *cd); 436 int genwqe_set_interrupt_capability(struct genwqe_dev *cd, int count); 437 void genwqe_reset_interrupt_capability(struct genwqe_dev *cd); 438 439 int genwqe_device_create(struct genwqe_dev *cd); 440 int genwqe_device_remove(struct genwqe_dev *cd); 441 442 /* debugfs */ 443 int genwqe_init_debugfs(struct genwqe_dev *cd); 444 void genqwe_exit_debugfs(struct genwqe_dev *cd); 445 446 int genwqe_read_softreset(struct genwqe_dev *cd); 447 448 /* Hardware Circumventions */ 449 int genwqe_recovery_on_fatal_gfir_required(struct genwqe_dev *cd); 450 int genwqe_flash_readback_fails(struct genwqe_dev *cd); 451 452 /** 453 * genwqe_write_vreg() - Write register in VF window 454 * @cd: genwqe device 455 * @reg: register address 456 * @val: value to write 457 * @func: 0: PF, 1: VF0, ..., 15: VF14 458 */ 459 int genwqe_write_vreg(struct genwqe_dev *cd, u32 reg, u64 val, int func); 460 461 /** 462 * genwqe_read_vreg() - Read register in VF window 463 * @cd: genwqe device 464 * @reg: register address 465 * @func: 0: PF, 1: VF0, ..., 15: VF14 466 * 467 * Return: content of the register 468 */ 469 u64 genwqe_read_vreg(struct genwqe_dev *cd, u32 reg, int func); 470 471 /* FFDC Buffer Management */ 472 int genwqe_ffdc_buff_size(struct genwqe_dev *cd, int unit_id); 473 int genwqe_ffdc_buff_read(struct genwqe_dev *cd, int unit_id, 474 struct genwqe_reg *regs, unsigned int max_regs); 475 int genwqe_read_ffdc_regs(struct genwqe_dev *cd, struct genwqe_reg *regs, 476 unsigned int max_regs, int all); 477 int genwqe_ffdc_dump_dma(struct genwqe_dev *cd, 478 struct genwqe_reg *regs, unsigned int max_regs); 479 480 int genwqe_init_debug_data(struct genwqe_dev *cd, 481 struct genwqe_debug_data *d); 482 483 void genwqe_init_crc32(void); 484 int genwqe_read_app_id(struct genwqe_dev *cd, char *app_name, int len); 485 486 /* Memory allocation/deallocation; dma address handling */ 487 int genwqe_user_vmap(struct genwqe_dev *cd, struct dma_mapping *m, 488 void *uaddr, unsigned long size, 489 struct ddcb_requ *req); 490 491 int genwqe_user_vunmap(struct genwqe_dev *cd, struct dma_mapping *m, 492 struct ddcb_requ *req); 493 494 static inline bool dma_mapping_used(struct dma_mapping *m) 495 { 496 if (!m) 497 return 0; 498 return m->size != 0; 499 } 500 501 /** 502 * __genwqe_execute_ddcb() - Execute DDCB request with addr translation 503 * 504 * This function will do the address translation changes to the DDCBs 505 * according to the definitions required by the ATS field. It looks up 506 * the memory allocation buffer or does vmap/vunmap for the respective 507 * user-space buffers, inclusive page pinning and scatter gather list 508 * buildup and teardown. 509 */ 510 int __genwqe_execute_ddcb(struct genwqe_dev *cd, 511 struct genwqe_ddcb_cmd *cmd, unsigned int f_flags); 512 513 /** 514 * __genwqe_execute_raw_ddcb() - Execute DDCB request without addr translation 515 * 516 * This version will not do address translation or any modification of 517 * the DDCB data. It is used e.g. for the MoveFlash DDCB which is 518 * entirely prepared by the driver itself. That means the appropriate 519 * DMA addresses are already in the DDCB and do not need any 520 * modification. 521 */ 522 int __genwqe_execute_raw_ddcb(struct genwqe_dev *cd, 523 struct genwqe_ddcb_cmd *cmd, 524 unsigned int f_flags); 525 int __genwqe_enqueue_ddcb(struct genwqe_dev *cd, 526 struct ddcb_requ *req, 527 unsigned int f_flags); 528 529 int __genwqe_wait_ddcb(struct genwqe_dev *cd, struct ddcb_requ *req); 530 int __genwqe_purge_ddcb(struct genwqe_dev *cd, struct ddcb_requ *req); 531 532 /* register access */ 533 int __genwqe_writeq(struct genwqe_dev *cd, u64 byte_offs, u64 val); 534 u64 __genwqe_readq(struct genwqe_dev *cd, u64 byte_offs); 535 int __genwqe_writel(struct genwqe_dev *cd, u64 byte_offs, u32 val); 536 u32 __genwqe_readl(struct genwqe_dev *cd, u64 byte_offs); 537 538 void *__genwqe_alloc_consistent(struct genwqe_dev *cd, size_t size, 539 dma_addr_t *dma_handle); 540 void __genwqe_free_consistent(struct genwqe_dev *cd, size_t size, 541 void *vaddr, dma_addr_t dma_handle); 542 543 /* Base clock frequency in MHz */ 544 int genwqe_base_clock_frequency(struct genwqe_dev *cd); 545 546 /* Before FFDC is captured the traps should be stopped. */ 547 void genwqe_stop_traps(struct genwqe_dev *cd); 548 void genwqe_start_traps(struct genwqe_dev *cd); 549 550 /* Hardware circumvention */ 551 bool genwqe_need_err_masking(struct genwqe_dev *cd); 552 553 /** 554 * genwqe_is_privileged() - Determine operation mode for PCI function 555 * 556 * On Intel with SRIOV support we see: 557 * PF: is_physfn = 1 is_virtfn = 0 558 * VF: is_physfn = 0 is_virtfn = 1 559 * 560 * On Systems with no SRIOV support _and_ virtualized systems we get: 561 * is_physfn = 0 is_virtfn = 0 562 * 563 * Other vendors have individual pci device ids to distinguish between 564 * virtual function drivers and physical function drivers. GenWQE 565 * unfortunately has just on pci device id for both, VFs and PF. 566 * 567 * The following code is used to distinguish if the card is running in 568 * privileged mode, either as true PF or in a virtualized system with 569 * full register access e.g. currently on PowerPC. 570 * 571 * if (pci_dev->is_virtfn) 572 * cd->is_privileged = 0; 573 * else 574 * cd->is_privileged = (__genwqe_readq(cd, IO_SLU_BITSTREAM) 575 * != IO_ILLEGAL_VALUE); 576 */ 577 static inline int genwqe_is_privileged(struct genwqe_dev *cd) 578 { 579 return cd->is_privileged; 580 } 581 582 #endif /* __CARD_BASE_H__ */ 583