1 #ifndef __CARD_BASE_H__ 2 #define __CARD_BASE_H__ 3 4 /** 5 * IBM Accelerator Family 'GenWQE' 6 * 7 * (C) Copyright IBM Corp. 2013 8 * 9 * Author: Frank Haverkamp <haver@linux.vnet.ibm.com> 10 * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com> 11 * Author: Michael Jung <mijung@de.ibm.com> 12 * Author: Michael Ruettger <michael@ibmra.de> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License (version 2 only) 16 * as published by the Free Software Foundation. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 */ 23 24 /* 25 * Interfaces within the GenWQE module. Defines genwqe_card and 26 * ddcb_queue as well as ddcb_requ. 27 */ 28 29 #include <linux/kernel.h> 30 #include <linux/types.h> 31 #include <linux/cdev.h> 32 #include <linux/stringify.h> 33 #include <linux/pci.h> 34 #include <linux/semaphore.h> 35 #include <linux/uaccess.h> 36 #include <linux/io.h> 37 #include <linux/version.h> 38 #include <linux/debugfs.h> 39 40 #include <linux/genwqe/genwqe_card.h> 41 #include "genwqe_driver.h" 42 43 #define GENWQE_MSI_IRQS 4 /* Just one supported, no MSIx */ 44 #define GENWQE_FLAG_MSI_ENABLED (1 << 0) 45 46 #define GENWQE_MAX_VFS 15 /* maximum 15 VFs are possible */ 47 #define GENWQE_MAX_FUNCS 16 /* 1 PF and 15 VFs */ 48 #define GENWQE_CARD_NO_MAX (16 * GENWQE_MAX_FUNCS) 49 50 /* Compile parameters, some of them appear in debugfs for later adjustment */ 51 #define genwqe_ddcb_max 32 /* DDCBs on the work-queue */ 52 #define genwqe_polling_enabled 0 /* in case of irqs not working */ 53 #define genwqe_ddcb_software_timeout 10 /* timeout per DDCB in seconds */ 54 #define genwqe_kill_timeout 8 /* time until process gets killed */ 55 #define genwqe_vf_jobtimeout_msec 250 /* 250 msec */ 56 #define genwqe_pf_jobtimeout_msec 8000 /* 8 sec should be ok */ 57 #define genwqe_health_check_interval 4 /* <= 0: disabled */ 58 59 /* Sysfs attribute groups used when we create the genwqe device */ 60 extern const struct attribute_group *genwqe_attribute_groups[]; 61 62 /* 63 * Config space for Genwqe5 A7: 64 * 00:[14 10 4b 04]40 00 10 00[00 00 00 12]00 00 00 00 65 * 10: 0c 00 00 f0 07 3c 00 00 00 00 00 00 00 00 00 00 66 * 20: 00 00 00 00 00 00 00 00 00 00 00 00[14 10 4b 04] 67 * 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 00 00 00 68 */ 69 #define PCI_DEVICE_GENWQE 0x044b /* Genwqe DeviceID */ 70 71 #define PCI_SUBSYSTEM_ID_GENWQE5 0x035f /* Genwqe A5 Subsystem-ID */ 72 #define PCI_SUBSYSTEM_ID_GENWQE5_NEW 0x044b /* Genwqe A5 Subsystem-ID */ 73 #define PCI_CLASSCODE_GENWQE5 0x1200 /* UNKNOWN */ 74 75 #define PCI_SUBVENDOR_ID_IBM_SRIOV 0x0000 76 #define PCI_SUBSYSTEM_ID_GENWQE5_SRIOV 0x0000 /* Genwqe A5 Subsystem-ID */ 77 #define PCI_CLASSCODE_GENWQE5_SRIOV 0x1200 /* UNKNOWN */ 78 79 #define GENWQE_SLU_ARCH_REQ 2 /* Required SLU architecture level */ 80 81 /** 82 * struct genwqe_reg - Genwqe data dump functionality 83 */ 84 struct genwqe_reg { 85 u32 addr; 86 u32 idx; 87 u64 val; 88 }; 89 90 /* 91 * enum genwqe_dbg_type - Specify chip unit to dump/debug 92 */ 93 enum genwqe_dbg_type { 94 GENWQE_DBG_UNIT0 = 0, /* captured before prev errs cleared */ 95 GENWQE_DBG_UNIT1 = 1, 96 GENWQE_DBG_UNIT2 = 2, 97 GENWQE_DBG_UNIT3 = 3, 98 GENWQE_DBG_UNIT4 = 4, 99 GENWQE_DBG_UNIT5 = 5, 100 GENWQE_DBG_UNIT6 = 6, 101 GENWQE_DBG_UNIT7 = 7, 102 GENWQE_DBG_REGS = 8, 103 GENWQE_DBG_DMA = 9, 104 GENWQE_DBG_UNITS = 10, /* max number of possible debug units */ 105 }; 106 107 /* Software error injection to simulate card failures */ 108 #define GENWQE_INJECT_HARDWARE_FAILURE 0x00000001 /* injects -1 reg reads */ 109 #define GENWQE_INJECT_BUS_RESET_FAILURE 0x00000002 /* pci_bus_reset fail */ 110 #define GENWQE_INJECT_GFIR_FATAL 0x00000004 /* GFIR = 0x0000ffff */ 111 #define GENWQE_INJECT_GFIR_INFO 0x00000008 /* GFIR = 0xffff0000 */ 112 113 /* 114 * Genwqe card description and management data. 115 * 116 * Error-handling in case of card malfunction 117 * ------------------------------------------ 118 * 119 * If the card is detected to be defective the outside environment 120 * will cause the PCI layer to call deinit (the cleanup function for 121 * probe). This is the same effect like doing a unbind/bind operation 122 * on the card. 123 * 124 * The genwqe card driver implements a health checking thread which 125 * verifies the card function. If this detects a problem the cards 126 * device is being shutdown and restarted again, along with a reset of 127 * the card and queue. 128 * 129 * All functions accessing the card device return either -EIO or -ENODEV 130 * code to indicate the malfunction to the user. The user has to close 131 * the file descriptor and open a new one, once the card becomes 132 * available again. 133 * 134 * If the open file descriptor is setup to receive SIGIO, the signal is 135 * genereated for the application which has to provide a handler to 136 * react on it. If the application does not close the open 137 * file descriptor a SIGKILL is send to enforce freeing the cards 138 * resources. 139 * 140 * I did not find a different way to prevent kernel problems due to 141 * reference counters for the cards character devices getting out of 142 * sync. The character device deallocation does not block, even if 143 * there is still an open file descriptor pending. If this pending 144 * descriptor is closed, the data structures used by the character 145 * device is reinstantiated, which will lead to the reference counter 146 * dropping below the allowed values. 147 * 148 * Card recovery 149 * ------------- 150 * 151 * To test the internal driver recovery the following command can be used: 152 * sudo sh -c 'echo 0xfffff > /sys/class/genwqe/genwqe0_card/err_inject' 153 */ 154 155 156 /** 157 * struct dma_mapping_type - Mapping type definition 158 * 159 * To avoid memcpying data arround we use user memory directly. To do 160 * this we need to pin/swap-in the memory and request a DMA address 161 * for it. 162 */ 163 enum dma_mapping_type { 164 GENWQE_MAPPING_RAW = 0, /* contignous memory buffer */ 165 GENWQE_MAPPING_SGL_TEMP, /* sglist dynamically used */ 166 GENWQE_MAPPING_SGL_PINNED, /* sglist used with pinning */ 167 }; 168 169 /** 170 * struct dma_mapping - Information about memory mappings done by the driver 171 */ 172 struct dma_mapping { 173 enum dma_mapping_type type; 174 175 void *u_vaddr; /* user-space vaddr/non-aligned */ 176 void *k_vaddr; /* kernel-space vaddr/non-aligned */ 177 dma_addr_t dma_addr; /* physical DMA address */ 178 179 struct page **page_list; /* list of pages used by user buff */ 180 dma_addr_t *dma_list; /* list of dma addresses per page */ 181 unsigned int nr_pages; /* number of pages */ 182 unsigned int size; /* size in bytes */ 183 184 struct list_head card_list; /* list of usr_maps for card */ 185 struct list_head pin_list; /* list of pinned memory for dev */ 186 }; 187 188 static inline void genwqe_mapping_init(struct dma_mapping *m, 189 enum dma_mapping_type type) 190 { 191 memset(m, 0, sizeof(*m)); 192 m->type = type; 193 } 194 195 /** 196 * struct ddcb_queue - DDCB queue data 197 * @ddcb_max: Number of DDCBs on the queue 198 * @ddcb_next: Next free DDCB 199 * @ddcb_act: Next DDCB supposed to finish 200 * @ddcb_seq: Sequence number of last DDCB 201 * @ddcbs_in_flight: Currently enqueued DDCBs 202 * @ddcbs_completed: Number of already completed DDCBs 203 * @busy: Number of -EBUSY returns 204 * @ddcb_daddr: DMA address of first DDCB in the queue 205 * @ddcb_vaddr: Kernel virtual address of first DDCB in the queue 206 * @ddcb_req: Associated requests (one per DDCB) 207 * @ddcb_waitqs: Associated wait queues (one per DDCB) 208 * @ddcb_lock: Lock to protect queuing operations 209 * @ddcb_waitq: Wait on next DDCB finishing 210 */ 211 212 struct ddcb_queue { 213 int ddcb_max; /* amount of DDCBs */ 214 int ddcb_next; /* next available DDCB num */ 215 int ddcb_act; /* DDCB to be processed */ 216 u16 ddcb_seq; /* slc seq num */ 217 unsigned int ddcbs_in_flight; /* number of ddcbs in processing */ 218 unsigned int ddcbs_completed; 219 unsigned int ddcbs_max_in_flight; 220 unsigned int busy; /* how many times -EBUSY? */ 221 222 dma_addr_t ddcb_daddr; /* DMA address */ 223 struct ddcb *ddcb_vaddr; /* kernel virtual addr for DDCBs */ 224 struct ddcb_requ **ddcb_req; /* ddcb processing parameter */ 225 wait_queue_head_t *ddcb_waitqs; /* waitqueue per ddcb */ 226 227 spinlock_t ddcb_lock; /* exclusive access to queue */ 228 wait_queue_head_t ddcb_waitq; /* wait for ddcb processing */ 229 230 /* registers or the respective queue to be used */ 231 u32 IO_QUEUE_CONFIG; 232 u32 IO_QUEUE_STATUS; 233 u32 IO_QUEUE_SEGMENT; 234 u32 IO_QUEUE_INITSQN; 235 u32 IO_QUEUE_WRAP; 236 u32 IO_QUEUE_OFFSET; 237 u32 IO_QUEUE_WTIME; 238 u32 IO_QUEUE_ERRCNTS; 239 u32 IO_QUEUE_LRW; 240 }; 241 242 /* 243 * GFIR, SLU_UNITCFG, APP_UNITCFG 244 * 8 Units with FIR/FEC + 64 * 2ndary FIRS/FEC. 245 */ 246 #define GENWQE_FFDC_REGS (3 + (8 * (2 + 2 * 64))) 247 248 struct genwqe_ffdc { 249 unsigned int entries; 250 struct genwqe_reg *regs; 251 }; 252 253 /** 254 * struct genwqe_dev - GenWQE device information 255 * @card_state: Card operation state, see above 256 * @ffdc: First Failure Data Capture buffers for each unit 257 * @card_thread: Working thread to operate the DDCB queue 258 * @card_waitq: Wait queue used in card_thread 259 * @queue: DDCB queue 260 * @health_thread: Card monitoring thread (only for PFs) 261 * @health_waitq: Wait queue used in health_thread 262 * @pci_dev: Associated PCI device (function) 263 * @mmio: Base address of 64-bit register space 264 * @mmio_len: Length of register area 265 * @file_lock: Lock to protect access to file_list 266 * @file_list: List of all processes with open GenWQE file descriptors 267 * 268 * This struct contains all information needed to communicate with a 269 * GenWQE card. It is initialized when a GenWQE device is found and 270 * destroyed when it goes away. It holds data to maintain the queue as 271 * well as data needed to feed the user interfaces. 272 */ 273 struct genwqe_dev { 274 enum genwqe_card_state card_state; 275 spinlock_t print_lock; 276 277 int card_idx; /* card index 0..CARD_NO_MAX-1 */ 278 u64 flags; /* general flags */ 279 280 /* FFDC data gathering */ 281 struct genwqe_ffdc ffdc[GENWQE_DBG_UNITS]; 282 283 /* DDCB workqueue */ 284 struct task_struct *card_thread; 285 wait_queue_head_t queue_waitq; 286 struct ddcb_queue queue; /* genwqe DDCB queue */ 287 unsigned int irqs_processed; 288 289 /* Card health checking thread */ 290 struct task_struct *health_thread; 291 wait_queue_head_t health_waitq; 292 293 /* char device */ 294 dev_t devnum_genwqe; /* major/minor num card */ 295 struct class *class_genwqe; /* reference to class object */ 296 struct device *dev; /* for device creation */ 297 struct cdev cdev_genwqe; /* char device for card */ 298 299 struct dentry *debugfs_root; /* debugfs card root directory */ 300 struct dentry *debugfs_genwqe; /* debugfs driver root directory */ 301 302 /* pci resources */ 303 struct pci_dev *pci_dev; /* PCI device */ 304 void __iomem *mmio; /* BAR-0 MMIO start */ 305 unsigned long mmio_len; 306 u16 num_vfs; 307 u32 vf_jobtimeout_msec[GENWQE_MAX_VFS]; 308 int is_privileged; /* access to all regs possible */ 309 310 /* config regs which we need often */ 311 u64 slu_unitcfg; 312 u64 app_unitcfg; 313 u64 softreset; 314 u64 err_inject; 315 u64 last_gfir; 316 char app_name[5]; 317 318 spinlock_t file_lock; /* lock for open files */ 319 struct list_head file_list; /* list of open files */ 320 321 /* debugfs parameters */ 322 int ddcb_software_timeout; /* wait until DDCB times out */ 323 int skip_recovery; /* circumvention if recovery fails */ 324 int kill_timeout; /* wait after sending SIGKILL */ 325 }; 326 327 /** 328 * enum genwqe_requ_state - State of a DDCB execution request 329 */ 330 enum genwqe_requ_state { 331 GENWQE_REQU_NEW = 0, 332 GENWQE_REQU_ENQUEUED = 1, 333 GENWQE_REQU_TAPPED = 2, 334 GENWQE_REQU_FINISHED = 3, 335 GENWQE_REQU_STATE_MAX, 336 }; 337 338 /** 339 * struct ddcb_requ - Kernel internal representation of the DDCB request 340 * @cmd: User space representation of the DDCB execution request 341 */ 342 struct ddcb_requ { 343 /* kernel specific content */ 344 enum genwqe_requ_state req_state; /* request status */ 345 int num; /* ddcb_no for this request */ 346 struct ddcb_queue *queue; /* associated queue */ 347 348 struct dma_mapping dma_mappings[DDCB_FIXUPS]; 349 struct sg_entry *sgl[DDCB_FIXUPS]; 350 dma_addr_t sgl_dma_addr[DDCB_FIXUPS]; 351 size_t sgl_size[DDCB_FIXUPS]; 352 353 /* kernel/user shared content */ 354 struct genwqe_ddcb_cmd cmd; /* ddcb_no for this request */ 355 struct genwqe_debug_data debug_data; 356 }; 357 358 /** 359 * struct genwqe_file - Information for open GenWQE devices 360 */ 361 struct genwqe_file { 362 struct genwqe_dev *cd; 363 struct genwqe_driver *client; 364 struct file *filp; 365 366 struct fasync_struct *async_queue; 367 struct task_struct *owner; 368 struct list_head list; /* entry in list of open files */ 369 370 spinlock_t map_lock; /* lock for dma_mappings */ 371 struct list_head map_list; /* list of dma_mappings */ 372 373 spinlock_t pin_lock; /* lock for pinned memory */ 374 struct list_head pin_list; /* list of pinned memory */ 375 }; 376 377 int genwqe_setup_service_layer(struct genwqe_dev *cd); /* for PF only */ 378 int genwqe_finish_queue(struct genwqe_dev *cd); 379 int genwqe_release_service_layer(struct genwqe_dev *cd); 380 381 /** 382 * genwqe_get_slu_id() - Read Service Layer Unit Id 383 * Return: 0x00: Development code 384 * 0x01: SLC1 (old) 385 * 0x02: SLC2 (sept2012) 386 * 0x03: SLC2 (feb2013, generic driver) 387 */ 388 static inline int genwqe_get_slu_id(struct genwqe_dev *cd) 389 { 390 return (int)((cd->slu_unitcfg >> 32) & 0xff); 391 } 392 393 int genwqe_ddcbs_in_flight(struct genwqe_dev *cd); 394 395 u8 genwqe_card_type(struct genwqe_dev *cd); 396 int genwqe_card_reset(struct genwqe_dev *cd); 397 int genwqe_set_interrupt_capability(struct genwqe_dev *cd, int count); 398 void genwqe_reset_interrupt_capability(struct genwqe_dev *cd); 399 400 int genwqe_device_create(struct genwqe_dev *cd); 401 int genwqe_device_remove(struct genwqe_dev *cd); 402 403 /* debugfs */ 404 int genwqe_init_debugfs(struct genwqe_dev *cd); 405 void genqwe_exit_debugfs(struct genwqe_dev *cd); 406 407 int genwqe_read_softreset(struct genwqe_dev *cd); 408 409 /* Hardware Circumventions */ 410 int genwqe_recovery_on_fatal_gfir_required(struct genwqe_dev *cd); 411 int genwqe_flash_readback_fails(struct genwqe_dev *cd); 412 413 /** 414 * genwqe_write_vreg() - Write register in VF window 415 * @cd: genwqe device 416 * @reg: register address 417 * @val: value to write 418 * @func: 0: PF, 1: VF0, ..., 15: VF14 419 */ 420 int genwqe_write_vreg(struct genwqe_dev *cd, u32 reg, u64 val, int func); 421 422 /** 423 * genwqe_read_vreg() - Read register in VF window 424 * @cd: genwqe device 425 * @reg: register address 426 * @func: 0: PF, 1: VF0, ..., 15: VF14 427 * 428 * Return: content of the register 429 */ 430 u64 genwqe_read_vreg(struct genwqe_dev *cd, u32 reg, int func); 431 432 /* FFDC Buffer Management */ 433 int genwqe_ffdc_buff_size(struct genwqe_dev *cd, int unit_id); 434 int genwqe_ffdc_buff_read(struct genwqe_dev *cd, int unit_id, 435 struct genwqe_reg *regs, unsigned int max_regs); 436 int genwqe_read_ffdc_regs(struct genwqe_dev *cd, struct genwqe_reg *regs, 437 unsigned int max_regs, int all); 438 int genwqe_ffdc_dump_dma(struct genwqe_dev *cd, 439 struct genwqe_reg *regs, unsigned int max_regs); 440 441 int genwqe_init_debug_data(struct genwqe_dev *cd, 442 struct genwqe_debug_data *d); 443 444 void genwqe_init_crc32(void); 445 int genwqe_read_app_id(struct genwqe_dev *cd, char *app_name, int len); 446 447 /* Memory allocation/deallocation; dma address handling */ 448 int genwqe_user_vmap(struct genwqe_dev *cd, struct dma_mapping *m, 449 void *uaddr, unsigned long size, 450 struct ddcb_requ *req); 451 452 int genwqe_user_vunmap(struct genwqe_dev *cd, struct dma_mapping *m, 453 struct ddcb_requ *req); 454 455 struct sg_entry *genwqe_alloc_sgl(struct genwqe_dev *cd, int num_pages, 456 dma_addr_t *dma_addr, size_t *sgl_size); 457 458 void genwqe_free_sgl(struct genwqe_dev *cd, struct sg_entry *sg_list, 459 dma_addr_t dma_addr, size_t size); 460 461 int genwqe_setup_sgl(struct genwqe_dev *cd, 462 unsigned long offs, 463 unsigned long size, 464 struct sg_entry *sgl, /* genwqe sgl */ 465 dma_addr_t dma_addr, size_t sgl_size, 466 dma_addr_t *dma_list, int page_offs, int num_pages); 467 468 int genwqe_check_sgl(struct genwqe_dev *cd, struct sg_entry *sg_list, 469 int size); 470 471 static inline bool dma_mapping_used(struct dma_mapping *m) 472 { 473 if (!m) 474 return 0; 475 return m->size != 0; 476 } 477 478 /** 479 * __genwqe_execute_ddcb() - Execute DDCB request with addr translation 480 * 481 * This function will do the address translation changes to the DDCBs 482 * according to the definitions required by the ATS field. It looks up 483 * the memory allocation buffer or does vmap/vunmap for the respective 484 * user-space buffers, inclusive page pinning and scatter gather list 485 * buildup and teardown. 486 */ 487 int __genwqe_execute_ddcb(struct genwqe_dev *cd, 488 struct genwqe_ddcb_cmd *cmd); 489 490 /** 491 * __genwqe_execute_raw_ddcb() - Execute DDCB request without addr translation 492 * 493 * This version will not do address translation or any modifcation of 494 * the DDCB data. It is used e.g. for the MoveFlash DDCB which is 495 * entirely prepared by the driver itself. That means the appropriate 496 * DMA addresses are already in the DDCB and do not need any 497 * modification. 498 */ 499 int __genwqe_execute_raw_ddcb(struct genwqe_dev *cd, 500 struct genwqe_ddcb_cmd *cmd); 501 502 int __genwqe_enqueue_ddcb(struct genwqe_dev *cd, struct ddcb_requ *req); 503 int __genwqe_wait_ddcb(struct genwqe_dev *cd, struct ddcb_requ *req); 504 int __genwqe_purge_ddcb(struct genwqe_dev *cd, struct ddcb_requ *req); 505 506 /* register access */ 507 int __genwqe_writeq(struct genwqe_dev *cd, u64 byte_offs, u64 val); 508 u64 __genwqe_readq(struct genwqe_dev *cd, u64 byte_offs); 509 int __genwqe_writel(struct genwqe_dev *cd, u64 byte_offs, u32 val); 510 u32 __genwqe_readl(struct genwqe_dev *cd, u64 byte_offs); 511 512 void *__genwqe_alloc_consistent(struct genwqe_dev *cd, size_t size, 513 dma_addr_t *dma_handle); 514 void __genwqe_free_consistent(struct genwqe_dev *cd, size_t size, 515 void *vaddr, dma_addr_t dma_handle); 516 517 /* Base clock frequency in MHz */ 518 int genwqe_base_clock_frequency(struct genwqe_dev *cd); 519 520 /* Before FFDC is captured the traps should be stopped. */ 521 void genwqe_stop_traps(struct genwqe_dev *cd); 522 void genwqe_start_traps(struct genwqe_dev *cd); 523 524 /* Hardware circumvention */ 525 bool genwqe_need_err_masking(struct genwqe_dev *cd); 526 527 /** 528 * genwqe_is_privileged() - Determine operation mode for PCI function 529 * 530 * On Intel with SRIOV support we see: 531 * PF: is_physfn = 1 is_virtfn = 0 532 * VF: is_physfn = 0 is_virtfn = 1 533 * 534 * On Systems with no SRIOV support _and_ virtualized systems we get: 535 * is_physfn = 0 is_virtfn = 0 536 * 537 * Other vendors have individual pci device ids to distinguish between 538 * virtual function drivers and physical function drivers. GenWQE 539 * unfortunately has just on pci device id for both, VFs and PF. 540 * 541 * The following code is used to distinguish if the card is running in 542 * privileged mode, either as true PF or in a virtualized system with 543 * full register access e.g. currently on PowerPC. 544 * 545 * if (pci_dev->is_virtfn) 546 * cd->is_privileged = 0; 547 * else 548 * cd->is_privileged = (__genwqe_readq(cd, IO_SLU_BITSTREAM) 549 * != IO_ILLEGAL_VALUE); 550 */ 551 static inline int genwqe_is_privileged(struct genwqe_dev *cd) 552 { 553 return cd->is_privileged; 554 } 555 556 #endif /* __CARD_BASE_H__ */ 557