1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for 93xx46 EEPROMs 4 * 5 * (C) 2011 DENX Software Engineering, Anatolij Gustschin <agust@denx.de> 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/device.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_gpio.h> 17 #include <linux/slab.h> 18 #include <linux/spi/spi.h> 19 #include <linux/nvmem-provider.h> 20 #include <linux/eeprom_93xx46.h> 21 22 #define OP_START 0x4 23 #define OP_WRITE (OP_START | 0x1) 24 #define OP_READ (OP_START | 0x2) 25 #define ADDR_EWDS 0x00 26 #define ADDR_ERAL 0x20 27 #define ADDR_EWEN 0x30 28 29 struct eeprom_93xx46_devtype_data { 30 unsigned int quirks; 31 }; 32 33 static const struct eeprom_93xx46_devtype_data atmel_at93c46d_data = { 34 .quirks = EEPROM_93XX46_QUIRK_SINGLE_WORD_READ | 35 EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH, 36 }; 37 38 static const struct eeprom_93xx46_devtype_data microchip_93lc46b_data = { 39 .quirks = EEPROM_93XX46_QUIRK_EXTRA_READ_CYCLE, 40 }; 41 42 struct eeprom_93xx46_dev { 43 struct spi_device *spi; 44 struct eeprom_93xx46_platform_data *pdata; 45 struct mutex lock; 46 struct nvmem_config nvmem_config; 47 struct nvmem_device *nvmem; 48 int addrlen; 49 int size; 50 }; 51 52 static inline bool has_quirk_single_word_read(struct eeprom_93xx46_dev *edev) 53 { 54 return edev->pdata->quirks & EEPROM_93XX46_QUIRK_SINGLE_WORD_READ; 55 } 56 57 static inline bool has_quirk_instruction_length(struct eeprom_93xx46_dev *edev) 58 { 59 return edev->pdata->quirks & EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH; 60 } 61 62 static inline bool has_quirk_extra_read_cycle(struct eeprom_93xx46_dev *edev) 63 { 64 return edev->pdata->quirks & EEPROM_93XX46_QUIRK_EXTRA_READ_CYCLE; 65 } 66 67 static int eeprom_93xx46_read(void *priv, unsigned int off, 68 void *val, size_t count) 69 { 70 struct eeprom_93xx46_dev *edev = priv; 71 char *buf = val; 72 int err = 0; 73 74 if (unlikely(off >= edev->size)) 75 return 0; 76 if ((off + count) > edev->size) 77 count = edev->size - off; 78 if (unlikely(!count)) 79 return count; 80 81 mutex_lock(&edev->lock); 82 83 if (edev->pdata->prepare) 84 edev->pdata->prepare(edev); 85 86 while (count) { 87 struct spi_message m; 88 struct spi_transfer t[2] = { { 0 } }; 89 u16 cmd_addr = OP_READ << edev->addrlen; 90 size_t nbytes = count; 91 int bits; 92 93 if (edev->addrlen == 7) { 94 cmd_addr |= off & 0x7f; 95 bits = 10; 96 if (has_quirk_single_word_read(edev)) 97 nbytes = 1; 98 } else { 99 cmd_addr |= (off >> 1) & 0x3f; 100 bits = 9; 101 if (has_quirk_single_word_read(edev)) 102 nbytes = 2; 103 } 104 105 dev_dbg(&edev->spi->dev, "read cmd 0x%x, %d Hz\n", 106 cmd_addr, edev->spi->max_speed_hz); 107 108 if (has_quirk_extra_read_cycle(edev)) { 109 cmd_addr <<= 1; 110 bits += 1; 111 } 112 113 spi_message_init(&m); 114 115 t[0].tx_buf = (char *)&cmd_addr; 116 t[0].len = 2; 117 t[0].bits_per_word = bits; 118 spi_message_add_tail(&t[0], &m); 119 120 t[1].rx_buf = buf; 121 t[1].len = count; 122 t[1].bits_per_word = 8; 123 spi_message_add_tail(&t[1], &m); 124 125 err = spi_sync(edev->spi, &m); 126 /* have to wait at least Tcsl ns */ 127 ndelay(250); 128 129 if (err) { 130 dev_err(&edev->spi->dev, "read %zu bytes at %d: err. %d\n", 131 nbytes, (int)off, err); 132 break; 133 } 134 135 buf += nbytes; 136 off += nbytes; 137 count -= nbytes; 138 } 139 140 if (edev->pdata->finish) 141 edev->pdata->finish(edev); 142 143 mutex_unlock(&edev->lock); 144 145 return err; 146 } 147 148 static int eeprom_93xx46_ew(struct eeprom_93xx46_dev *edev, int is_on) 149 { 150 struct spi_message m; 151 struct spi_transfer t; 152 int bits, ret; 153 u16 cmd_addr; 154 155 cmd_addr = OP_START << edev->addrlen; 156 if (edev->addrlen == 7) { 157 cmd_addr |= (is_on ? ADDR_EWEN : ADDR_EWDS) << 1; 158 bits = 10; 159 } else { 160 cmd_addr |= (is_on ? ADDR_EWEN : ADDR_EWDS); 161 bits = 9; 162 } 163 164 if (has_quirk_instruction_length(edev)) { 165 cmd_addr <<= 2; 166 bits += 2; 167 } 168 169 dev_dbg(&edev->spi->dev, "ew%s cmd 0x%04x, %d bits\n", 170 is_on ? "en" : "ds", cmd_addr, bits); 171 172 spi_message_init(&m); 173 memset(&t, 0, sizeof(t)); 174 175 t.tx_buf = &cmd_addr; 176 t.len = 2; 177 t.bits_per_word = bits; 178 spi_message_add_tail(&t, &m); 179 180 mutex_lock(&edev->lock); 181 182 if (edev->pdata->prepare) 183 edev->pdata->prepare(edev); 184 185 ret = spi_sync(edev->spi, &m); 186 /* have to wait at least Tcsl ns */ 187 ndelay(250); 188 if (ret) 189 dev_err(&edev->spi->dev, "erase/write %sable error %d\n", 190 is_on ? "en" : "dis", ret); 191 192 if (edev->pdata->finish) 193 edev->pdata->finish(edev); 194 195 mutex_unlock(&edev->lock); 196 return ret; 197 } 198 199 static ssize_t 200 eeprom_93xx46_write_word(struct eeprom_93xx46_dev *edev, 201 const char *buf, unsigned off) 202 { 203 struct spi_message m; 204 struct spi_transfer t[2]; 205 int bits, data_len, ret; 206 u16 cmd_addr; 207 208 cmd_addr = OP_WRITE << edev->addrlen; 209 210 if (edev->addrlen == 7) { 211 cmd_addr |= off & 0x7f; 212 bits = 10; 213 data_len = 1; 214 } else { 215 cmd_addr |= (off >> 1) & 0x3f; 216 bits = 9; 217 data_len = 2; 218 } 219 220 dev_dbg(&edev->spi->dev, "write cmd 0x%x\n", cmd_addr); 221 222 spi_message_init(&m); 223 memset(t, 0, sizeof(t)); 224 225 t[0].tx_buf = (char *)&cmd_addr; 226 t[0].len = 2; 227 t[0].bits_per_word = bits; 228 spi_message_add_tail(&t[0], &m); 229 230 t[1].tx_buf = buf; 231 t[1].len = data_len; 232 t[1].bits_per_word = 8; 233 spi_message_add_tail(&t[1], &m); 234 235 ret = spi_sync(edev->spi, &m); 236 /* have to wait program cycle time Twc ms */ 237 mdelay(6); 238 return ret; 239 } 240 241 static int eeprom_93xx46_write(void *priv, unsigned int off, 242 void *val, size_t count) 243 { 244 struct eeprom_93xx46_dev *edev = priv; 245 char *buf = val; 246 int i, ret, step = 1; 247 248 if (unlikely(off >= edev->size)) 249 return -EFBIG; 250 if ((off + count) > edev->size) 251 count = edev->size - off; 252 if (unlikely(!count)) 253 return count; 254 255 /* only write even number of bytes on 16-bit devices */ 256 if (edev->addrlen == 6) { 257 step = 2; 258 count &= ~1; 259 } 260 261 /* erase/write enable */ 262 ret = eeprom_93xx46_ew(edev, 1); 263 if (ret) 264 return ret; 265 266 mutex_lock(&edev->lock); 267 268 if (edev->pdata->prepare) 269 edev->pdata->prepare(edev); 270 271 for (i = 0; i < count; i += step) { 272 ret = eeprom_93xx46_write_word(edev, &buf[i], off + i); 273 if (ret) { 274 dev_err(&edev->spi->dev, "write failed at %d: %d\n", 275 (int)off + i, ret); 276 break; 277 } 278 } 279 280 if (edev->pdata->finish) 281 edev->pdata->finish(edev); 282 283 mutex_unlock(&edev->lock); 284 285 /* erase/write disable */ 286 eeprom_93xx46_ew(edev, 0); 287 return ret; 288 } 289 290 static int eeprom_93xx46_eral(struct eeprom_93xx46_dev *edev) 291 { 292 struct eeprom_93xx46_platform_data *pd = edev->pdata; 293 struct spi_message m; 294 struct spi_transfer t; 295 int bits, ret; 296 u16 cmd_addr; 297 298 cmd_addr = OP_START << edev->addrlen; 299 if (edev->addrlen == 7) { 300 cmd_addr |= ADDR_ERAL << 1; 301 bits = 10; 302 } else { 303 cmd_addr |= ADDR_ERAL; 304 bits = 9; 305 } 306 307 if (has_quirk_instruction_length(edev)) { 308 cmd_addr <<= 2; 309 bits += 2; 310 } 311 312 dev_dbg(&edev->spi->dev, "eral cmd 0x%04x, %d bits\n", cmd_addr, bits); 313 314 spi_message_init(&m); 315 memset(&t, 0, sizeof(t)); 316 317 t.tx_buf = &cmd_addr; 318 t.len = 2; 319 t.bits_per_word = bits; 320 spi_message_add_tail(&t, &m); 321 322 mutex_lock(&edev->lock); 323 324 if (edev->pdata->prepare) 325 edev->pdata->prepare(edev); 326 327 ret = spi_sync(edev->spi, &m); 328 if (ret) 329 dev_err(&edev->spi->dev, "erase error %d\n", ret); 330 /* have to wait erase cycle time Tec ms */ 331 mdelay(6); 332 333 if (pd->finish) 334 pd->finish(edev); 335 336 mutex_unlock(&edev->lock); 337 return ret; 338 } 339 340 static ssize_t eeprom_93xx46_store_erase(struct device *dev, 341 struct device_attribute *attr, 342 const char *buf, size_t count) 343 { 344 struct eeprom_93xx46_dev *edev = dev_get_drvdata(dev); 345 int erase = 0, ret; 346 347 sscanf(buf, "%d", &erase); 348 if (erase) { 349 ret = eeprom_93xx46_ew(edev, 1); 350 if (ret) 351 return ret; 352 ret = eeprom_93xx46_eral(edev); 353 if (ret) 354 return ret; 355 ret = eeprom_93xx46_ew(edev, 0); 356 if (ret) 357 return ret; 358 } 359 return count; 360 } 361 static DEVICE_ATTR(erase, S_IWUSR, NULL, eeprom_93xx46_store_erase); 362 363 static void select_assert(void *context) 364 { 365 struct eeprom_93xx46_dev *edev = context; 366 367 gpiod_set_value_cansleep(edev->pdata->select, 1); 368 } 369 370 static void select_deassert(void *context) 371 { 372 struct eeprom_93xx46_dev *edev = context; 373 374 gpiod_set_value_cansleep(edev->pdata->select, 0); 375 } 376 377 static const struct of_device_id eeprom_93xx46_of_table[] = { 378 { .compatible = "eeprom-93xx46", }, 379 { .compatible = "atmel,at93c46d", .data = &atmel_at93c46d_data, }, 380 { .compatible = "microchip,93lc46b", .data = µchip_93lc46b_data, }, 381 {} 382 }; 383 MODULE_DEVICE_TABLE(of, eeprom_93xx46_of_table); 384 385 static int eeprom_93xx46_probe_dt(struct spi_device *spi) 386 { 387 const struct of_device_id *of_id = 388 of_match_device(eeprom_93xx46_of_table, &spi->dev); 389 struct device_node *np = spi->dev.of_node; 390 struct eeprom_93xx46_platform_data *pd; 391 u32 tmp; 392 int ret; 393 394 pd = devm_kzalloc(&spi->dev, sizeof(*pd), GFP_KERNEL); 395 if (!pd) 396 return -ENOMEM; 397 398 ret = of_property_read_u32(np, "data-size", &tmp); 399 if (ret < 0) { 400 dev_err(&spi->dev, "data-size property not found\n"); 401 return ret; 402 } 403 404 if (tmp == 8) { 405 pd->flags |= EE_ADDR8; 406 } else if (tmp == 16) { 407 pd->flags |= EE_ADDR16; 408 } else { 409 dev_err(&spi->dev, "invalid data-size (%d)\n", tmp); 410 return -EINVAL; 411 } 412 413 if (of_property_read_bool(np, "read-only")) 414 pd->flags |= EE_READONLY; 415 416 pd->select = devm_gpiod_get_optional(&spi->dev, "select", 417 GPIOD_OUT_LOW); 418 if (IS_ERR(pd->select)) 419 return PTR_ERR(pd->select); 420 421 pd->prepare = select_assert; 422 pd->finish = select_deassert; 423 gpiod_direction_output(pd->select, 0); 424 425 if (of_id->data) { 426 const struct eeprom_93xx46_devtype_data *data = of_id->data; 427 428 pd->quirks = data->quirks; 429 } 430 431 spi->dev.platform_data = pd; 432 433 return 0; 434 } 435 436 static int eeprom_93xx46_probe(struct spi_device *spi) 437 { 438 struct eeprom_93xx46_platform_data *pd; 439 struct eeprom_93xx46_dev *edev; 440 int err; 441 442 if (spi->dev.of_node) { 443 err = eeprom_93xx46_probe_dt(spi); 444 if (err < 0) 445 return err; 446 } 447 448 pd = spi->dev.platform_data; 449 if (!pd) { 450 dev_err(&spi->dev, "missing platform data\n"); 451 return -ENODEV; 452 } 453 454 edev = devm_kzalloc(&spi->dev, sizeof(*edev), GFP_KERNEL); 455 if (!edev) 456 return -ENOMEM; 457 458 if (pd->flags & EE_ADDR8) 459 edev->addrlen = 7; 460 else if (pd->flags & EE_ADDR16) 461 edev->addrlen = 6; 462 else { 463 dev_err(&spi->dev, "unspecified address type\n"); 464 return -EINVAL; 465 } 466 467 mutex_init(&edev->lock); 468 469 edev->spi = spi; 470 edev->pdata = pd; 471 472 edev->size = 128; 473 edev->nvmem_config.type = NVMEM_TYPE_EEPROM; 474 edev->nvmem_config.name = dev_name(&spi->dev); 475 edev->nvmem_config.dev = &spi->dev; 476 edev->nvmem_config.read_only = pd->flags & EE_READONLY; 477 edev->nvmem_config.root_only = true; 478 edev->nvmem_config.owner = THIS_MODULE; 479 edev->nvmem_config.compat = true; 480 edev->nvmem_config.base_dev = &spi->dev; 481 edev->nvmem_config.reg_read = eeprom_93xx46_read; 482 edev->nvmem_config.reg_write = eeprom_93xx46_write; 483 edev->nvmem_config.priv = edev; 484 edev->nvmem_config.stride = 4; 485 edev->nvmem_config.word_size = 1; 486 edev->nvmem_config.size = edev->size; 487 488 edev->nvmem = devm_nvmem_register(&spi->dev, &edev->nvmem_config); 489 if (IS_ERR(edev->nvmem)) 490 return PTR_ERR(edev->nvmem); 491 492 dev_info(&spi->dev, "%d-bit eeprom %s\n", 493 (pd->flags & EE_ADDR8) ? 8 : 16, 494 (pd->flags & EE_READONLY) ? "(readonly)" : ""); 495 496 if (!(pd->flags & EE_READONLY)) { 497 if (device_create_file(&spi->dev, &dev_attr_erase)) 498 dev_err(&spi->dev, "can't create erase interface\n"); 499 } 500 501 spi_set_drvdata(spi, edev); 502 return 0; 503 } 504 505 static int eeprom_93xx46_remove(struct spi_device *spi) 506 { 507 struct eeprom_93xx46_dev *edev = spi_get_drvdata(spi); 508 509 if (!(edev->pdata->flags & EE_READONLY)) 510 device_remove_file(&spi->dev, &dev_attr_erase); 511 512 return 0; 513 } 514 515 static struct spi_driver eeprom_93xx46_driver = { 516 .driver = { 517 .name = "93xx46", 518 .of_match_table = of_match_ptr(eeprom_93xx46_of_table), 519 }, 520 .probe = eeprom_93xx46_probe, 521 .remove = eeprom_93xx46_remove, 522 }; 523 524 module_spi_driver(eeprom_93xx46_driver); 525 526 MODULE_LICENSE("GPL"); 527 MODULE_DESCRIPTION("Driver for 93xx46 EEPROMs"); 528 MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>"); 529 MODULE_ALIAS("spi:93xx46"); 530 MODULE_ALIAS("spi:eeprom-93xx46"); 531 MODULE_ALIAS("spi:93lc46b"); 532