1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * at25.c -- support most SPI EEPROMs, such as Atmel AT25 models 4 * and Cypress FRAMs FM25 models 5 * 6 * Copyright (C) 2006 David Brownell 7 */ 8 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/slab.h> 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/sched.h> 15 16 #include <linux/nvmem-provider.h> 17 #include <linux/spi/spi.h> 18 #include <linux/spi/eeprom.h> 19 #include <linux/property.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 #include <linux/math.h> 23 24 /* 25 * NOTE: this is an *EEPROM* driver. The vagaries of product naming 26 * mean that some AT25 products are EEPROMs, and others are FLASH. 27 * Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver, 28 * not this one! 29 * 30 * EEPROMs that can be used with this driver include, for example: 31 * AT25M02, AT25128B 32 */ 33 34 #define FM25_SN_LEN 8 /* serial number length */ 35 struct at25_data { 36 struct spi_device *spi; 37 struct mutex lock; 38 struct spi_eeprom chip; 39 unsigned addrlen; 40 struct nvmem_config nvmem_config; 41 struct nvmem_device *nvmem; 42 u8 sernum[FM25_SN_LEN]; 43 }; 44 45 #define AT25_WREN 0x06 /* latch the write enable */ 46 #define AT25_WRDI 0x04 /* reset the write enable */ 47 #define AT25_RDSR 0x05 /* read status register */ 48 #define AT25_WRSR 0x01 /* write status register */ 49 #define AT25_READ 0x03 /* read byte(s) */ 50 #define AT25_WRITE 0x02 /* write byte(s)/sector */ 51 #define FM25_SLEEP 0xb9 /* enter sleep mode */ 52 #define FM25_RDID 0x9f /* read device ID */ 53 #define FM25_RDSN 0xc3 /* read S/N */ 54 55 #define AT25_SR_nRDY 0x01 /* nRDY = write-in-progress */ 56 #define AT25_SR_WEN 0x02 /* write enable (latched) */ 57 #define AT25_SR_BP0 0x04 /* BP for software writeprotect */ 58 #define AT25_SR_BP1 0x08 59 #define AT25_SR_WPEN 0x80 /* writeprotect enable */ 60 61 #define AT25_INSTR_BIT3 0x08 /* Additional address bit in instr */ 62 63 #define FM25_ID_LEN 9 /* ID length */ 64 65 #define EE_MAXADDRLEN 3 /* 24 bit addresses, up to 2 MBytes */ 66 67 /* Specs often allow 5 msec for a page write, sometimes 20 msec; 68 * it's important to recover from write timeouts. 69 */ 70 #define EE_TIMEOUT 25 71 72 /*-------------------------------------------------------------------------*/ 73 74 #define io_limit PAGE_SIZE /* bytes */ 75 76 static int at25_ee_read(void *priv, unsigned int offset, 77 void *val, size_t count) 78 { 79 struct at25_data *at25 = priv; 80 char *buf = val; 81 u8 command[EE_MAXADDRLEN + 1]; 82 u8 *cp; 83 ssize_t status; 84 struct spi_transfer t[2]; 85 struct spi_message m; 86 u8 instr; 87 88 if (unlikely(offset >= at25->chip.byte_len)) 89 return -EINVAL; 90 if ((offset + count) > at25->chip.byte_len) 91 count = at25->chip.byte_len - offset; 92 if (unlikely(!count)) 93 return -EINVAL; 94 95 cp = command; 96 97 instr = AT25_READ; 98 if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR) 99 if (offset >= (1U << (at25->addrlen * 8))) 100 instr |= AT25_INSTR_BIT3; 101 *cp++ = instr; 102 103 /* 8/16/24-bit address is written MSB first */ 104 switch (at25->addrlen) { 105 default: /* case 3 */ 106 *cp++ = offset >> 16; 107 fallthrough; 108 case 2: 109 *cp++ = offset >> 8; 110 fallthrough; 111 case 1: 112 case 0: /* can't happen: for better codegen */ 113 *cp++ = offset >> 0; 114 } 115 116 spi_message_init(&m); 117 memset(t, 0, sizeof(t)); 118 119 t[0].tx_buf = command; 120 t[0].len = at25->addrlen + 1; 121 spi_message_add_tail(&t[0], &m); 122 123 t[1].rx_buf = buf; 124 t[1].len = count; 125 spi_message_add_tail(&t[1], &m); 126 127 mutex_lock(&at25->lock); 128 129 /* Read it all at once. 130 * 131 * REVISIT that's potentially a problem with large chips, if 132 * other devices on the bus need to be accessed regularly or 133 * this chip is clocked very slowly 134 */ 135 status = spi_sync(at25->spi, &m); 136 dev_dbg(&at25->spi->dev, "read %zu bytes at %d --> %zd\n", 137 count, offset, status); 138 139 mutex_unlock(&at25->lock); 140 return status; 141 } 142 143 /* 144 * read extra registers as ID or serial number 145 */ 146 static int fm25_aux_read(struct at25_data *at25, u8 *buf, uint8_t command, 147 int len) 148 { 149 int status; 150 struct spi_transfer t[2]; 151 struct spi_message m; 152 153 spi_message_init(&m); 154 memset(t, 0, sizeof(t)); 155 156 t[0].tx_buf = &command; 157 t[0].len = 1; 158 spi_message_add_tail(&t[0], &m); 159 160 t[1].rx_buf = buf; 161 t[1].len = len; 162 spi_message_add_tail(&t[1], &m); 163 164 mutex_lock(&at25->lock); 165 166 status = spi_sync(at25->spi, &m); 167 dev_dbg(&at25->spi->dev, "read %d aux bytes --> %d\n", len, status); 168 169 mutex_unlock(&at25->lock); 170 return status; 171 } 172 173 static ssize_t sernum_show(struct device *dev, struct device_attribute *attr, char *buf) 174 { 175 struct at25_data *at25; 176 177 at25 = dev_get_drvdata(dev); 178 return sysfs_emit(buf, "%*ph\n", (int)sizeof(at25->sernum), at25->sernum); 179 } 180 static DEVICE_ATTR_RO(sernum); 181 182 static struct attribute *sernum_attrs[] = { 183 &dev_attr_sernum.attr, 184 NULL, 185 }; 186 ATTRIBUTE_GROUPS(sernum); 187 188 static int at25_ee_write(void *priv, unsigned int off, void *val, size_t count) 189 { 190 struct at25_data *at25 = priv; 191 const char *buf = val; 192 int status = 0; 193 unsigned buf_size; 194 u8 *bounce; 195 196 if (unlikely(off >= at25->chip.byte_len)) 197 return -EFBIG; 198 if ((off + count) > at25->chip.byte_len) 199 count = at25->chip.byte_len - off; 200 if (unlikely(!count)) 201 return -EINVAL; 202 203 /* Temp buffer starts with command and address */ 204 buf_size = at25->chip.page_size; 205 if (buf_size > io_limit) 206 buf_size = io_limit; 207 bounce = kmalloc(buf_size + at25->addrlen + 1, GFP_KERNEL); 208 if (!bounce) 209 return -ENOMEM; 210 211 /* For write, rollover is within the page ... so we write at 212 * most one page, then manually roll over to the next page. 213 */ 214 mutex_lock(&at25->lock); 215 do { 216 unsigned long timeout, retries; 217 unsigned segment; 218 unsigned offset = (unsigned) off; 219 u8 *cp = bounce; 220 int sr; 221 u8 instr; 222 223 *cp = AT25_WREN; 224 status = spi_write(at25->spi, cp, 1); 225 if (status < 0) { 226 dev_dbg(&at25->spi->dev, "WREN --> %d\n", status); 227 break; 228 } 229 230 instr = AT25_WRITE; 231 if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR) 232 if (offset >= (1U << (at25->addrlen * 8))) 233 instr |= AT25_INSTR_BIT3; 234 *cp++ = instr; 235 236 /* 8/16/24-bit address is written MSB first */ 237 switch (at25->addrlen) { 238 default: /* case 3 */ 239 *cp++ = offset >> 16; 240 fallthrough; 241 case 2: 242 *cp++ = offset >> 8; 243 fallthrough; 244 case 1: 245 case 0: /* can't happen: for better codegen */ 246 *cp++ = offset >> 0; 247 } 248 249 /* Write as much of a page as we can */ 250 segment = buf_size - (offset % buf_size); 251 if (segment > count) 252 segment = count; 253 memcpy(cp, buf, segment); 254 status = spi_write(at25->spi, bounce, 255 segment + at25->addrlen + 1); 256 dev_dbg(&at25->spi->dev, "write %u bytes at %u --> %d\n", 257 segment, offset, status); 258 if (status < 0) 259 break; 260 261 /* REVISIT this should detect (or prevent) failed writes 262 * to readonly sections of the EEPROM... 263 */ 264 265 /* Wait for non-busy status */ 266 timeout = jiffies + msecs_to_jiffies(EE_TIMEOUT); 267 retries = 0; 268 do { 269 270 sr = spi_w8r8(at25->spi, AT25_RDSR); 271 if (sr < 0 || (sr & AT25_SR_nRDY)) { 272 dev_dbg(&at25->spi->dev, 273 "rdsr --> %d (%02x)\n", sr, sr); 274 /* at HZ=100, this is sloooow */ 275 msleep(1); 276 continue; 277 } 278 if (!(sr & AT25_SR_nRDY)) 279 break; 280 } while (retries++ < 3 || time_before_eq(jiffies, timeout)); 281 282 if ((sr < 0) || (sr & AT25_SR_nRDY)) { 283 dev_err(&at25->spi->dev, 284 "write %u bytes offset %u, timeout after %u msecs\n", 285 segment, offset, 286 jiffies_to_msecs(jiffies - 287 (timeout - EE_TIMEOUT))); 288 status = -ETIMEDOUT; 289 break; 290 } 291 292 off += segment; 293 buf += segment; 294 count -= segment; 295 296 } while (count > 0); 297 298 mutex_unlock(&at25->lock); 299 300 kfree(bounce); 301 return status; 302 } 303 304 /*-------------------------------------------------------------------------*/ 305 306 static int at25_fw_to_chip(struct device *dev, struct spi_eeprom *chip) 307 { 308 u32 val; 309 310 memset(chip, 0, sizeof(*chip)); 311 strncpy(chip->name, "at25", sizeof(chip->name)); 312 313 if (device_property_read_u32(dev, "size", &val) == 0 || 314 device_property_read_u32(dev, "at25,byte-len", &val) == 0) { 315 chip->byte_len = val; 316 } else { 317 dev_err(dev, "Error: missing \"size\" property\n"); 318 return -ENODEV; 319 } 320 321 if (device_property_read_u32(dev, "pagesize", &val) == 0 || 322 device_property_read_u32(dev, "at25,page-size", &val) == 0) { 323 chip->page_size = val; 324 } else { 325 dev_err(dev, "Error: missing \"pagesize\" property\n"); 326 return -ENODEV; 327 } 328 329 if (device_property_read_u32(dev, "at25,addr-mode", &val) == 0) { 330 chip->flags = (u16)val; 331 } else { 332 if (device_property_read_u32(dev, "address-width", &val)) { 333 dev_err(dev, 334 "Error: missing \"address-width\" property\n"); 335 return -ENODEV; 336 } 337 switch (val) { 338 case 9: 339 chip->flags |= EE_INSTR_BIT3_IS_ADDR; 340 fallthrough; 341 case 8: 342 chip->flags |= EE_ADDR1; 343 break; 344 case 16: 345 chip->flags |= EE_ADDR2; 346 break; 347 case 24: 348 chip->flags |= EE_ADDR3; 349 break; 350 default: 351 dev_err(dev, 352 "Error: bad \"address-width\" property: %u\n", 353 val); 354 return -ENODEV; 355 } 356 if (device_property_present(dev, "read-only")) 357 chip->flags |= EE_READONLY; 358 } 359 return 0; 360 } 361 362 static const struct of_device_id at25_of_match[] = { 363 { .compatible = "atmel,at25",}, 364 { .compatible = "cypress,fm25",}, 365 { } 366 }; 367 MODULE_DEVICE_TABLE(of, at25_of_match); 368 369 static const struct spi_device_id at25_spi_ids[] = { 370 { .name = "at25",}, 371 { .name = "fm25",}, 372 { } 373 }; 374 MODULE_DEVICE_TABLE(spi, at25_spi_ids); 375 376 static int at25_probe(struct spi_device *spi) 377 { 378 struct at25_data *at25 = NULL; 379 struct spi_eeprom chip; 380 int err; 381 int sr; 382 u8 id[FM25_ID_LEN]; 383 u8 sernum[FM25_SN_LEN]; 384 int i; 385 const struct of_device_id *match; 386 bool is_fram = 0; 387 388 match = of_match_device(of_match_ptr(at25_of_match), &spi->dev); 389 if (match && !strcmp(match->compatible, "cypress,fm25")) 390 is_fram = 1; 391 392 /* Chip description */ 393 if (!spi->dev.platform_data) { 394 if (!is_fram) { 395 err = at25_fw_to_chip(&spi->dev, &chip); 396 if (err) 397 return err; 398 } 399 } else 400 chip = *(struct spi_eeprom *)spi->dev.platform_data; 401 402 /* Ping the chip ... the status register is pretty portable, 403 * unlike probing manufacturer IDs. We do expect that system 404 * firmware didn't write it in the past few milliseconds! 405 */ 406 sr = spi_w8r8(spi, AT25_RDSR); 407 if (sr < 0 || sr & AT25_SR_nRDY) { 408 dev_dbg(&spi->dev, "rdsr --> %d (%02x)\n", sr, sr); 409 return -ENXIO; 410 } 411 412 at25 = devm_kzalloc(&spi->dev, sizeof(struct at25_data), GFP_KERNEL); 413 if (!at25) 414 return -ENOMEM; 415 416 mutex_init(&at25->lock); 417 at25->chip = chip; 418 at25->spi = spi; 419 spi_set_drvdata(spi, at25); 420 421 if (is_fram) { 422 /* Get ID of chip */ 423 fm25_aux_read(at25, id, FM25_RDID, FM25_ID_LEN); 424 if (id[6] != 0xc2) { 425 dev_err(&spi->dev, 426 "Error: no Cypress FRAM (id %02x)\n", id[6]); 427 return -ENODEV; 428 } 429 /* set size found in ID */ 430 if (id[7] < 0x21 || id[7] > 0x26) { 431 dev_err(&spi->dev, "Error: unsupported size (id %02x)\n", id[7]); 432 return -ENODEV; 433 } 434 chip.byte_len = int_pow(2, id[7] - 0x21 + 4) * 1024; 435 436 if (at25->chip.byte_len > 64 * 1024) 437 at25->chip.flags |= EE_ADDR3; 438 else 439 at25->chip.flags |= EE_ADDR2; 440 441 if (id[8]) { 442 fm25_aux_read(at25, sernum, FM25_RDSN, FM25_SN_LEN); 443 /* swap byte order */ 444 for (i = 0; i < FM25_SN_LEN; i++) 445 at25->sernum[i] = sernum[FM25_SN_LEN - 1 - i]; 446 } 447 448 at25->chip.page_size = PAGE_SIZE; 449 strncpy(at25->chip.name, "fm25", sizeof(at25->chip.name)); 450 } 451 452 /* For now we only support 8/16/24 bit addressing */ 453 if (at25->chip.flags & EE_ADDR1) 454 at25->addrlen = 1; 455 else if (at25->chip.flags & EE_ADDR2) 456 at25->addrlen = 2; 457 else if (at25->chip.flags & EE_ADDR3) 458 at25->addrlen = 3; 459 else { 460 dev_dbg(&spi->dev, "unsupported address type\n"); 461 return -EINVAL; 462 } 463 464 at25->nvmem_config.type = is_fram ? NVMEM_TYPE_FRAM : NVMEM_TYPE_EEPROM; 465 at25->nvmem_config.name = dev_name(&spi->dev); 466 at25->nvmem_config.dev = &spi->dev; 467 at25->nvmem_config.read_only = chip.flags & EE_READONLY; 468 at25->nvmem_config.root_only = true; 469 at25->nvmem_config.owner = THIS_MODULE; 470 at25->nvmem_config.compat = true; 471 at25->nvmem_config.base_dev = &spi->dev; 472 at25->nvmem_config.reg_read = at25_ee_read; 473 at25->nvmem_config.reg_write = at25_ee_write; 474 at25->nvmem_config.priv = at25; 475 at25->nvmem_config.stride = 1; 476 at25->nvmem_config.word_size = 1; 477 at25->nvmem_config.size = chip.byte_len; 478 479 at25->nvmem = devm_nvmem_register(&spi->dev, &at25->nvmem_config); 480 if (IS_ERR(at25->nvmem)) 481 return PTR_ERR(at25->nvmem); 482 483 dev_info(&spi->dev, "%d %s %s %s%s, pagesize %u\n", 484 (chip.byte_len < 1024) ? chip.byte_len : (chip.byte_len / 1024), 485 (chip.byte_len < 1024) ? "Byte" : "KByte", 486 at25->chip.name, is_fram ? "fram" : "eeprom", 487 (chip.flags & EE_READONLY) ? " (readonly)" : "", 488 at25->chip.page_size); 489 return 0; 490 } 491 492 /*-------------------------------------------------------------------------*/ 493 494 static struct spi_driver at25_driver = { 495 .driver = { 496 .name = "at25", 497 .of_match_table = at25_of_match, 498 .dev_groups = sernum_groups, 499 }, 500 .probe = at25_probe, 501 .id_table = at25_spi_ids, 502 }; 503 504 module_spi_driver(at25_driver); 505 506 MODULE_DESCRIPTION("Driver for most SPI EEPROMs"); 507 MODULE_AUTHOR("David Brownell"); 508 MODULE_LICENSE("GPL"); 509 MODULE_ALIAS("spi:at25"); 510