1 /* 2 * at25.c -- support most SPI EEPROMs, such as Atmel AT25 models 3 * 4 * Copyright (C) 2006 David Brownell 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/slab.h> 15 #include <linux/delay.h> 16 #include <linux/device.h> 17 #include <linux/sched.h> 18 19 #include <linux/nvmem-provider.h> 20 #include <linux/spi/spi.h> 21 #include <linux/spi/eeprom.h> 22 #include <linux/property.h> 23 24 /* 25 * NOTE: this is an *EEPROM* driver. The vagaries of product naming 26 * mean that some AT25 products are EEPROMs, and others are FLASH. 27 * Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver, 28 * not this one! 29 */ 30 31 struct at25_data { 32 struct spi_device *spi; 33 struct mutex lock; 34 struct spi_eeprom chip; 35 unsigned addrlen; 36 struct nvmem_config nvmem_config; 37 struct nvmem_device *nvmem; 38 }; 39 40 #define AT25_WREN 0x06 /* latch the write enable */ 41 #define AT25_WRDI 0x04 /* reset the write enable */ 42 #define AT25_RDSR 0x05 /* read status register */ 43 #define AT25_WRSR 0x01 /* write status register */ 44 #define AT25_READ 0x03 /* read byte(s) */ 45 #define AT25_WRITE 0x02 /* write byte(s)/sector */ 46 47 #define AT25_SR_nRDY 0x01 /* nRDY = write-in-progress */ 48 #define AT25_SR_WEN 0x02 /* write enable (latched) */ 49 #define AT25_SR_BP0 0x04 /* BP for software writeprotect */ 50 #define AT25_SR_BP1 0x08 51 #define AT25_SR_WPEN 0x80 /* writeprotect enable */ 52 53 #define AT25_INSTR_BIT3 0x08 /* Additional address bit in instr */ 54 55 #define EE_MAXADDRLEN 3 /* 24 bit addresses, up to 2 MBytes */ 56 57 /* Specs often allow 5 msec for a page write, sometimes 20 msec; 58 * it's important to recover from write timeouts. 59 */ 60 #define EE_TIMEOUT 25 61 62 /*-------------------------------------------------------------------------*/ 63 64 #define io_limit PAGE_SIZE /* bytes */ 65 66 static int at25_ee_read(void *priv, unsigned int offset, 67 void *val, size_t count) 68 { 69 struct at25_data *at25 = priv; 70 char *buf = val; 71 u8 command[EE_MAXADDRLEN + 1]; 72 u8 *cp; 73 ssize_t status; 74 struct spi_transfer t[2]; 75 struct spi_message m; 76 u8 instr; 77 78 if (unlikely(offset >= at25->chip.byte_len)) 79 return -EINVAL; 80 if ((offset + count) > at25->chip.byte_len) 81 count = at25->chip.byte_len - offset; 82 if (unlikely(!count)) 83 return -EINVAL; 84 85 cp = command; 86 87 instr = AT25_READ; 88 if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR) 89 if (offset >= (1U << (at25->addrlen * 8))) 90 instr |= AT25_INSTR_BIT3; 91 *cp++ = instr; 92 93 /* 8/16/24-bit address is written MSB first */ 94 switch (at25->addrlen) { 95 default: /* case 3 */ 96 *cp++ = offset >> 16; 97 /* fall through */ 98 case 2: 99 *cp++ = offset >> 8; 100 /* fall through */ 101 case 1: 102 case 0: /* can't happen: for better codegen */ 103 *cp++ = offset >> 0; 104 } 105 106 spi_message_init(&m); 107 memset(t, 0, sizeof(t)); 108 109 t[0].tx_buf = command; 110 t[0].len = at25->addrlen + 1; 111 spi_message_add_tail(&t[0], &m); 112 113 t[1].rx_buf = buf; 114 t[1].len = count; 115 spi_message_add_tail(&t[1], &m); 116 117 mutex_lock(&at25->lock); 118 119 /* Read it all at once. 120 * 121 * REVISIT that's potentially a problem with large chips, if 122 * other devices on the bus need to be accessed regularly or 123 * this chip is clocked very slowly 124 */ 125 status = spi_sync(at25->spi, &m); 126 dev_dbg(&at25->spi->dev, "read %zu bytes at %d --> %zd\n", 127 count, offset, status); 128 129 mutex_unlock(&at25->lock); 130 return status; 131 } 132 133 static int at25_ee_write(void *priv, unsigned int off, void *val, size_t count) 134 { 135 struct at25_data *at25 = priv; 136 const char *buf = val; 137 int status = 0; 138 unsigned buf_size; 139 u8 *bounce; 140 141 if (unlikely(off >= at25->chip.byte_len)) 142 return -EFBIG; 143 if ((off + count) > at25->chip.byte_len) 144 count = at25->chip.byte_len - off; 145 if (unlikely(!count)) 146 return -EINVAL; 147 148 /* Temp buffer starts with command and address */ 149 buf_size = at25->chip.page_size; 150 if (buf_size > io_limit) 151 buf_size = io_limit; 152 bounce = kmalloc(buf_size + at25->addrlen + 1, GFP_KERNEL); 153 if (!bounce) 154 return -ENOMEM; 155 156 /* For write, rollover is within the page ... so we write at 157 * most one page, then manually roll over to the next page. 158 */ 159 mutex_lock(&at25->lock); 160 do { 161 unsigned long timeout, retries; 162 unsigned segment; 163 unsigned offset = (unsigned) off; 164 u8 *cp = bounce; 165 int sr; 166 u8 instr; 167 168 *cp = AT25_WREN; 169 status = spi_write(at25->spi, cp, 1); 170 if (status < 0) { 171 dev_dbg(&at25->spi->dev, "WREN --> %d\n", status); 172 break; 173 } 174 175 instr = AT25_WRITE; 176 if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR) 177 if (offset >= (1U << (at25->addrlen * 8))) 178 instr |= AT25_INSTR_BIT3; 179 *cp++ = instr; 180 181 /* 8/16/24-bit address is written MSB first */ 182 switch (at25->addrlen) { 183 default: /* case 3 */ 184 *cp++ = offset >> 16; 185 /* fall through */ 186 case 2: 187 *cp++ = offset >> 8; 188 /* fall through */ 189 case 1: 190 case 0: /* can't happen: for better codegen */ 191 *cp++ = offset >> 0; 192 } 193 194 /* Write as much of a page as we can */ 195 segment = buf_size - (offset % buf_size); 196 if (segment > count) 197 segment = count; 198 memcpy(cp, buf, segment); 199 status = spi_write(at25->spi, bounce, 200 segment + at25->addrlen + 1); 201 dev_dbg(&at25->spi->dev, "write %u bytes at %u --> %d\n", 202 segment, offset, status); 203 if (status < 0) 204 break; 205 206 /* REVISIT this should detect (or prevent) failed writes 207 * to readonly sections of the EEPROM... 208 */ 209 210 /* Wait for non-busy status */ 211 timeout = jiffies + msecs_to_jiffies(EE_TIMEOUT); 212 retries = 0; 213 do { 214 215 sr = spi_w8r8(at25->spi, AT25_RDSR); 216 if (sr < 0 || (sr & AT25_SR_nRDY)) { 217 dev_dbg(&at25->spi->dev, 218 "rdsr --> %d (%02x)\n", sr, sr); 219 /* at HZ=100, this is sloooow */ 220 msleep(1); 221 continue; 222 } 223 if (!(sr & AT25_SR_nRDY)) 224 break; 225 } while (retries++ < 3 || time_before_eq(jiffies, timeout)); 226 227 if ((sr < 0) || (sr & AT25_SR_nRDY)) { 228 dev_err(&at25->spi->dev, 229 "write %u bytes offset %u, timeout after %u msecs\n", 230 segment, offset, 231 jiffies_to_msecs(jiffies - 232 (timeout - EE_TIMEOUT))); 233 status = -ETIMEDOUT; 234 break; 235 } 236 237 off += segment; 238 buf += segment; 239 count -= segment; 240 241 } while (count > 0); 242 243 mutex_unlock(&at25->lock); 244 245 kfree(bounce); 246 return status; 247 } 248 249 /*-------------------------------------------------------------------------*/ 250 251 static int at25_fw_to_chip(struct device *dev, struct spi_eeprom *chip) 252 { 253 u32 val; 254 255 memset(chip, 0, sizeof(*chip)); 256 strncpy(chip->name, "at25", sizeof(chip->name)); 257 258 if (device_property_read_u32(dev, "size", &val) == 0 || 259 device_property_read_u32(dev, "at25,byte-len", &val) == 0) { 260 chip->byte_len = val; 261 } else { 262 dev_err(dev, "Error: missing \"size\" property\n"); 263 return -ENODEV; 264 } 265 266 if (device_property_read_u32(dev, "pagesize", &val) == 0 || 267 device_property_read_u32(dev, "at25,page-size", &val) == 0) { 268 chip->page_size = (u16)val; 269 } else { 270 dev_err(dev, "Error: missing \"pagesize\" property\n"); 271 return -ENODEV; 272 } 273 274 if (device_property_read_u32(dev, "at25,addr-mode", &val) == 0) { 275 chip->flags = (u16)val; 276 } else { 277 if (device_property_read_u32(dev, "address-width", &val)) { 278 dev_err(dev, 279 "Error: missing \"address-width\" property\n"); 280 return -ENODEV; 281 } 282 switch (val) { 283 case 9: 284 chip->flags |= EE_INSTR_BIT3_IS_ADDR; 285 /* fall through */ 286 case 8: 287 chip->flags |= EE_ADDR1; 288 break; 289 case 16: 290 chip->flags |= EE_ADDR2; 291 break; 292 case 24: 293 chip->flags |= EE_ADDR3; 294 break; 295 default: 296 dev_err(dev, 297 "Error: bad \"address-width\" property: %u\n", 298 val); 299 return -ENODEV; 300 } 301 if (device_property_present(dev, "read-only")) 302 chip->flags |= EE_READONLY; 303 } 304 return 0; 305 } 306 307 static int at25_probe(struct spi_device *spi) 308 { 309 struct at25_data *at25 = NULL; 310 struct spi_eeprom chip; 311 int err; 312 int sr; 313 int addrlen; 314 315 /* Chip description */ 316 if (!spi->dev.platform_data) { 317 err = at25_fw_to_chip(&spi->dev, &chip); 318 if (err) 319 return err; 320 } else 321 chip = *(struct spi_eeprom *)spi->dev.platform_data; 322 323 /* For now we only support 8/16/24 bit addressing */ 324 if (chip.flags & EE_ADDR1) 325 addrlen = 1; 326 else if (chip.flags & EE_ADDR2) 327 addrlen = 2; 328 else if (chip.flags & EE_ADDR3) 329 addrlen = 3; 330 else { 331 dev_dbg(&spi->dev, "unsupported address type\n"); 332 return -EINVAL; 333 } 334 335 /* Ping the chip ... the status register is pretty portable, 336 * unlike probing manufacturer IDs. We do expect that system 337 * firmware didn't write it in the past few milliseconds! 338 */ 339 sr = spi_w8r8(spi, AT25_RDSR); 340 if (sr < 0 || sr & AT25_SR_nRDY) { 341 dev_dbg(&spi->dev, "rdsr --> %d (%02x)\n", sr, sr); 342 return -ENXIO; 343 } 344 345 at25 = devm_kzalloc(&spi->dev, sizeof(struct at25_data), GFP_KERNEL); 346 if (!at25) 347 return -ENOMEM; 348 349 mutex_init(&at25->lock); 350 at25->chip = chip; 351 at25->spi = spi; 352 spi_set_drvdata(spi, at25); 353 at25->addrlen = addrlen; 354 355 at25->nvmem_config.name = dev_name(&spi->dev); 356 at25->nvmem_config.dev = &spi->dev; 357 at25->nvmem_config.read_only = chip.flags & EE_READONLY; 358 at25->nvmem_config.root_only = true; 359 at25->nvmem_config.owner = THIS_MODULE; 360 at25->nvmem_config.compat = true; 361 at25->nvmem_config.base_dev = &spi->dev; 362 at25->nvmem_config.reg_read = at25_ee_read; 363 at25->nvmem_config.reg_write = at25_ee_write; 364 at25->nvmem_config.priv = at25; 365 at25->nvmem_config.stride = 4; 366 at25->nvmem_config.word_size = 1; 367 at25->nvmem_config.size = chip.byte_len; 368 369 at25->nvmem = devm_nvmem_register(&spi->dev, &at25->nvmem_config); 370 if (IS_ERR(at25->nvmem)) 371 return PTR_ERR(at25->nvmem); 372 373 dev_info(&spi->dev, "%d %s %s eeprom%s, pagesize %u\n", 374 (chip.byte_len < 1024) ? chip.byte_len : (chip.byte_len / 1024), 375 (chip.byte_len < 1024) ? "Byte" : "KByte", 376 at25->chip.name, 377 (chip.flags & EE_READONLY) ? " (readonly)" : "", 378 at25->chip.page_size); 379 return 0; 380 } 381 382 /*-------------------------------------------------------------------------*/ 383 384 static const struct of_device_id at25_of_match[] = { 385 { .compatible = "atmel,at25", }, 386 { } 387 }; 388 MODULE_DEVICE_TABLE(of, at25_of_match); 389 390 static struct spi_driver at25_driver = { 391 .driver = { 392 .name = "at25", 393 .of_match_table = at25_of_match, 394 }, 395 .probe = at25_probe, 396 }; 397 398 module_spi_driver(at25_driver); 399 400 MODULE_DESCRIPTION("Driver for most SPI EEPROMs"); 401 MODULE_AUTHOR("David Brownell"); 402 MODULE_LICENSE("GPL"); 403 MODULE_ALIAS("spi:at25"); 404