1 /* 2 * at25.c -- support most SPI EEPROMs, such as Atmel AT25 models 3 * 4 * Copyright (C) 2006 David Brownell 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/slab.h> 15 #include <linux/delay.h> 16 #include <linux/device.h> 17 #include <linux/sched.h> 18 19 #include <linux/nvmem-provider.h> 20 #include <linux/spi/spi.h> 21 #include <linux/spi/eeprom.h> 22 #include <linux/property.h> 23 24 /* 25 * NOTE: this is an *EEPROM* driver. The vagaries of product naming 26 * mean that some AT25 products are EEPROMs, and others are FLASH. 27 * Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver, 28 * not this one! 29 */ 30 31 struct at25_data { 32 struct spi_device *spi; 33 struct mutex lock; 34 struct spi_eeprom chip; 35 unsigned addrlen; 36 struct nvmem_config nvmem_config; 37 struct nvmem_device *nvmem; 38 }; 39 40 #define AT25_WREN 0x06 /* latch the write enable */ 41 #define AT25_WRDI 0x04 /* reset the write enable */ 42 #define AT25_RDSR 0x05 /* read status register */ 43 #define AT25_WRSR 0x01 /* write status register */ 44 #define AT25_READ 0x03 /* read byte(s) */ 45 #define AT25_WRITE 0x02 /* write byte(s)/sector */ 46 47 #define AT25_SR_nRDY 0x01 /* nRDY = write-in-progress */ 48 #define AT25_SR_WEN 0x02 /* write enable (latched) */ 49 #define AT25_SR_BP0 0x04 /* BP for software writeprotect */ 50 #define AT25_SR_BP1 0x08 51 #define AT25_SR_WPEN 0x80 /* writeprotect enable */ 52 53 #define AT25_INSTR_BIT3 0x08 /* Additional address bit in instr */ 54 55 #define EE_MAXADDRLEN 3 /* 24 bit addresses, up to 2 MBytes */ 56 57 /* Specs often allow 5 msec for a page write, sometimes 20 msec; 58 * it's important to recover from write timeouts. 59 */ 60 #define EE_TIMEOUT 25 61 62 /*-------------------------------------------------------------------------*/ 63 64 #define io_limit PAGE_SIZE /* bytes */ 65 66 static int at25_ee_read(void *priv, unsigned int offset, 67 void *val, size_t count) 68 { 69 struct at25_data *at25 = priv; 70 char *buf = val; 71 u8 command[EE_MAXADDRLEN + 1]; 72 u8 *cp; 73 ssize_t status; 74 struct spi_transfer t[2]; 75 struct spi_message m; 76 u8 instr; 77 78 if (unlikely(offset >= at25->chip.byte_len)) 79 return -EINVAL; 80 if ((offset + count) > at25->chip.byte_len) 81 count = at25->chip.byte_len - offset; 82 if (unlikely(!count)) 83 return -EINVAL; 84 85 cp = command; 86 87 instr = AT25_READ; 88 if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR) 89 if (offset >= (1U << (at25->addrlen * 8))) 90 instr |= AT25_INSTR_BIT3; 91 *cp++ = instr; 92 93 /* 8/16/24-bit address is written MSB first */ 94 switch (at25->addrlen) { 95 default: /* case 3 */ 96 *cp++ = offset >> 16; 97 case 2: 98 *cp++ = offset >> 8; 99 case 1: 100 case 0: /* can't happen: for better codegen */ 101 *cp++ = offset >> 0; 102 } 103 104 spi_message_init(&m); 105 memset(t, 0, sizeof t); 106 107 t[0].tx_buf = command; 108 t[0].len = at25->addrlen + 1; 109 spi_message_add_tail(&t[0], &m); 110 111 t[1].rx_buf = buf; 112 t[1].len = count; 113 spi_message_add_tail(&t[1], &m); 114 115 mutex_lock(&at25->lock); 116 117 /* Read it all at once. 118 * 119 * REVISIT that's potentially a problem with large chips, if 120 * other devices on the bus need to be accessed regularly or 121 * this chip is clocked very slowly 122 */ 123 status = spi_sync(at25->spi, &m); 124 dev_dbg(&at25->spi->dev, "read %zu bytes at %d --> %zd\n", 125 count, offset, status); 126 127 mutex_unlock(&at25->lock); 128 return status; 129 } 130 131 static int at25_ee_write(void *priv, unsigned int off, void *val, size_t count) 132 { 133 struct at25_data *at25 = priv; 134 const char *buf = val; 135 int status = 0; 136 unsigned buf_size; 137 u8 *bounce; 138 139 if (unlikely(off >= at25->chip.byte_len)) 140 return -EFBIG; 141 if ((off + count) > at25->chip.byte_len) 142 count = at25->chip.byte_len - off; 143 if (unlikely(!count)) 144 return -EINVAL; 145 146 /* Temp buffer starts with command and address */ 147 buf_size = at25->chip.page_size; 148 if (buf_size > io_limit) 149 buf_size = io_limit; 150 bounce = kmalloc(buf_size + at25->addrlen + 1, GFP_KERNEL); 151 if (!bounce) 152 return -ENOMEM; 153 154 /* For write, rollover is within the page ... so we write at 155 * most one page, then manually roll over to the next page. 156 */ 157 mutex_lock(&at25->lock); 158 do { 159 unsigned long timeout, retries; 160 unsigned segment; 161 unsigned offset = (unsigned) off; 162 u8 *cp = bounce; 163 int sr; 164 u8 instr; 165 166 *cp = AT25_WREN; 167 status = spi_write(at25->spi, cp, 1); 168 if (status < 0) { 169 dev_dbg(&at25->spi->dev, "WREN --> %d\n", status); 170 break; 171 } 172 173 instr = AT25_WRITE; 174 if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR) 175 if (offset >= (1U << (at25->addrlen * 8))) 176 instr |= AT25_INSTR_BIT3; 177 *cp++ = instr; 178 179 /* 8/16/24-bit address is written MSB first */ 180 switch (at25->addrlen) { 181 default: /* case 3 */ 182 *cp++ = offset >> 16; 183 case 2: 184 *cp++ = offset >> 8; 185 case 1: 186 case 0: /* can't happen: for better codegen */ 187 *cp++ = offset >> 0; 188 } 189 190 /* Write as much of a page as we can */ 191 segment = buf_size - (offset % buf_size); 192 if (segment > count) 193 segment = count; 194 memcpy(cp, buf, segment); 195 status = spi_write(at25->spi, bounce, 196 segment + at25->addrlen + 1); 197 dev_dbg(&at25->spi->dev, "write %u bytes at %u --> %d\n", 198 segment, offset, status); 199 if (status < 0) 200 break; 201 202 /* REVISIT this should detect (or prevent) failed writes 203 * to readonly sections of the EEPROM... 204 */ 205 206 /* Wait for non-busy status */ 207 timeout = jiffies + msecs_to_jiffies(EE_TIMEOUT); 208 retries = 0; 209 do { 210 211 sr = spi_w8r8(at25->spi, AT25_RDSR); 212 if (sr < 0 || (sr & AT25_SR_nRDY)) { 213 dev_dbg(&at25->spi->dev, 214 "rdsr --> %d (%02x)\n", sr, sr); 215 /* at HZ=100, this is sloooow */ 216 msleep(1); 217 continue; 218 } 219 if (!(sr & AT25_SR_nRDY)) 220 break; 221 } while (retries++ < 3 || time_before_eq(jiffies, timeout)); 222 223 if ((sr < 0) || (sr & AT25_SR_nRDY)) { 224 dev_err(&at25->spi->dev, 225 "write %u bytes offset %u, timeout after %u msecs\n", 226 segment, offset, 227 jiffies_to_msecs(jiffies - 228 (timeout - EE_TIMEOUT))); 229 status = -ETIMEDOUT; 230 break; 231 } 232 233 off += segment; 234 buf += segment; 235 count -= segment; 236 237 } while (count > 0); 238 239 mutex_unlock(&at25->lock); 240 241 kfree(bounce); 242 return status; 243 } 244 245 /*-------------------------------------------------------------------------*/ 246 247 static int at25_fw_to_chip(struct device *dev, struct spi_eeprom *chip) 248 { 249 u32 val; 250 251 memset(chip, 0, sizeof(*chip)); 252 strncpy(chip->name, "at25", sizeof(chip->name)); 253 254 if (device_property_read_u32(dev, "size", &val) == 0 || 255 device_property_read_u32(dev, "at25,byte-len", &val) == 0) { 256 chip->byte_len = val; 257 } else { 258 dev_err(dev, "Error: missing \"size\" property\n"); 259 return -ENODEV; 260 } 261 262 if (device_property_read_u32(dev, "pagesize", &val) == 0 || 263 device_property_read_u32(dev, "at25,page-size", &val) == 0) { 264 chip->page_size = (u16)val; 265 } else { 266 dev_err(dev, "Error: missing \"pagesize\" property\n"); 267 return -ENODEV; 268 } 269 270 if (device_property_read_u32(dev, "at25,addr-mode", &val) == 0) { 271 chip->flags = (u16)val; 272 } else { 273 if (device_property_read_u32(dev, "address-width", &val)) { 274 dev_err(dev, 275 "Error: missing \"address-width\" property\n"); 276 return -ENODEV; 277 } 278 switch (val) { 279 case 8: 280 chip->flags |= EE_ADDR1; 281 break; 282 case 16: 283 chip->flags |= EE_ADDR2; 284 break; 285 case 24: 286 chip->flags |= EE_ADDR3; 287 break; 288 default: 289 dev_err(dev, 290 "Error: bad \"address-width\" property: %u\n", 291 val); 292 return -ENODEV; 293 } 294 if (device_property_present(dev, "read-only")) 295 chip->flags |= EE_READONLY; 296 } 297 return 0; 298 } 299 300 static int at25_probe(struct spi_device *spi) 301 { 302 struct at25_data *at25 = NULL; 303 struct spi_eeprom chip; 304 int err; 305 int sr; 306 int addrlen; 307 308 /* Chip description */ 309 if (!spi->dev.platform_data) { 310 err = at25_fw_to_chip(&spi->dev, &chip); 311 if (err) 312 return err; 313 } else 314 chip = *(struct spi_eeprom *)spi->dev.platform_data; 315 316 /* For now we only support 8/16/24 bit addressing */ 317 if (chip.flags & EE_ADDR1) 318 addrlen = 1; 319 else if (chip.flags & EE_ADDR2) 320 addrlen = 2; 321 else if (chip.flags & EE_ADDR3) 322 addrlen = 3; 323 else { 324 dev_dbg(&spi->dev, "unsupported address type\n"); 325 return -EINVAL; 326 } 327 328 /* Ping the chip ... the status register is pretty portable, 329 * unlike probing manufacturer IDs. We do expect that system 330 * firmware didn't write it in the past few milliseconds! 331 */ 332 sr = spi_w8r8(spi, AT25_RDSR); 333 if (sr < 0 || sr & AT25_SR_nRDY) { 334 dev_dbg(&spi->dev, "rdsr --> %d (%02x)\n", sr, sr); 335 return -ENXIO; 336 } 337 338 at25 = devm_kzalloc(&spi->dev, sizeof(struct at25_data), GFP_KERNEL); 339 if (!at25) 340 return -ENOMEM; 341 342 mutex_init(&at25->lock); 343 at25->chip = chip; 344 at25->spi = spi; 345 spi_set_drvdata(spi, at25); 346 at25->addrlen = addrlen; 347 348 at25->nvmem_config.name = dev_name(&spi->dev); 349 at25->nvmem_config.dev = &spi->dev; 350 at25->nvmem_config.read_only = chip.flags & EE_READONLY; 351 at25->nvmem_config.root_only = true; 352 at25->nvmem_config.owner = THIS_MODULE; 353 at25->nvmem_config.compat = true; 354 at25->nvmem_config.base_dev = &spi->dev; 355 at25->nvmem_config.reg_read = at25_ee_read; 356 at25->nvmem_config.reg_write = at25_ee_write; 357 at25->nvmem_config.priv = at25; 358 at25->nvmem_config.stride = 4; 359 at25->nvmem_config.word_size = 1; 360 at25->nvmem_config.size = chip.byte_len; 361 362 at25->nvmem = nvmem_register(&at25->nvmem_config); 363 if (IS_ERR(at25->nvmem)) 364 return PTR_ERR(at25->nvmem); 365 366 dev_info(&spi->dev, "%d %s %s eeprom%s, pagesize %u\n", 367 (chip.byte_len < 1024) ? chip.byte_len : (chip.byte_len / 1024), 368 (chip.byte_len < 1024) ? "Byte" : "KByte", 369 at25->chip.name, 370 (chip.flags & EE_READONLY) ? " (readonly)" : "", 371 at25->chip.page_size); 372 return 0; 373 } 374 375 static int at25_remove(struct spi_device *spi) 376 { 377 struct at25_data *at25; 378 379 at25 = spi_get_drvdata(spi); 380 nvmem_unregister(at25->nvmem); 381 382 return 0; 383 } 384 385 /*-------------------------------------------------------------------------*/ 386 387 static const struct of_device_id at25_of_match[] = { 388 { .compatible = "atmel,at25", }, 389 { } 390 }; 391 MODULE_DEVICE_TABLE(of, at25_of_match); 392 393 static struct spi_driver at25_driver = { 394 .driver = { 395 .name = "at25", 396 .of_match_table = at25_of_match, 397 }, 398 .probe = at25_probe, 399 .remove = at25_remove, 400 }; 401 402 module_spi_driver(at25_driver); 403 404 MODULE_DESCRIPTION("Driver for most SPI EEPROMs"); 405 MODULE_AUTHOR("David Brownell"); 406 MODULE_LICENSE("GPL"); 407 MODULE_ALIAS("spi:at25"); 408