1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for most of the SPI EEPROMs, such as Atmel AT25 models 4 * and Cypress FRAMs FM25 models. 5 * 6 * Copyright (C) 2006 David Brownell 7 */ 8 9 #include <linux/bits.h> 10 #include <linux/delay.h> 11 #include <linux/device.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/property.h> 15 #include <linux/sched.h> 16 #include <linux/slab.h> 17 18 #include <linux/spi/eeprom.h> 19 #include <linux/spi/spi.h> 20 21 #include <linux/nvmem-provider.h> 22 23 /* 24 * NOTE: this is an *EEPROM* driver. The vagaries of product naming 25 * mean that some AT25 products are EEPROMs, and others are FLASH. 26 * Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver, 27 * not this one! 28 * 29 * EEPROMs that can be used with this driver include, for example: 30 * AT25M02, AT25128B 31 */ 32 33 #define FM25_SN_LEN 8 /* serial number length */ 34 #define EE_MAXADDRLEN 3 /* 24 bit addresses, up to 2 MBytes */ 35 36 struct at25_data { 37 struct spi_eeprom chip; 38 struct spi_device *spi; 39 struct mutex lock; 40 unsigned addrlen; 41 struct nvmem_config nvmem_config; 42 struct nvmem_device *nvmem; 43 u8 sernum[FM25_SN_LEN]; 44 u8 command[EE_MAXADDRLEN + 1]; 45 }; 46 47 #define AT25_WREN 0x06 /* latch the write enable */ 48 #define AT25_WRDI 0x04 /* reset the write enable */ 49 #define AT25_RDSR 0x05 /* read status register */ 50 #define AT25_WRSR 0x01 /* write status register */ 51 #define AT25_READ 0x03 /* read byte(s) */ 52 #define AT25_WRITE 0x02 /* write byte(s)/sector */ 53 #define FM25_SLEEP 0xb9 /* enter sleep mode */ 54 #define FM25_RDID 0x9f /* read device ID */ 55 #define FM25_RDSN 0xc3 /* read S/N */ 56 57 #define AT25_SR_nRDY 0x01 /* nRDY = write-in-progress */ 58 #define AT25_SR_WEN 0x02 /* write enable (latched) */ 59 #define AT25_SR_BP0 0x04 /* BP for software writeprotect */ 60 #define AT25_SR_BP1 0x08 61 #define AT25_SR_WPEN 0x80 /* writeprotect enable */ 62 63 #define AT25_INSTR_BIT3 0x08 /* additional address bit in instr */ 64 65 #define FM25_ID_LEN 9 /* ID length */ 66 67 /* 68 * Specs often allow 5ms for a page write, sometimes 20ms; 69 * it's important to recover from write timeouts. 70 */ 71 #define EE_TIMEOUT 25 72 73 /*-------------------------------------------------------------------------*/ 74 75 #define io_limit PAGE_SIZE /* bytes */ 76 77 static int at25_ee_read(void *priv, unsigned int offset, 78 void *val, size_t count) 79 { 80 struct at25_data *at25 = priv; 81 char *buf = val; 82 u8 *cp; 83 ssize_t status; 84 struct spi_transfer t[2]; 85 struct spi_message m; 86 u8 instr; 87 88 if (unlikely(offset >= at25->chip.byte_len)) 89 return -EINVAL; 90 if ((offset + count) > at25->chip.byte_len) 91 count = at25->chip.byte_len - offset; 92 if (unlikely(!count)) 93 return -EINVAL; 94 95 cp = at25->command; 96 97 instr = AT25_READ; 98 if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR) 99 if (offset >= BIT(at25->addrlen * 8)) 100 instr |= AT25_INSTR_BIT3; 101 102 mutex_lock(&at25->lock); 103 104 *cp++ = instr; 105 106 /* 8/16/24-bit address is written MSB first */ 107 switch (at25->addrlen) { 108 default: /* case 3 */ 109 *cp++ = offset >> 16; 110 fallthrough; 111 case 2: 112 *cp++ = offset >> 8; 113 fallthrough; 114 case 1: 115 case 0: /* can't happen: for better code generation */ 116 *cp++ = offset >> 0; 117 } 118 119 spi_message_init(&m); 120 memset(t, 0, sizeof(t)); 121 122 t[0].tx_buf = at25->command; 123 t[0].len = at25->addrlen + 1; 124 spi_message_add_tail(&t[0], &m); 125 126 t[1].rx_buf = buf; 127 t[1].len = count; 128 spi_message_add_tail(&t[1], &m); 129 130 /* 131 * Read it all at once. 132 * 133 * REVISIT that's potentially a problem with large chips, if 134 * other devices on the bus need to be accessed regularly or 135 * this chip is clocked very slowly. 136 */ 137 status = spi_sync(at25->spi, &m); 138 dev_dbg(&at25->spi->dev, "read %zu bytes at %d --> %zd\n", 139 count, offset, status); 140 141 mutex_unlock(&at25->lock); 142 return status; 143 } 144 145 /* Read extra registers as ID or serial number */ 146 static int fm25_aux_read(struct at25_data *at25, u8 *buf, uint8_t command, 147 int len) 148 { 149 int status; 150 struct spi_transfer t[2]; 151 struct spi_message m; 152 153 spi_message_init(&m); 154 memset(t, 0, sizeof(t)); 155 156 t[0].tx_buf = at25->command; 157 t[0].len = 1; 158 spi_message_add_tail(&t[0], &m); 159 160 t[1].rx_buf = buf; 161 t[1].len = len; 162 spi_message_add_tail(&t[1], &m); 163 164 mutex_lock(&at25->lock); 165 166 at25->command[0] = command; 167 168 status = spi_sync(at25->spi, &m); 169 dev_dbg(&at25->spi->dev, "read %d aux bytes --> %d\n", len, status); 170 171 mutex_unlock(&at25->lock); 172 return status; 173 } 174 175 static ssize_t sernum_show(struct device *dev, struct device_attribute *attr, char *buf) 176 { 177 struct at25_data *at25; 178 179 at25 = dev_get_drvdata(dev); 180 return sysfs_emit(buf, "%*ph\n", (int)sizeof(at25->sernum), at25->sernum); 181 } 182 static DEVICE_ATTR_RO(sernum); 183 184 static struct attribute *sernum_attrs[] = { 185 &dev_attr_sernum.attr, 186 NULL, 187 }; 188 ATTRIBUTE_GROUPS(sernum); 189 190 static int at25_ee_write(void *priv, unsigned int off, void *val, size_t count) 191 { 192 struct at25_data *at25 = priv; 193 const char *buf = val; 194 int status = 0; 195 unsigned buf_size; 196 u8 *bounce; 197 198 if (unlikely(off >= at25->chip.byte_len)) 199 return -EFBIG; 200 if ((off + count) > at25->chip.byte_len) 201 count = at25->chip.byte_len - off; 202 if (unlikely(!count)) 203 return -EINVAL; 204 205 /* Temp buffer starts with command and address */ 206 buf_size = at25->chip.page_size; 207 if (buf_size > io_limit) 208 buf_size = io_limit; 209 bounce = kmalloc(buf_size + at25->addrlen + 1, GFP_KERNEL); 210 if (!bounce) 211 return -ENOMEM; 212 213 /* 214 * For write, rollover is within the page ... so we write at 215 * most one page, then manually roll over to the next page. 216 */ 217 mutex_lock(&at25->lock); 218 do { 219 unsigned long timeout, retries; 220 unsigned segment; 221 unsigned offset = (unsigned) off; 222 u8 *cp = bounce; 223 int sr; 224 u8 instr; 225 226 *cp = AT25_WREN; 227 status = spi_write(at25->spi, cp, 1); 228 if (status < 0) { 229 dev_dbg(&at25->spi->dev, "WREN --> %d\n", status); 230 break; 231 } 232 233 instr = AT25_WRITE; 234 if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR) 235 if (offset >= BIT(at25->addrlen * 8)) 236 instr |= AT25_INSTR_BIT3; 237 *cp++ = instr; 238 239 /* 8/16/24-bit address is written MSB first */ 240 switch (at25->addrlen) { 241 default: /* case 3 */ 242 *cp++ = offset >> 16; 243 fallthrough; 244 case 2: 245 *cp++ = offset >> 8; 246 fallthrough; 247 case 1: 248 case 0: /* can't happen: for better code generation */ 249 *cp++ = offset >> 0; 250 } 251 252 /* Write as much of a page as we can */ 253 segment = buf_size - (offset % buf_size); 254 if (segment > count) 255 segment = count; 256 memcpy(cp, buf, segment); 257 status = spi_write(at25->spi, bounce, 258 segment + at25->addrlen + 1); 259 dev_dbg(&at25->spi->dev, "write %u bytes at %u --> %d\n", 260 segment, offset, status); 261 if (status < 0) 262 break; 263 264 /* 265 * REVISIT this should detect (or prevent) failed writes 266 * to read-only sections of the EEPROM... 267 */ 268 269 /* Wait for non-busy status */ 270 timeout = jiffies + msecs_to_jiffies(EE_TIMEOUT); 271 retries = 0; 272 do { 273 274 sr = spi_w8r8(at25->spi, AT25_RDSR); 275 if (sr < 0 || (sr & AT25_SR_nRDY)) { 276 dev_dbg(&at25->spi->dev, 277 "rdsr --> %d (%02x)\n", sr, sr); 278 /* at HZ=100, this is sloooow */ 279 msleep(1); 280 continue; 281 } 282 if (!(sr & AT25_SR_nRDY)) 283 break; 284 } while (retries++ < 3 || time_before_eq(jiffies, timeout)); 285 286 if ((sr < 0) || (sr & AT25_SR_nRDY)) { 287 dev_err(&at25->spi->dev, 288 "write %u bytes offset %u, timeout after %u msecs\n", 289 segment, offset, 290 jiffies_to_msecs(jiffies - 291 (timeout - EE_TIMEOUT))); 292 status = -ETIMEDOUT; 293 break; 294 } 295 296 off += segment; 297 buf += segment; 298 count -= segment; 299 300 } while (count > 0); 301 302 mutex_unlock(&at25->lock); 303 304 kfree(bounce); 305 return status; 306 } 307 308 /*-------------------------------------------------------------------------*/ 309 310 static int at25_fw_to_chip(struct device *dev, struct spi_eeprom *chip) 311 { 312 u32 val; 313 int err; 314 315 strscpy(chip->name, "at25", sizeof(chip->name)); 316 317 err = device_property_read_u32(dev, "size", &val); 318 if (err) 319 err = device_property_read_u32(dev, "at25,byte-len", &val); 320 if (err) { 321 dev_err(dev, "Error: missing \"size\" property\n"); 322 return err; 323 } 324 chip->byte_len = val; 325 326 err = device_property_read_u32(dev, "pagesize", &val); 327 if (err) 328 err = device_property_read_u32(dev, "at25,page-size", &val); 329 if (err) { 330 dev_err(dev, "Error: missing \"pagesize\" property\n"); 331 return err; 332 } 333 chip->page_size = val; 334 335 err = device_property_read_u32(dev, "address-width", &val); 336 if (err) { 337 err = device_property_read_u32(dev, "at25,addr-mode", &val); 338 if (err) { 339 dev_err(dev, "Error: missing \"address-width\" property\n"); 340 return err; 341 } 342 chip->flags = (u16)val; 343 } else { 344 switch (val) { 345 case 9: 346 chip->flags |= EE_INSTR_BIT3_IS_ADDR; 347 fallthrough; 348 case 8: 349 chip->flags |= EE_ADDR1; 350 break; 351 case 16: 352 chip->flags |= EE_ADDR2; 353 break; 354 case 24: 355 chip->flags |= EE_ADDR3; 356 break; 357 default: 358 dev_err(dev, 359 "Error: bad \"address-width\" property: %u\n", 360 val); 361 return -ENODEV; 362 } 363 if (device_property_present(dev, "read-only")) 364 chip->flags |= EE_READONLY; 365 } 366 return 0; 367 } 368 369 static int at25_fram_to_chip(struct device *dev, struct spi_eeprom *chip) 370 { 371 struct at25_data *at25 = container_of(chip, struct at25_data, chip); 372 u8 sernum[FM25_SN_LEN]; 373 u8 id[FM25_ID_LEN]; 374 int i; 375 376 strscpy(chip->name, "fm25", sizeof(chip->name)); 377 378 /* Get ID of chip */ 379 fm25_aux_read(at25, id, FM25_RDID, FM25_ID_LEN); 380 if (id[6] != 0xc2) { 381 dev_err(dev, "Error: no Cypress FRAM (id %02x)\n", id[6]); 382 return -ENODEV; 383 } 384 /* Set size found in ID */ 385 if (id[7] < 0x21 || id[7] > 0x26) { 386 dev_err(dev, "Error: unsupported size (id %02x)\n", id[7]); 387 return -ENODEV; 388 } 389 390 chip->byte_len = BIT(id[7] - 0x21 + 4) * 1024; 391 if (chip->byte_len > 64 * 1024) 392 chip->flags |= EE_ADDR3; 393 else 394 chip->flags |= EE_ADDR2; 395 396 if (id[8]) { 397 fm25_aux_read(at25, sernum, FM25_RDSN, FM25_SN_LEN); 398 /* Swap byte order */ 399 for (i = 0; i < FM25_SN_LEN; i++) 400 at25->sernum[i] = sernum[FM25_SN_LEN - 1 - i]; 401 } 402 403 chip->page_size = PAGE_SIZE; 404 return 0; 405 } 406 407 static const struct of_device_id at25_of_match[] = { 408 { .compatible = "atmel,at25" }, 409 { .compatible = "cypress,fm25" }, 410 { } 411 }; 412 MODULE_DEVICE_TABLE(of, at25_of_match); 413 414 static const struct spi_device_id at25_spi_ids[] = { 415 { .name = "at25" }, 416 { .name = "fm25" }, 417 { } 418 }; 419 MODULE_DEVICE_TABLE(spi, at25_spi_ids); 420 421 static int at25_probe(struct spi_device *spi) 422 { 423 struct at25_data *at25 = NULL; 424 int err; 425 int sr; 426 struct spi_eeprom *pdata; 427 bool is_fram; 428 429 err = device_property_match_string(&spi->dev, "compatible", "cypress,fm25"); 430 if (err >= 0) 431 is_fram = true; 432 else 433 is_fram = false; 434 435 /* 436 * Ping the chip ... the status register is pretty portable, 437 * unlike probing manufacturer IDs. We do expect that system 438 * firmware didn't write it in the past few milliseconds! 439 */ 440 sr = spi_w8r8(spi, AT25_RDSR); 441 if (sr < 0 || sr & AT25_SR_nRDY) { 442 dev_dbg(&spi->dev, "rdsr --> %d (%02x)\n", sr, sr); 443 return -ENXIO; 444 } 445 446 at25 = devm_kzalloc(&spi->dev, sizeof(*at25), GFP_KERNEL); 447 if (!at25) 448 return -ENOMEM; 449 450 mutex_init(&at25->lock); 451 at25->spi = spi; 452 spi_set_drvdata(spi, at25); 453 454 /* Chip description */ 455 pdata = dev_get_platdata(&spi->dev); 456 if (pdata) { 457 at25->chip = *pdata; 458 } else { 459 if (is_fram) 460 err = at25_fram_to_chip(&spi->dev, &at25->chip); 461 else 462 err = at25_fw_to_chip(&spi->dev, &at25->chip); 463 if (err) 464 return err; 465 } 466 467 /* For now we only support 8/16/24 bit addressing */ 468 if (at25->chip.flags & EE_ADDR1) 469 at25->addrlen = 1; 470 else if (at25->chip.flags & EE_ADDR2) 471 at25->addrlen = 2; 472 else if (at25->chip.flags & EE_ADDR3) 473 at25->addrlen = 3; 474 else { 475 dev_dbg(&spi->dev, "unsupported address type\n"); 476 return -EINVAL; 477 } 478 479 at25->nvmem_config.type = is_fram ? NVMEM_TYPE_FRAM : NVMEM_TYPE_EEPROM; 480 at25->nvmem_config.name = dev_name(&spi->dev); 481 at25->nvmem_config.dev = &spi->dev; 482 at25->nvmem_config.read_only = at25->chip.flags & EE_READONLY; 483 at25->nvmem_config.root_only = true; 484 at25->nvmem_config.owner = THIS_MODULE; 485 at25->nvmem_config.compat = true; 486 at25->nvmem_config.base_dev = &spi->dev; 487 at25->nvmem_config.reg_read = at25_ee_read; 488 at25->nvmem_config.reg_write = at25_ee_write; 489 at25->nvmem_config.priv = at25; 490 at25->nvmem_config.stride = 1; 491 at25->nvmem_config.word_size = 1; 492 at25->nvmem_config.size = at25->chip.byte_len; 493 494 at25->nvmem = devm_nvmem_register(&spi->dev, &at25->nvmem_config); 495 if (IS_ERR(at25->nvmem)) 496 return PTR_ERR(at25->nvmem); 497 498 dev_info(&spi->dev, "%d %s %s %s%s, pagesize %u\n", 499 (at25->chip.byte_len < 1024) ? 500 at25->chip.byte_len : (at25->chip.byte_len / 1024), 501 (at25->chip.byte_len < 1024) ? "Byte" : "KByte", 502 at25->chip.name, is_fram ? "fram" : "eeprom", 503 (at25->chip.flags & EE_READONLY) ? " (readonly)" : "", 504 at25->chip.page_size); 505 return 0; 506 } 507 508 /*-------------------------------------------------------------------------*/ 509 510 static struct spi_driver at25_driver = { 511 .driver = { 512 .name = "at25", 513 .of_match_table = at25_of_match, 514 .dev_groups = sernum_groups, 515 }, 516 .probe = at25_probe, 517 .id_table = at25_spi_ids, 518 }; 519 520 module_spi_driver(at25_driver); 521 522 MODULE_DESCRIPTION("Driver for most SPI EEPROMs"); 523 MODULE_AUTHOR("David Brownell"); 524 MODULE_LICENSE("GPL"); 525 MODULE_ALIAS("spi:at25"); 526