1 /* 2 * at25.c -- support most SPI EEPROMs, such as Atmel AT25 models 3 * 4 * Copyright (C) 2006 David Brownell 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/slab.h> 15 #include <linux/delay.h> 16 #include <linux/device.h> 17 #include <linux/sched.h> 18 19 #include <linux/nvmem-provider.h> 20 #include <linux/spi/spi.h> 21 #include <linux/spi/eeprom.h> 22 #include <linux/property.h> 23 24 /* 25 * NOTE: this is an *EEPROM* driver. The vagaries of product naming 26 * mean that some AT25 products are EEPROMs, and others are FLASH. 27 * Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver, 28 * not this one! 29 */ 30 31 struct at25_data { 32 struct spi_device *spi; 33 struct mutex lock; 34 struct spi_eeprom chip; 35 unsigned addrlen; 36 struct nvmem_config nvmem_config; 37 struct nvmem_device *nvmem; 38 }; 39 40 #define AT25_WREN 0x06 /* latch the write enable */ 41 #define AT25_WRDI 0x04 /* reset the write enable */ 42 #define AT25_RDSR 0x05 /* read status register */ 43 #define AT25_WRSR 0x01 /* write status register */ 44 #define AT25_READ 0x03 /* read byte(s) */ 45 #define AT25_WRITE 0x02 /* write byte(s)/sector */ 46 47 #define AT25_SR_nRDY 0x01 /* nRDY = write-in-progress */ 48 #define AT25_SR_WEN 0x02 /* write enable (latched) */ 49 #define AT25_SR_BP0 0x04 /* BP for software writeprotect */ 50 #define AT25_SR_BP1 0x08 51 #define AT25_SR_WPEN 0x80 /* writeprotect enable */ 52 53 #define AT25_INSTR_BIT3 0x08 /* Additional address bit in instr */ 54 55 #define EE_MAXADDRLEN 3 /* 24 bit addresses, up to 2 MBytes */ 56 57 /* Specs often allow 5 msec for a page write, sometimes 20 msec; 58 * it's important to recover from write timeouts. 59 */ 60 #define EE_TIMEOUT 25 61 62 /*-------------------------------------------------------------------------*/ 63 64 #define io_limit PAGE_SIZE /* bytes */ 65 66 static int at25_ee_read(void *priv, unsigned int offset, 67 void *val, size_t count) 68 { 69 struct at25_data *at25 = priv; 70 char *buf = val; 71 u8 command[EE_MAXADDRLEN + 1]; 72 u8 *cp; 73 ssize_t status; 74 struct spi_transfer t[2]; 75 struct spi_message m; 76 u8 instr; 77 78 if (unlikely(offset >= at25->chip.byte_len)) 79 return -EINVAL; 80 if ((offset + count) > at25->chip.byte_len) 81 count = at25->chip.byte_len - offset; 82 if (unlikely(!count)) 83 return -EINVAL; 84 85 cp = command; 86 87 instr = AT25_READ; 88 if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR) 89 if (offset >= (1U << (at25->addrlen * 8))) 90 instr |= AT25_INSTR_BIT3; 91 *cp++ = instr; 92 93 /* 8/16/24-bit address is written MSB first */ 94 switch (at25->addrlen) { 95 default: /* case 3 */ 96 *cp++ = offset >> 16; 97 case 2: 98 *cp++ = offset >> 8; 99 case 1: 100 case 0: /* can't happen: for better codegen */ 101 *cp++ = offset >> 0; 102 } 103 104 spi_message_init(&m); 105 memset(t, 0, sizeof t); 106 107 t[0].tx_buf = command; 108 t[0].len = at25->addrlen + 1; 109 spi_message_add_tail(&t[0], &m); 110 111 t[1].rx_buf = buf; 112 t[1].len = count; 113 spi_message_add_tail(&t[1], &m); 114 115 mutex_lock(&at25->lock); 116 117 /* Read it all at once. 118 * 119 * REVISIT that's potentially a problem with large chips, if 120 * other devices on the bus need to be accessed regularly or 121 * this chip is clocked very slowly 122 */ 123 status = spi_sync(at25->spi, &m); 124 dev_dbg(&at25->spi->dev, 125 "read %Zd bytes at %d --> %d\n", 126 count, offset, (int) status); 127 128 mutex_unlock(&at25->lock); 129 return status; 130 } 131 132 static int at25_ee_write(void *priv, unsigned int off, void *val, size_t count) 133 { 134 struct at25_data *at25 = priv; 135 const char *buf = val; 136 int status = 0; 137 unsigned buf_size; 138 u8 *bounce; 139 140 if (unlikely(off >= at25->chip.byte_len)) 141 return -EFBIG; 142 if ((off + count) > at25->chip.byte_len) 143 count = at25->chip.byte_len - off; 144 if (unlikely(!count)) 145 return -EINVAL; 146 147 /* Temp buffer starts with command and address */ 148 buf_size = at25->chip.page_size; 149 if (buf_size > io_limit) 150 buf_size = io_limit; 151 bounce = kmalloc(buf_size + at25->addrlen + 1, GFP_KERNEL); 152 if (!bounce) 153 return -ENOMEM; 154 155 /* For write, rollover is within the page ... so we write at 156 * most one page, then manually roll over to the next page. 157 */ 158 mutex_lock(&at25->lock); 159 do { 160 unsigned long timeout, retries; 161 unsigned segment; 162 unsigned offset = (unsigned) off; 163 u8 *cp = bounce; 164 int sr; 165 u8 instr; 166 167 *cp = AT25_WREN; 168 status = spi_write(at25->spi, cp, 1); 169 if (status < 0) { 170 dev_dbg(&at25->spi->dev, "WREN --> %d\n", 171 (int) status); 172 break; 173 } 174 175 instr = AT25_WRITE; 176 if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR) 177 if (offset >= (1U << (at25->addrlen * 8))) 178 instr |= AT25_INSTR_BIT3; 179 *cp++ = instr; 180 181 /* 8/16/24-bit address is written MSB first */ 182 switch (at25->addrlen) { 183 default: /* case 3 */ 184 *cp++ = offset >> 16; 185 case 2: 186 *cp++ = offset >> 8; 187 case 1: 188 case 0: /* can't happen: for better codegen */ 189 *cp++ = offset >> 0; 190 } 191 192 /* Write as much of a page as we can */ 193 segment = buf_size - (offset % buf_size); 194 if (segment > count) 195 segment = count; 196 memcpy(cp, buf, segment); 197 status = spi_write(at25->spi, bounce, 198 segment + at25->addrlen + 1); 199 dev_dbg(&at25->spi->dev, 200 "write %u bytes at %u --> %d\n", 201 segment, offset, (int) status); 202 if (status < 0) 203 break; 204 205 /* REVISIT this should detect (or prevent) failed writes 206 * to readonly sections of the EEPROM... 207 */ 208 209 /* Wait for non-busy status */ 210 timeout = jiffies + msecs_to_jiffies(EE_TIMEOUT); 211 retries = 0; 212 do { 213 214 sr = spi_w8r8(at25->spi, AT25_RDSR); 215 if (sr < 0 || (sr & AT25_SR_nRDY)) { 216 dev_dbg(&at25->spi->dev, 217 "rdsr --> %d (%02x)\n", sr, sr); 218 /* at HZ=100, this is sloooow */ 219 msleep(1); 220 continue; 221 } 222 if (!(sr & AT25_SR_nRDY)) 223 break; 224 } while (retries++ < 3 || time_before_eq(jiffies, timeout)); 225 226 if ((sr < 0) || (sr & AT25_SR_nRDY)) { 227 dev_err(&at25->spi->dev, 228 "write %d bytes offset %d, " 229 "timeout after %u msecs\n", 230 segment, offset, 231 jiffies_to_msecs(jiffies - 232 (timeout - EE_TIMEOUT))); 233 status = -ETIMEDOUT; 234 break; 235 } 236 237 off += segment; 238 buf += segment; 239 count -= segment; 240 241 } while (count > 0); 242 243 mutex_unlock(&at25->lock); 244 245 kfree(bounce); 246 return status; 247 } 248 249 /*-------------------------------------------------------------------------*/ 250 251 static int at25_fw_to_chip(struct device *dev, struct spi_eeprom *chip) 252 { 253 u32 val; 254 255 memset(chip, 0, sizeof(*chip)); 256 strncpy(chip->name, "at25", sizeof(chip->name)); 257 258 if (device_property_read_u32(dev, "size", &val) == 0 || 259 device_property_read_u32(dev, "at25,byte-len", &val) == 0) { 260 chip->byte_len = val; 261 } else { 262 dev_err(dev, "Error: missing \"size\" property\n"); 263 return -ENODEV; 264 } 265 266 if (device_property_read_u32(dev, "pagesize", &val) == 0 || 267 device_property_read_u32(dev, "at25,page-size", &val) == 0) { 268 chip->page_size = (u16)val; 269 } else { 270 dev_err(dev, "Error: missing \"pagesize\" property\n"); 271 return -ENODEV; 272 } 273 274 if (device_property_read_u32(dev, "at25,addr-mode", &val) == 0) { 275 chip->flags = (u16)val; 276 } else { 277 if (device_property_read_u32(dev, "address-width", &val)) { 278 dev_err(dev, 279 "Error: missing \"address-width\" property\n"); 280 return -ENODEV; 281 } 282 switch (val) { 283 case 8: 284 chip->flags |= EE_ADDR1; 285 break; 286 case 16: 287 chip->flags |= EE_ADDR2; 288 break; 289 case 24: 290 chip->flags |= EE_ADDR3; 291 break; 292 default: 293 dev_err(dev, 294 "Error: bad \"address-width\" property: %u\n", 295 val); 296 return -ENODEV; 297 } 298 if (device_property_present(dev, "read-only")) 299 chip->flags |= EE_READONLY; 300 } 301 return 0; 302 } 303 304 static int at25_probe(struct spi_device *spi) 305 { 306 struct at25_data *at25 = NULL; 307 struct spi_eeprom chip; 308 int err; 309 int sr; 310 int addrlen; 311 312 /* Chip description */ 313 if (!spi->dev.platform_data) { 314 err = at25_fw_to_chip(&spi->dev, &chip); 315 if (err) 316 return err; 317 } else 318 chip = *(struct spi_eeprom *)spi->dev.platform_data; 319 320 /* For now we only support 8/16/24 bit addressing */ 321 if (chip.flags & EE_ADDR1) 322 addrlen = 1; 323 else if (chip.flags & EE_ADDR2) 324 addrlen = 2; 325 else if (chip.flags & EE_ADDR3) 326 addrlen = 3; 327 else { 328 dev_dbg(&spi->dev, "unsupported address type\n"); 329 return -EINVAL; 330 } 331 332 /* Ping the chip ... the status register is pretty portable, 333 * unlike probing manufacturer IDs. We do expect that system 334 * firmware didn't write it in the past few milliseconds! 335 */ 336 sr = spi_w8r8(spi, AT25_RDSR); 337 if (sr < 0 || sr & AT25_SR_nRDY) { 338 dev_dbg(&spi->dev, "rdsr --> %d (%02x)\n", sr, sr); 339 return -ENXIO; 340 } 341 342 at25 = devm_kzalloc(&spi->dev, sizeof(struct at25_data), GFP_KERNEL); 343 if (!at25) 344 return -ENOMEM; 345 346 mutex_init(&at25->lock); 347 at25->chip = chip; 348 at25->spi = spi; 349 spi_set_drvdata(spi, at25); 350 at25->addrlen = addrlen; 351 352 at25->nvmem_config.name = dev_name(&spi->dev); 353 at25->nvmem_config.dev = &spi->dev; 354 at25->nvmem_config.read_only = chip.flags & EE_READONLY; 355 at25->nvmem_config.root_only = true; 356 at25->nvmem_config.owner = THIS_MODULE; 357 at25->nvmem_config.compat = true; 358 at25->nvmem_config.base_dev = &spi->dev; 359 at25->nvmem_config.reg_read = at25_ee_read; 360 at25->nvmem_config.reg_write = at25_ee_write; 361 at25->nvmem_config.priv = at25; 362 at25->nvmem_config.stride = 4; 363 at25->nvmem_config.word_size = 1; 364 at25->nvmem_config.size = chip.byte_len; 365 366 at25->nvmem = nvmem_register(&at25->nvmem_config); 367 if (IS_ERR(at25->nvmem)) 368 return PTR_ERR(at25->nvmem); 369 370 dev_info(&spi->dev, "%d %s %s eeprom%s, pagesize %u\n", 371 (chip.byte_len < 1024) 372 ? chip.byte_len 373 : (chip.byte_len / 1024), 374 (chip.byte_len < 1024) ? "Byte" : "KByte", 375 at25->chip.name, 376 (chip.flags & EE_READONLY) ? " (readonly)" : "", 377 at25->chip.page_size); 378 return 0; 379 } 380 381 static int at25_remove(struct spi_device *spi) 382 { 383 struct at25_data *at25; 384 385 at25 = spi_get_drvdata(spi); 386 nvmem_unregister(at25->nvmem); 387 388 return 0; 389 } 390 391 /*-------------------------------------------------------------------------*/ 392 393 static const struct of_device_id at25_of_match[] = { 394 { .compatible = "atmel,at25", }, 395 { } 396 }; 397 MODULE_DEVICE_TABLE(of, at25_of_match); 398 399 static struct spi_driver at25_driver = { 400 .driver = { 401 .name = "at25", 402 .of_match_table = at25_of_match, 403 }, 404 .probe = at25_probe, 405 .remove = at25_remove, 406 }; 407 408 module_spi_driver(at25_driver); 409 410 MODULE_DESCRIPTION("Driver for most SPI EEPROMs"); 411 MODULE_AUTHOR("David Brownell"); 412 MODULE_LICENSE("GPL"); 413 MODULE_ALIAS("spi:at25"); 414