1 /* 2 * Copyright 2014 IBM Corp. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 */ 9 10 #include <linux/pci.h> 11 #include <misc/cxl.h> 12 #include "cxl.h" 13 14 static int cxl_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 15 { 16 if (dma_mask < DMA_BIT_MASK(64)) { 17 pr_info("%s only 64bit DMA supported on CXL", __func__); 18 return -EIO; 19 } 20 21 *(pdev->dev.dma_mask) = dma_mask; 22 return 0; 23 } 24 25 static int cxl_pci_probe_mode(struct pci_bus *bus) 26 { 27 return PCI_PROBE_NORMAL; 28 } 29 30 static int cxl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) 31 { 32 return -ENODEV; 33 } 34 35 static void cxl_teardown_msi_irqs(struct pci_dev *pdev) 36 { 37 /* 38 * MSI should never be set but need still need to provide this call 39 * back. 40 */ 41 } 42 43 static bool cxl_pci_enable_device_hook(struct pci_dev *dev) 44 { 45 struct pci_controller *phb; 46 struct cxl_afu *afu; 47 struct cxl_context *ctx; 48 49 phb = pci_bus_to_host(dev->bus); 50 afu = (struct cxl_afu *)phb->private_data; 51 52 if (!cxl_ops->link_ok(afu->adapter, afu)) { 53 dev_warn(&dev->dev, "%s: Device link is down, refusing to enable AFU\n", __func__); 54 return false; 55 } 56 57 set_dma_ops(&dev->dev, &dma_direct_ops); 58 set_dma_offset(&dev->dev, PAGE_OFFSET); 59 60 /* 61 * Allocate a context to do cxl things too. If we eventually do real 62 * DMA ops, we'll need a default context to attach them to 63 */ 64 ctx = cxl_dev_context_init(dev); 65 if (!ctx) 66 return false; 67 dev->dev.archdata.cxl_ctx = ctx; 68 69 return (cxl_ops->afu_check_and_enable(afu) == 0); 70 } 71 72 static void cxl_pci_disable_device(struct pci_dev *dev) 73 { 74 struct cxl_context *ctx = cxl_get_context(dev); 75 76 if (ctx) { 77 if (ctx->status == STARTED) { 78 dev_err(&dev->dev, "Default context started\n"); 79 return; 80 } 81 dev->dev.archdata.cxl_ctx = NULL; 82 cxl_release_context(ctx); 83 } 84 } 85 86 static resource_size_t cxl_pci_window_alignment(struct pci_bus *bus, 87 unsigned long type) 88 { 89 return 1; 90 } 91 92 static void cxl_pci_reset_secondary_bus(struct pci_dev *dev) 93 { 94 /* Should we do an AFU reset here ? */ 95 } 96 97 static int cxl_pcie_cfg_record(u8 bus, u8 devfn) 98 { 99 return (bus << 8) + devfn; 100 } 101 102 static int cxl_pcie_config_info(struct pci_bus *bus, unsigned int devfn, 103 struct cxl_afu **_afu, int *_record) 104 { 105 struct pci_controller *phb; 106 struct cxl_afu *afu; 107 int record; 108 109 phb = pci_bus_to_host(bus); 110 if (phb == NULL) 111 return PCIBIOS_DEVICE_NOT_FOUND; 112 113 afu = (struct cxl_afu *)phb->private_data; 114 record = cxl_pcie_cfg_record(bus->number, devfn); 115 if (record > afu->crs_num) 116 return PCIBIOS_DEVICE_NOT_FOUND; 117 118 *_afu = afu; 119 *_record = record; 120 return 0; 121 } 122 123 static int cxl_pcie_read_config(struct pci_bus *bus, unsigned int devfn, 124 int offset, int len, u32 *val) 125 { 126 int rc, record; 127 struct cxl_afu *afu; 128 u8 val8; 129 u16 val16; 130 u32 val32; 131 132 rc = cxl_pcie_config_info(bus, devfn, &afu, &record); 133 if (rc) 134 return rc; 135 136 switch (len) { 137 case 1: 138 rc = cxl_ops->afu_cr_read8(afu, record, offset, &val8); 139 *val = val8; 140 break; 141 case 2: 142 rc = cxl_ops->afu_cr_read16(afu, record, offset, &val16); 143 *val = val16; 144 break; 145 case 4: 146 rc = cxl_ops->afu_cr_read32(afu, record, offset, &val32); 147 *val = val32; 148 break; 149 default: 150 WARN_ON(1); 151 } 152 153 if (rc) 154 return PCIBIOS_DEVICE_NOT_FOUND; 155 156 return PCIBIOS_SUCCESSFUL; 157 } 158 159 static int cxl_pcie_write_config(struct pci_bus *bus, unsigned int devfn, 160 int offset, int len, u32 val) 161 { 162 int rc, record; 163 struct cxl_afu *afu; 164 165 rc = cxl_pcie_config_info(bus, devfn, &afu, &record); 166 if (rc) 167 return rc; 168 169 switch (len) { 170 case 1: 171 rc = cxl_ops->afu_cr_write8(afu, record, offset, val & 0xff); 172 break; 173 case 2: 174 rc = cxl_ops->afu_cr_write16(afu, record, offset, val & 0xffff); 175 break; 176 case 4: 177 rc = cxl_ops->afu_cr_write32(afu, record, offset, val); 178 break; 179 default: 180 WARN_ON(1); 181 } 182 183 if (rc) 184 return PCIBIOS_SET_FAILED; 185 186 return PCIBIOS_SUCCESSFUL; 187 } 188 189 static struct pci_ops cxl_pcie_pci_ops = 190 { 191 .read = cxl_pcie_read_config, 192 .write = cxl_pcie_write_config, 193 }; 194 195 196 static struct pci_controller_ops cxl_pci_controller_ops = 197 { 198 .probe_mode = cxl_pci_probe_mode, 199 .enable_device_hook = cxl_pci_enable_device_hook, 200 .disable_device = cxl_pci_disable_device, 201 .release_device = cxl_pci_disable_device, 202 .window_alignment = cxl_pci_window_alignment, 203 .reset_secondary_bus = cxl_pci_reset_secondary_bus, 204 .setup_msi_irqs = cxl_setup_msi_irqs, 205 .teardown_msi_irqs = cxl_teardown_msi_irqs, 206 .dma_set_mask = cxl_dma_set_mask, 207 }; 208 209 int cxl_pci_vphb_add(struct cxl_afu *afu) 210 { 211 struct pci_dev *phys_dev; 212 struct pci_controller *phb, *phys_phb; 213 struct device_node *vphb_dn; 214 struct device *parent; 215 216 if (cpu_has_feature(CPU_FTR_HVMODE)) { 217 phys_dev = to_pci_dev(afu->adapter->dev.parent); 218 phys_phb = pci_bus_to_host(phys_dev->bus); 219 vphb_dn = phys_phb->dn; 220 parent = &phys_dev->dev; 221 } else { 222 vphb_dn = afu->adapter->dev.parent->of_node; 223 parent = afu->adapter->dev.parent; 224 } 225 226 /* Alloc and setup PHB data structure */ 227 phb = pcibios_alloc_controller(vphb_dn); 228 if (!phb) 229 return -ENODEV; 230 231 /* Setup parent in sysfs */ 232 phb->parent = parent; 233 234 /* Setup the PHB using arch provided callback */ 235 phb->ops = &cxl_pcie_pci_ops; 236 phb->cfg_addr = NULL; 237 phb->cfg_data = 0; 238 phb->private_data = afu; 239 phb->controller_ops = cxl_pci_controller_ops; 240 241 /* Scan the bus */ 242 pcibios_scan_phb(phb); 243 if (phb->bus == NULL) 244 return -ENXIO; 245 246 /* Claim resources. This might need some rework as well depending 247 * whether we are doing probe-only or not, like assigning unassigned 248 * resources etc... 249 */ 250 pcibios_claim_one_bus(phb->bus); 251 252 /* Add probed PCI devices to the device model */ 253 pci_bus_add_devices(phb->bus); 254 255 afu->phb = phb; 256 257 return 0; 258 } 259 260 void cxl_pci_vphb_remove(struct cxl_afu *afu) 261 { 262 struct pci_controller *phb; 263 264 /* If there is no configuration record we won't have one of these */ 265 if (!afu || !afu->phb) 266 return; 267 268 phb = afu->phb; 269 afu->phb = NULL; 270 271 pci_remove_root_bus(phb->bus); 272 pcibios_free_controller(phb); 273 } 274 275 bool cxl_pci_is_vphb_device(struct pci_dev *dev) 276 { 277 struct pci_controller *phb; 278 279 phb = pci_bus_to_host(dev->bus); 280 281 return (phb->ops == &cxl_pcie_pci_ops); 282 } 283 284 struct cxl_afu *cxl_pci_to_afu(struct pci_dev *dev) 285 { 286 struct pci_controller *phb; 287 288 phb = pci_bus_to_host(dev->bus); 289 290 return (struct cxl_afu *)phb->private_data; 291 } 292 EXPORT_SYMBOL_GPL(cxl_pci_to_afu); 293 294 unsigned int cxl_pci_to_cfg_record(struct pci_dev *dev) 295 { 296 return cxl_pcie_cfg_record(dev->bus->number, dev->devfn); 297 } 298 EXPORT_SYMBOL_GPL(cxl_pci_to_cfg_record); 299