1 /* 2 * Copyright 2014 IBM Corp. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 */ 9 10 #include <linux/pci_regs.h> 11 #include <linux/pci_ids.h> 12 #include <linux/device.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/slab.h> 16 #include <linux/sort.h> 17 #include <linux/pci.h> 18 #include <linux/of.h> 19 #include <linux/delay.h> 20 #include <asm/opal.h> 21 #include <asm/msi_bitmap.h> 22 #include <asm/pnv-pci.h> 23 #include <asm/io.h> 24 #include <asm/reg.h> 25 26 #include "cxl.h" 27 #include <misc/cxl.h> 28 29 30 #define CXL_PCI_VSEC_ID 0x1280 31 #define CXL_VSEC_MIN_SIZE 0x80 32 33 #define CXL_READ_VSEC_LENGTH(dev, vsec, dest) \ 34 { \ 35 pci_read_config_word(dev, vsec + 0x6, dest); \ 36 *dest >>= 4; \ 37 } 38 #define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \ 39 pci_read_config_byte(dev, vsec + 0x8, dest) 40 41 #define CXL_READ_VSEC_STATUS(dev, vsec, dest) \ 42 pci_read_config_byte(dev, vsec + 0x9, dest) 43 #define CXL_STATUS_SECOND_PORT 0x80 44 #define CXL_STATUS_MSI_X_FULL 0x40 45 #define CXL_STATUS_MSI_X_SINGLE 0x20 46 #define CXL_STATUS_FLASH_RW 0x08 47 #define CXL_STATUS_FLASH_RO 0x04 48 #define CXL_STATUS_LOADABLE_AFU 0x02 49 #define CXL_STATUS_LOADABLE_PSL 0x01 50 /* If we see these features we won't try to use the card */ 51 #define CXL_UNSUPPORTED_FEATURES \ 52 (CXL_STATUS_MSI_X_FULL | CXL_STATUS_MSI_X_SINGLE) 53 54 #define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \ 55 pci_read_config_byte(dev, vsec + 0xa, dest) 56 #define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \ 57 pci_write_config_byte(dev, vsec + 0xa, val) 58 #define CXL_WRITE_VSEC_MODE_CONTROL_BUS(bus, devfn, vsec, val) \ 59 pci_bus_write_config_byte(bus, devfn, vsec + 0xa, val) 60 #define CXL_VSEC_PROTOCOL_MASK 0xe0 61 #define CXL_VSEC_PROTOCOL_1024TB 0x80 62 #define CXL_VSEC_PROTOCOL_512TB 0x40 63 #define CXL_VSEC_PROTOCOL_256TB 0x20 /* Power 8/9 uses this */ 64 #define CXL_VSEC_PROTOCOL_ENABLE 0x01 65 66 #define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \ 67 pci_read_config_word(dev, vsec + 0xc, dest) 68 #define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \ 69 pci_read_config_byte(dev, vsec + 0xe, dest) 70 #define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \ 71 pci_read_config_byte(dev, vsec + 0xf, dest) 72 #define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \ 73 pci_read_config_word(dev, vsec + 0x10, dest) 74 75 #define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \ 76 pci_read_config_byte(dev, vsec + 0x13, dest) 77 #define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \ 78 pci_write_config_byte(dev, vsec + 0x13, val) 79 #define CXL_VSEC_USER_IMAGE_LOADED 0x80 /* RO */ 80 #define CXL_VSEC_PERST_LOADS_IMAGE 0x20 /* RW */ 81 #define CXL_VSEC_PERST_SELECT_USER 0x10 /* RW */ 82 83 #define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \ 84 pci_read_config_dword(dev, vsec + 0x20, dest) 85 #define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \ 86 pci_read_config_dword(dev, vsec + 0x24, dest) 87 #define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \ 88 pci_read_config_dword(dev, vsec + 0x28, dest) 89 #define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \ 90 pci_read_config_dword(dev, vsec + 0x2c, dest) 91 92 93 /* This works a little different than the p1/p2 register accesses to make it 94 * easier to pull out individual fields */ 95 #define AFUD_READ(afu, off) in_be64(afu->native->afu_desc_mmio + off) 96 #define AFUD_READ_LE(afu, off) in_le64(afu->native->afu_desc_mmio + off) 97 #define EXTRACT_PPC_BIT(val, bit) (!!(val & PPC_BIT(bit))) 98 #define EXTRACT_PPC_BITS(val, bs, be) ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be)) 99 100 #define AFUD_READ_INFO(afu) AFUD_READ(afu, 0x0) 101 #define AFUD_NUM_INTS_PER_PROC(val) EXTRACT_PPC_BITS(val, 0, 15) 102 #define AFUD_NUM_PROCS(val) EXTRACT_PPC_BITS(val, 16, 31) 103 #define AFUD_NUM_CRS(val) EXTRACT_PPC_BITS(val, 32, 47) 104 #define AFUD_MULTIMODE(val) EXTRACT_PPC_BIT(val, 48) 105 #define AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55) 106 #define AFUD_DEDICATED_PROCESS(val) EXTRACT_PPC_BIT(val, 59) 107 #define AFUD_AFU_DIRECTED(val) EXTRACT_PPC_BIT(val, 61) 108 #define AFUD_TIME_SLICED(val) EXTRACT_PPC_BIT(val, 63) 109 #define AFUD_READ_CR(afu) AFUD_READ(afu, 0x20) 110 #define AFUD_CR_LEN(val) EXTRACT_PPC_BITS(val, 8, 63) 111 #define AFUD_READ_CR_OFF(afu) AFUD_READ(afu, 0x28) 112 #define AFUD_READ_PPPSA(afu) AFUD_READ(afu, 0x30) 113 #define AFUD_PPPSA_PP(val) EXTRACT_PPC_BIT(val, 6) 114 #define AFUD_PPPSA_PSA(val) EXTRACT_PPC_BIT(val, 7) 115 #define AFUD_PPPSA_LEN(val) EXTRACT_PPC_BITS(val, 8, 63) 116 #define AFUD_READ_PPPSA_OFF(afu) AFUD_READ(afu, 0x38) 117 #define AFUD_READ_EB(afu) AFUD_READ(afu, 0x40) 118 #define AFUD_EB_LEN(val) EXTRACT_PPC_BITS(val, 8, 63) 119 #define AFUD_READ_EB_OFF(afu) AFUD_READ(afu, 0x48) 120 121 static const struct pci_device_id cxl_pci_tbl[] = { 122 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), }, 123 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), }, 124 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), }, 125 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0601), }, 126 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0623), }, 127 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0628), }, 128 { } 129 }; 130 MODULE_DEVICE_TABLE(pci, cxl_pci_tbl); 131 132 133 /* 134 * Mostly using these wrappers to avoid confusion: 135 * priv 1 is BAR2, while priv 2 is BAR0 136 */ 137 static inline resource_size_t p1_base(struct pci_dev *dev) 138 { 139 return pci_resource_start(dev, 2); 140 } 141 142 static inline resource_size_t p1_size(struct pci_dev *dev) 143 { 144 return pci_resource_len(dev, 2); 145 } 146 147 static inline resource_size_t p2_base(struct pci_dev *dev) 148 { 149 return pci_resource_start(dev, 0); 150 } 151 152 static inline resource_size_t p2_size(struct pci_dev *dev) 153 { 154 return pci_resource_len(dev, 0); 155 } 156 157 static int find_cxl_vsec(struct pci_dev *dev) 158 { 159 int vsec = 0; 160 u16 val; 161 162 while ((vsec = pci_find_next_ext_capability(dev, vsec, PCI_EXT_CAP_ID_VNDR))) { 163 pci_read_config_word(dev, vsec + 0x4, &val); 164 if (val == CXL_PCI_VSEC_ID) 165 return vsec; 166 } 167 return 0; 168 169 } 170 171 static void dump_cxl_config_space(struct pci_dev *dev) 172 { 173 int vsec; 174 u32 val; 175 176 dev_info(&dev->dev, "dump_cxl_config_space\n"); 177 178 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val); 179 dev_info(&dev->dev, "BAR0: %#.8x\n", val); 180 pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val); 181 dev_info(&dev->dev, "BAR1: %#.8x\n", val); 182 pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val); 183 dev_info(&dev->dev, "BAR2: %#.8x\n", val); 184 pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val); 185 dev_info(&dev->dev, "BAR3: %#.8x\n", val); 186 pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val); 187 dev_info(&dev->dev, "BAR4: %#.8x\n", val); 188 pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val); 189 dev_info(&dev->dev, "BAR5: %#.8x\n", val); 190 191 dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n", 192 p1_base(dev), p1_size(dev)); 193 dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n", 194 p2_base(dev), p2_size(dev)); 195 dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n", 196 pci_resource_start(dev, 4), pci_resource_len(dev, 4)); 197 198 if (!(vsec = find_cxl_vsec(dev))) 199 return; 200 201 #define show_reg(name, what) \ 202 dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what) 203 204 pci_read_config_dword(dev, vsec + 0x0, &val); 205 show_reg("Cap ID", (val >> 0) & 0xffff); 206 show_reg("Cap Ver", (val >> 16) & 0xf); 207 show_reg("Next Cap Ptr", (val >> 20) & 0xfff); 208 pci_read_config_dword(dev, vsec + 0x4, &val); 209 show_reg("VSEC ID", (val >> 0) & 0xffff); 210 show_reg("VSEC Rev", (val >> 16) & 0xf); 211 show_reg("VSEC Length", (val >> 20) & 0xfff); 212 pci_read_config_dword(dev, vsec + 0x8, &val); 213 show_reg("Num AFUs", (val >> 0) & 0xff); 214 show_reg("Status", (val >> 8) & 0xff); 215 show_reg("Mode Control", (val >> 16) & 0xff); 216 show_reg("Reserved", (val >> 24) & 0xff); 217 pci_read_config_dword(dev, vsec + 0xc, &val); 218 show_reg("PSL Rev", (val >> 0) & 0xffff); 219 show_reg("CAIA Ver", (val >> 16) & 0xffff); 220 pci_read_config_dword(dev, vsec + 0x10, &val); 221 show_reg("Base Image Rev", (val >> 0) & 0xffff); 222 show_reg("Reserved", (val >> 16) & 0x0fff); 223 show_reg("Image Control", (val >> 28) & 0x3); 224 show_reg("Reserved", (val >> 30) & 0x1); 225 show_reg("Image Loaded", (val >> 31) & 0x1); 226 227 pci_read_config_dword(dev, vsec + 0x14, &val); 228 show_reg("Reserved", val); 229 pci_read_config_dword(dev, vsec + 0x18, &val); 230 show_reg("Reserved", val); 231 pci_read_config_dword(dev, vsec + 0x1c, &val); 232 show_reg("Reserved", val); 233 234 pci_read_config_dword(dev, vsec + 0x20, &val); 235 show_reg("AFU Descriptor Offset", val); 236 pci_read_config_dword(dev, vsec + 0x24, &val); 237 show_reg("AFU Descriptor Size", val); 238 pci_read_config_dword(dev, vsec + 0x28, &val); 239 show_reg("Problem State Offset", val); 240 pci_read_config_dword(dev, vsec + 0x2c, &val); 241 show_reg("Problem State Size", val); 242 243 pci_read_config_dword(dev, vsec + 0x30, &val); 244 show_reg("Reserved", val); 245 pci_read_config_dword(dev, vsec + 0x34, &val); 246 show_reg("Reserved", val); 247 pci_read_config_dword(dev, vsec + 0x38, &val); 248 show_reg("Reserved", val); 249 pci_read_config_dword(dev, vsec + 0x3c, &val); 250 show_reg("Reserved", val); 251 252 pci_read_config_dword(dev, vsec + 0x40, &val); 253 show_reg("PSL Programming Port", val); 254 pci_read_config_dword(dev, vsec + 0x44, &val); 255 show_reg("PSL Programming Control", val); 256 257 pci_read_config_dword(dev, vsec + 0x48, &val); 258 show_reg("Reserved", val); 259 pci_read_config_dword(dev, vsec + 0x4c, &val); 260 show_reg("Reserved", val); 261 262 pci_read_config_dword(dev, vsec + 0x50, &val); 263 show_reg("Flash Address Register", val); 264 pci_read_config_dword(dev, vsec + 0x54, &val); 265 show_reg("Flash Size Register", val); 266 pci_read_config_dword(dev, vsec + 0x58, &val); 267 show_reg("Flash Status/Control Register", val); 268 pci_read_config_dword(dev, vsec + 0x58, &val); 269 show_reg("Flash Data Port", val); 270 271 #undef show_reg 272 } 273 274 static void dump_afu_descriptor(struct cxl_afu *afu) 275 { 276 u64 val, afu_cr_num, afu_cr_off, afu_cr_len; 277 int i; 278 279 #define show_reg(name, what) \ 280 dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what) 281 282 val = AFUD_READ_INFO(afu); 283 show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val)); 284 show_reg("num_of_processes", AFUD_NUM_PROCS(val)); 285 show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val)); 286 show_reg("req_prog_mode", val & 0xffffULL); 287 afu_cr_num = AFUD_NUM_CRS(val); 288 289 val = AFUD_READ(afu, 0x8); 290 show_reg("Reserved", val); 291 val = AFUD_READ(afu, 0x10); 292 show_reg("Reserved", val); 293 val = AFUD_READ(afu, 0x18); 294 show_reg("Reserved", val); 295 296 val = AFUD_READ_CR(afu); 297 show_reg("Reserved", (val >> (63-7)) & 0xff); 298 show_reg("AFU_CR_len", AFUD_CR_LEN(val)); 299 afu_cr_len = AFUD_CR_LEN(val) * 256; 300 301 val = AFUD_READ_CR_OFF(afu); 302 afu_cr_off = val; 303 show_reg("AFU_CR_offset", val); 304 305 val = AFUD_READ_PPPSA(afu); 306 show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff); 307 show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val)); 308 309 val = AFUD_READ_PPPSA_OFF(afu); 310 show_reg("PerProcessPSA_offset", val); 311 312 val = AFUD_READ_EB(afu); 313 show_reg("Reserved", (val >> (63-7)) & 0xff); 314 show_reg("AFU_EB_len", AFUD_EB_LEN(val)); 315 316 val = AFUD_READ_EB_OFF(afu); 317 show_reg("AFU_EB_offset", val); 318 319 for (i = 0; i < afu_cr_num; i++) { 320 val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len); 321 show_reg("CR Vendor", val & 0xffff); 322 show_reg("CR Device", (val >> 16) & 0xffff); 323 } 324 #undef show_reg 325 } 326 327 #define P8_CAPP_UNIT0_ID 0xBA 328 #define P8_CAPP_UNIT1_ID 0XBE 329 #define P9_CAPP_UNIT0_ID 0xC0 330 #define P9_CAPP_UNIT1_ID 0xE0 331 332 static int get_phb_index(struct device_node *np, u32 *phb_index) 333 { 334 if (of_property_read_u32(np, "ibm,phb-index", phb_index)) 335 return -ENODEV; 336 return 0; 337 } 338 339 static u64 get_capp_unit_id(struct device_node *np, u32 phb_index) 340 { 341 /* 342 * POWER 8: 343 * - For chips other than POWER8NVL, we only have CAPP 0, 344 * irrespective of which PHB is used. 345 * - For POWER8NVL, assume CAPP 0 is attached to PHB0 and 346 * CAPP 1 is attached to PHB1. 347 */ 348 if (cxl_is_power8()) { 349 if (!pvr_version_is(PVR_POWER8NVL)) 350 return P8_CAPP_UNIT0_ID; 351 352 if (phb_index == 0) 353 return P8_CAPP_UNIT0_ID; 354 355 if (phb_index == 1) 356 return P8_CAPP_UNIT1_ID; 357 } 358 359 /* 360 * POWER 9: 361 * PEC0 (PHB0). Capp ID = CAPP0 (0b1100_0000) 362 * PEC1 (PHB1 - PHB2). No capi mode 363 * PEC2 (PHB3 - PHB4 - PHB5): Capi mode on PHB3 only. Capp ID = CAPP1 (0b1110_0000) 364 */ 365 if (cxl_is_power9()) { 366 if (phb_index == 0) 367 return P9_CAPP_UNIT0_ID; 368 369 if (phb_index == 3) 370 return P9_CAPP_UNIT1_ID; 371 } 372 373 return 0; 374 } 375 376 int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid, 377 u32 *phb_index, u64 *capp_unit_id) 378 { 379 int rc; 380 struct device_node *np; 381 const __be32 *prop; 382 383 if (!(np = pnv_pci_get_phb_node(dev))) 384 return -ENODEV; 385 386 while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL))) 387 np = of_get_next_parent(np); 388 if (!np) 389 return -ENODEV; 390 391 *chipid = be32_to_cpup(prop); 392 393 rc = get_phb_index(np, phb_index); 394 if (rc) { 395 pr_err("cxl: invalid phb index\n"); 396 return rc; 397 } 398 399 *capp_unit_id = get_capp_unit_id(np, *phb_index); 400 of_node_put(np); 401 if (!*capp_unit_id) { 402 pr_err("cxl: invalid capp unit id (phb_index: %d)\n", 403 *phb_index); 404 return -ENODEV; 405 } 406 407 return 0; 408 } 409 410 static DEFINE_MUTEX(indications_mutex); 411 412 static int get_phb_indications(struct pci_dev *dev, u64 *capiind, u64 *asnind, 413 u64 *nbwind) 414 { 415 static u64 nbw, asn, capi = 0; 416 struct device_node *np; 417 const __be32 *prop; 418 419 mutex_lock(&indications_mutex); 420 if (!capi) { 421 if (!(np = pnv_pci_get_phb_node(dev))) { 422 mutex_unlock(&indications_mutex); 423 return -ENODEV; 424 } 425 426 prop = of_get_property(np, "ibm,phb-indications", NULL); 427 if (!prop) { 428 nbw = 0x0300UL; /* legacy values */ 429 asn = 0x0400UL; 430 capi = 0x0200UL; 431 } else { 432 nbw = (u64)be32_to_cpu(prop[2]); 433 asn = (u64)be32_to_cpu(prop[1]); 434 capi = (u64)be32_to_cpu(prop[0]); 435 } 436 of_node_put(np); 437 } 438 *capiind = capi; 439 *asnind = asn; 440 *nbwind = nbw; 441 mutex_unlock(&indications_mutex); 442 return 0; 443 } 444 445 int cxl_get_xsl9_dsnctl(struct pci_dev *dev, u64 capp_unit_id, u64 *reg) 446 { 447 u64 xsl_dsnctl; 448 u64 capiind, asnind, nbwind; 449 450 /* 451 * CAPI Identifier bits [0:7] 452 * bit 61:60 MSI bits --> 0 453 * bit 59 TVT selector --> 0 454 */ 455 if (get_phb_indications(dev, &capiind, &asnind, &nbwind)) 456 return -ENODEV; 457 458 /* 459 * Tell XSL where to route data to. 460 * The field chipid should match the PHB CAPI_CMPM register 461 */ 462 xsl_dsnctl = (capiind << (63-15)); /* Bit 57 */ 463 xsl_dsnctl |= (capp_unit_id << (63-15)); 464 465 /* nMMU_ID Defaults to: b’000001001’*/ 466 xsl_dsnctl |= ((u64)0x09 << (63-28)); 467 468 if (!(cxl_is_power9_dd1())) { 469 /* 470 * Used to identify CAPI packets which should be sorted into 471 * the Non-Blocking queues by the PHB. This field should match 472 * the PHB PBL_NBW_CMPM register 473 * nbwind=0x03, bits [57:58], must include capi indicator. 474 * Not supported on P9 DD1. 475 */ 476 xsl_dsnctl |= (nbwind << (63-55)); 477 478 /* 479 * Upper 16b address bits of ASB_Notify messages sent to the 480 * system. Need to match the PHB’s ASN Compare/Mask Register. 481 * Not supported on P9 DD1. 482 */ 483 xsl_dsnctl |= asnind; 484 } 485 486 *reg = xsl_dsnctl; 487 return 0; 488 } 489 490 static int init_implementation_adapter_regs_psl9(struct cxl *adapter, 491 struct pci_dev *dev) 492 { 493 u64 xsl_dsnctl, psl_fircntl; 494 u64 chipid; 495 u32 phb_index; 496 u64 capp_unit_id; 497 u64 psl_debug; 498 int rc; 499 500 rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id); 501 if (rc) 502 return rc; 503 504 rc = cxl_get_xsl9_dsnctl(dev, capp_unit_id, &xsl_dsnctl); 505 if (rc) 506 return rc; 507 508 cxl_p1_write(adapter, CXL_XSL9_DSNCTL, xsl_dsnctl); 509 510 /* Set fir_cntl to recommended value for production env */ 511 psl_fircntl = (0x2ULL << (63-3)); /* ce_report */ 512 psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */ 513 psl_fircntl |= 0x1ULL; /* ce_thresh */ 514 cxl_p1_write(adapter, CXL_PSL9_FIR_CNTL, psl_fircntl); 515 516 /* Setup the PSL to transmit packets on the PCIe before the 517 * CAPP is enabled. Make sure that CAPP virtual machines are disabled 518 */ 519 cxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0001001000012A10ULL); 520 521 /* 522 * A response to an ASB_Notify request is returned by the 523 * system as an MMIO write to the address defined in 524 * the PSL_TNR_ADDR register. 525 * keep the Reset Value: 0x00020000E0000000 526 */ 527 528 /* Enable XSL rty limit */ 529 cxl_p1_write(adapter, CXL_XSL9_DEF, 0x51F8000000000005ULL); 530 531 /* Change XSL_INV dummy read threshold */ 532 cxl_p1_write(adapter, CXL_XSL9_INV, 0x0000040007FFC200ULL); 533 534 if (phb_index == 3) { 535 /* disable machines 31-47 and 20-27 for DMA */ 536 cxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, 0x40000FF3FFFF0000ULL); 537 } 538 539 /* Snoop machines */ 540 cxl_p1_write(adapter, CXL_PSL9_APCDEDALLOC, 0x800F000200000000ULL); 541 542 if (cxl_is_power9_dd1()) { 543 /* Disabling deadlock counter CAR */ 544 cxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0020000000000001ULL); 545 /* Enable NORST */ 546 cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x8000000000000000ULL); 547 } else { 548 /* Enable NORST and DD2 features */ 549 cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0xC000000000000000ULL); 550 } 551 552 /* 553 * Check if PSL has data-cache. We need to flush adapter datacache 554 * when as its about to be removed. 555 */ 556 psl_debug = cxl_p1_read(adapter, CXL_PSL9_DEBUG); 557 if (psl_debug & CXL_PSL_DEBUG_CDC) { 558 dev_dbg(&dev->dev, "No data-cache present\n"); 559 adapter->native->no_data_cache = true; 560 } 561 562 return 0; 563 } 564 565 static int init_implementation_adapter_regs_psl8(struct cxl *adapter, struct pci_dev *dev) 566 { 567 u64 psl_dsnctl, psl_fircntl; 568 u64 chipid; 569 u32 phb_index; 570 u64 capp_unit_id; 571 int rc; 572 573 rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id); 574 if (rc) 575 return rc; 576 577 psl_dsnctl = 0x0000900000000000ULL; /* pteupd ttype, scdone */ 578 psl_dsnctl |= (0x2ULL << (63-38)); /* MMIO hang pulse: 256 us */ 579 /* Tell PSL where to route data to */ 580 psl_dsnctl |= (chipid << (63-5)); 581 psl_dsnctl |= (capp_unit_id << (63-13)); 582 583 cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl); 584 cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL); 585 /* snoop write mask */ 586 cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL); 587 /* set fir_cntl to recommended value for production env */ 588 psl_fircntl = (0x2ULL << (63-3)); /* ce_report */ 589 psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */ 590 psl_fircntl |= 0x1ULL; /* ce_thresh */ 591 cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, psl_fircntl); 592 /* for debugging with trace arrays */ 593 cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL); 594 595 return 0; 596 } 597 598 static int init_implementation_adapter_regs_xsl(struct cxl *adapter, struct pci_dev *dev) 599 { 600 u64 xsl_dsnctl; 601 u64 chipid; 602 u32 phb_index; 603 u64 capp_unit_id; 604 int rc; 605 606 rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id); 607 if (rc) 608 return rc; 609 610 /* Tell XSL where to route data to */ 611 xsl_dsnctl = 0x0000600000000000ULL | (chipid << (63-5)); 612 xsl_dsnctl |= (capp_unit_id << (63-13)); 613 cxl_p1_write(adapter, CXL_XSL_DSNCTL, xsl_dsnctl); 614 615 return 0; 616 } 617 618 /* PSL & XSL */ 619 #define TBSYNC_CAL(n) (((u64)n & 0x7) << (63-3)) 620 #define TBSYNC_CNT(n) (((u64)n & 0x7) << (63-6)) 621 /* For the PSL this is a multiple for 0 < n <= 7: */ 622 #define PSL_2048_250MHZ_CYCLES 1 623 624 static void write_timebase_ctrl_psl8(struct cxl *adapter) 625 { 626 cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT, 627 TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES)); 628 } 629 630 /* XSL */ 631 #define TBSYNC_ENA (1ULL << 63) 632 /* For the XSL this is 2**n * 2000 clocks for 0 < n <= 6: */ 633 #define XSL_2000_CLOCKS 1 634 #define XSL_4000_CLOCKS 2 635 #define XSL_8000_CLOCKS 3 636 637 static void write_timebase_ctrl_xsl(struct cxl *adapter) 638 { 639 cxl_p1_write(adapter, CXL_XSL_TB_CTLSTAT, 640 TBSYNC_ENA | 641 TBSYNC_CAL(3) | 642 TBSYNC_CNT(XSL_4000_CLOCKS)); 643 } 644 645 static u64 timebase_read_psl9(struct cxl *adapter) 646 { 647 return cxl_p1_read(adapter, CXL_PSL9_Timebase); 648 } 649 650 static u64 timebase_read_psl8(struct cxl *adapter) 651 { 652 return cxl_p1_read(adapter, CXL_PSL_Timebase); 653 } 654 655 static u64 timebase_read_xsl(struct cxl *adapter) 656 { 657 return cxl_p1_read(adapter, CXL_XSL_Timebase); 658 } 659 660 static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev) 661 { 662 struct device_node *np; 663 664 adapter->psl_timebase_synced = false; 665 666 if (!(np = pnv_pci_get_phb_node(dev))) 667 return; 668 669 /* Do not fail when CAPP timebase sync is not supported by OPAL */ 670 of_node_get(np); 671 if (! of_get_property(np, "ibm,capp-timebase-sync", NULL)) { 672 of_node_put(np); 673 dev_info(&dev->dev, "PSL timebase inactive: OPAL support missing\n"); 674 return; 675 } 676 of_node_put(np); 677 678 /* 679 * Setup PSL Timebase Control and Status register 680 * with the recommended Timebase Sync Count value 681 */ 682 if (adapter->native->sl_ops->write_timebase_ctrl) 683 adapter->native->sl_ops->write_timebase_ctrl(adapter); 684 685 /* Enable PSL Timebase */ 686 cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000); 687 cxl_p1_write(adapter, CXL_PSL_Control, CXL_PSL_Control_tb); 688 689 return; 690 } 691 692 static int init_implementation_afu_regs_psl9(struct cxl_afu *afu) 693 { 694 return 0; 695 } 696 697 static int init_implementation_afu_regs_psl8(struct cxl_afu *afu) 698 { 699 /* read/write masks for this slice */ 700 cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL); 701 /* APC read/write masks for this slice */ 702 cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL); 703 /* for debugging with trace arrays */ 704 cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL); 705 cxl_p1n_write(afu, CXL_PSL_RXCTL_A, CXL_PSL_RXCTL_AFUHP_4S); 706 707 return 0; 708 } 709 710 int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq, 711 unsigned int virq) 712 { 713 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 714 715 return pnv_cxl_ioda_msi_setup(dev, hwirq, virq); 716 } 717 718 int cxl_update_image_control(struct cxl *adapter) 719 { 720 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 721 int rc; 722 int vsec; 723 u8 image_state; 724 725 if (!(vsec = find_cxl_vsec(dev))) { 726 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n"); 727 return -ENODEV; 728 } 729 730 if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state))) { 731 dev_err(&dev->dev, "failed to read image state: %i\n", rc); 732 return rc; 733 } 734 735 if (adapter->perst_loads_image) 736 image_state |= CXL_VSEC_PERST_LOADS_IMAGE; 737 else 738 image_state &= ~CXL_VSEC_PERST_LOADS_IMAGE; 739 740 if (adapter->perst_select_user) 741 image_state |= CXL_VSEC_PERST_SELECT_USER; 742 else 743 image_state &= ~CXL_VSEC_PERST_SELECT_USER; 744 745 if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) { 746 dev_err(&dev->dev, "failed to update image control: %i\n", rc); 747 return rc; 748 } 749 750 return 0; 751 } 752 753 int cxl_pci_alloc_one_irq(struct cxl *adapter) 754 { 755 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 756 757 return pnv_cxl_alloc_hwirqs(dev, 1); 758 } 759 760 void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq) 761 { 762 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 763 764 return pnv_cxl_release_hwirqs(dev, hwirq, 1); 765 } 766 767 int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs, 768 struct cxl *adapter, unsigned int num) 769 { 770 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 771 772 return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num); 773 } 774 775 void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs, 776 struct cxl *adapter) 777 { 778 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 779 780 pnv_cxl_release_hwirq_ranges(irqs, dev); 781 } 782 783 static int setup_cxl_bars(struct pci_dev *dev) 784 { 785 /* Safety check in case we get backported to < 3.17 without M64 */ 786 if ((p1_base(dev) < 0x100000000ULL) || 787 (p2_base(dev) < 0x100000000ULL)) { 788 dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n"); 789 return -ENODEV; 790 } 791 792 /* 793 * BAR 4/5 has a special meaning for CXL and must be programmed with a 794 * special value corresponding to the CXL protocol address range. 795 * For POWER 8/9 that means bits 48:49 must be set to 10 796 */ 797 pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000); 798 pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000); 799 800 return 0; 801 } 802 803 #ifdef CONFIG_CXL_BIMODAL 804 805 struct cxl_switch_work { 806 struct pci_dev *dev; 807 struct work_struct work; 808 int vsec; 809 int mode; 810 }; 811 812 static void switch_card_to_cxl(struct work_struct *work) 813 { 814 struct cxl_switch_work *switch_work = 815 container_of(work, struct cxl_switch_work, work); 816 struct pci_dev *dev = switch_work->dev; 817 struct pci_bus *bus = dev->bus; 818 struct pci_controller *hose = pci_bus_to_host(bus); 819 struct pci_dev *bridge; 820 struct pnv_php_slot *php_slot; 821 unsigned int devfn; 822 u8 val; 823 int rc; 824 825 dev_info(&bus->dev, "cxl: Preparing for mode switch...\n"); 826 bridge = list_first_entry_or_null(&hose->bus->devices, struct pci_dev, 827 bus_list); 828 if (!bridge) { 829 dev_WARN(&bus->dev, "cxl: Couldn't find root port!\n"); 830 goto err_dev_put; 831 } 832 833 php_slot = pnv_php_find_slot(pci_device_to_OF_node(bridge)); 834 if (!php_slot) { 835 dev_err(&bus->dev, "cxl: Failed to find slot hotplug " 836 "information. You may need to upgrade " 837 "skiboot. Aborting.\n"); 838 goto err_dev_put; 839 } 840 841 rc = CXL_READ_VSEC_MODE_CONTROL(dev, switch_work->vsec, &val); 842 if (rc) { 843 dev_err(&bus->dev, "cxl: Failed to read CAPI mode control: %i\n", rc); 844 goto err_dev_put; 845 } 846 devfn = dev->devfn; 847 848 /* Release the reference obtained in cxl_check_and_switch_mode() */ 849 pci_dev_put(dev); 850 851 dev_dbg(&bus->dev, "cxl: Removing PCI devices from kernel\n"); 852 pci_lock_rescan_remove(); 853 pci_hp_remove_devices(bridge->subordinate); 854 pci_unlock_rescan_remove(); 855 856 /* Switch the CXL protocol on the card */ 857 if (switch_work->mode == CXL_BIMODE_CXL) { 858 dev_info(&bus->dev, "cxl: Switching card to CXL mode\n"); 859 val &= ~CXL_VSEC_PROTOCOL_MASK; 860 val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE; 861 rc = pnv_cxl_enable_phb_kernel_api(hose, true); 862 if (rc) { 863 dev_err(&bus->dev, "cxl: Failed to enable kernel API" 864 " on real PHB, aborting\n"); 865 goto err_free_work; 866 } 867 } else { 868 dev_WARN(&bus->dev, "cxl: Switching card to PCI mode not supported!\n"); 869 goto err_free_work; 870 } 871 872 rc = CXL_WRITE_VSEC_MODE_CONTROL_BUS(bus, devfn, switch_work->vsec, val); 873 if (rc) { 874 dev_err(&bus->dev, "cxl: Failed to configure CXL protocol: %i\n", rc); 875 goto err_free_work; 876 } 877 878 /* 879 * The CAIA spec (v1.1, Section 10.6 Bi-modal Device Support) states 880 * we must wait 100ms after this mode switch before touching PCIe config 881 * space. 882 */ 883 msleep(100); 884 885 /* 886 * Hot reset to cause the card to come back in cxl mode. A 887 * OPAL_RESET_PCI_LINK would be sufficient, but currently lacks support 888 * in skiboot, so we use a hot reset instead. 889 * 890 * We call pci_set_pcie_reset_state() on the bridge, as a CAPI card is 891 * guaranteed to sit directly under the root port, and setting the reset 892 * state on a device directly under the root port is equivalent to doing 893 * it on the root port iself. 894 */ 895 dev_info(&bus->dev, "cxl: Configuration write complete, resetting card\n"); 896 pci_set_pcie_reset_state(bridge, pcie_hot_reset); 897 pci_set_pcie_reset_state(bridge, pcie_deassert_reset); 898 899 dev_dbg(&bus->dev, "cxl: Offlining slot\n"); 900 rc = pnv_php_set_slot_power_state(&php_slot->slot, OPAL_PCI_SLOT_OFFLINE); 901 if (rc) { 902 dev_err(&bus->dev, "cxl: OPAL offlining call failed: %i\n", rc); 903 goto err_free_work; 904 } 905 906 dev_dbg(&bus->dev, "cxl: Onlining and probing slot\n"); 907 rc = pnv_php_set_slot_power_state(&php_slot->slot, OPAL_PCI_SLOT_ONLINE); 908 if (rc) { 909 dev_err(&bus->dev, "cxl: OPAL onlining call failed: %i\n", rc); 910 goto err_free_work; 911 } 912 913 pci_lock_rescan_remove(); 914 pci_hp_add_devices(bridge->subordinate); 915 pci_unlock_rescan_remove(); 916 917 dev_info(&bus->dev, "cxl: CAPI mode switch completed\n"); 918 kfree(switch_work); 919 return; 920 921 err_dev_put: 922 /* Release the reference obtained in cxl_check_and_switch_mode() */ 923 pci_dev_put(dev); 924 err_free_work: 925 kfree(switch_work); 926 } 927 928 int cxl_check_and_switch_mode(struct pci_dev *dev, int mode, int vsec) 929 { 930 struct cxl_switch_work *work; 931 u8 val; 932 int rc; 933 934 if (!cpu_has_feature(CPU_FTR_HVMODE)) 935 return -ENODEV; 936 937 if (!vsec) { 938 vsec = find_cxl_vsec(dev); 939 if (!vsec) { 940 dev_info(&dev->dev, "CXL VSEC not found\n"); 941 return -ENODEV; 942 } 943 } 944 945 rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val); 946 if (rc) { 947 dev_err(&dev->dev, "Failed to read current mode control: %i", rc); 948 return rc; 949 } 950 951 if (mode == CXL_BIMODE_PCI) { 952 if (!(val & CXL_VSEC_PROTOCOL_ENABLE)) { 953 dev_info(&dev->dev, "Card is already in PCI mode\n"); 954 return 0; 955 } 956 /* 957 * TODO: Before it's safe to switch the card back to PCI mode 958 * we need to disable the CAPP and make sure any cachelines the 959 * card holds have been flushed out. Needs skiboot support. 960 */ 961 dev_WARN(&dev->dev, "CXL mode switch to PCI unsupported!\n"); 962 return -EIO; 963 } 964 965 if (val & CXL_VSEC_PROTOCOL_ENABLE) { 966 dev_info(&dev->dev, "Card is already in CXL mode\n"); 967 return 0; 968 } 969 970 dev_info(&dev->dev, "Card is in PCI mode, scheduling kernel thread " 971 "to switch to CXL mode\n"); 972 973 work = kmalloc(sizeof(struct cxl_switch_work), GFP_KERNEL); 974 if (!work) 975 return -ENOMEM; 976 977 pci_dev_get(dev); 978 work->dev = dev; 979 work->vsec = vsec; 980 work->mode = mode; 981 INIT_WORK(&work->work, switch_card_to_cxl); 982 983 schedule_work(&work->work); 984 985 /* 986 * We return a failure now to abort the driver init. Once the 987 * link has been cycled and the card is in cxl mode we will 988 * come back (possibly using the generic cxl driver), but 989 * return success as the card should then be in cxl mode. 990 * 991 * TODO: What if the card comes back in PCI mode even after 992 * the switch? Don't want to spin endlessly. 993 */ 994 return -EBUSY; 995 } 996 EXPORT_SYMBOL_GPL(cxl_check_and_switch_mode); 997 998 #endif /* CONFIG_CXL_BIMODAL */ 999 1000 static int setup_cxl_protocol_area(struct pci_dev *dev) 1001 { 1002 u8 val; 1003 int rc; 1004 int vsec = find_cxl_vsec(dev); 1005 1006 if (!vsec) { 1007 dev_info(&dev->dev, "CXL VSEC not found\n"); 1008 return -ENODEV; 1009 } 1010 1011 rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val); 1012 if (rc) { 1013 dev_err(&dev->dev, "Failed to read current mode control: %i\n", rc); 1014 return rc; 1015 } 1016 1017 if (!(val & CXL_VSEC_PROTOCOL_ENABLE)) { 1018 dev_err(&dev->dev, "Card not in CAPI mode!\n"); 1019 return -EIO; 1020 } 1021 1022 if ((val & CXL_VSEC_PROTOCOL_MASK) != CXL_VSEC_PROTOCOL_256TB) { 1023 val &= ~CXL_VSEC_PROTOCOL_MASK; 1024 val |= CXL_VSEC_PROTOCOL_256TB; 1025 rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val); 1026 if (rc) { 1027 dev_err(&dev->dev, "Failed to set CXL protocol area: %i\n", rc); 1028 return rc; 1029 } 1030 } 1031 1032 return 0; 1033 } 1034 1035 static int pci_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev) 1036 { 1037 u64 p1n_base, p2n_base, afu_desc; 1038 const u64 p1n_size = 0x100; 1039 const u64 p2n_size = 0x1000; 1040 1041 p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size); 1042 p2n_base = p2_base(dev) + (afu->slice * p2n_size); 1043 afu->psn_phys = p2_base(dev) + (adapter->native->ps_off + (afu->slice * adapter->ps_size)); 1044 afu_desc = p2_base(dev) + adapter->native->afu_desc_off + (afu->slice * adapter->native->afu_desc_size); 1045 1046 if (!(afu->native->p1n_mmio = ioremap(p1n_base, p1n_size))) 1047 goto err; 1048 if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size))) 1049 goto err1; 1050 if (afu_desc) { 1051 if (!(afu->native->afu_desc_mmio = ioremap(afu_desc, adapter->native->afu_desc_size))) 1052 goto err2; 1053 } 1054 1055 return 0; 1056 err2: 1057 iounmap(afu->p2n_mmio); 1058 err1: 1059 iounmap(afu->native->p1n_mmio); 1060 err: 1061 dev_err(&afu->dev, "Error mapping AFU MMIO regions\n"); 1062 return -ENOMEM; 1063 } 1064 1065 static void pci_unmap_slice_regs(struct cxl_afu *afu) 1066 { 1067 if (afu->p2n_mmio) { 1068 iounmap(afu->p2n_mmio); 1069 afu->p2n_mmio = NULL; 1070 } 1071 if (afu->native->p1n_mmio) { 1072 iounmap(afu->native->p1n_mmio); 1073 afu->native->p1n_mmio = NULL; 1074 } 1075 if (afu->native->afu_desc_mmio) { 1076 iounmap(afu->native->afu_desc_mmio); 1077 afu->native->afu_desc_mmio = NULL; 1078 } 1079 } 1080 1081 void cxl_pci_release_afu(struct device *dev) 1082 { 1083 struct cxl_afu *afu = to_cxl_afu(dev); 1084 1085 pr_devel("%s\n", __func__); 1086 1087 idr_destroy(&afu->contexts_idr); 1088 cxl_release_spa(afu); 1089 1090 kfree(afu->native); 1091 kfree(afu); 1092 } 1093 1094 /* Expects AFU struct to have recently been zeroed out */ 1095 static int cxl_read_afu_descriptor(struct cxl_afu *afu) 1096 { 1097 u64 val; 1098 1099 val = AFUD_READ_INFO(afu); 1100 afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val); 1101 afu->max_procs_virtualised = AFUD_NUM_PROCS(val); 1102 afu->crs_num = AFUD_NUM_CRS(val); 1103 1104 if (AFUD_AFU_DIRECTED(val)) 1105 afu->modes_supported |= CXL_MODE_DIRECTED; 1106 if (AFUD_DEDICATED_PROCESS(val)) 1107 afu->modes_supported |= CXL_MODE_DEDICATED; 1108 if (AFUD_TIME_SLICED(val)) 1109 afu->modes_supported |= CXL_MODE_TIME_SLICED; 1110 1111 val = AFUD_READ_PPPSA(afu); 1112 afu->pp_size = AFUD_PPPSA_LEN(val) * 4096; 1113 afu->psa = AFUD_PPPSA_PSA(val); 1114 if ((afu->pp_psa = AFUD_PPPSA_PP(val))) 1115 afu->native->pp_offset = AFUD_READ_PPPSA_OFF(afu); 1116 1117 val = AFUD_READ_CR(afu); 1118 afu->crs_len = AFUD_CR_LEN(val) * 256; 1119 afu->crs_offset = AFUD_READ_CR_OFF(afu); 1120 1121 1122 /* eb_len is in multiple of 4K */ 1123 afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096; 1124 afu->eb_offset = AFUD_READ_EB_OFF(afu); 1125 1126 /* eb_off is 4K aligned so lower 12 bits are always zero */ 1127 if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) { 1128 dev_warn(&afu->dev, 1129 "Invalid AFU error buffer offset %Lx\n", 1130 afu->eb_offset); 1131 dev_info(&afu->dev, 1132 "Ignoring AFU error buffer in the descriptor\n"); 1133 /* indicate that no afu buffer exists */ 1134 afu->eb_len = 0; 1135 } 1136 1137 return 0; 1138 } 1139 1140 static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu) 1141 { 1142 int i, rc; 1143 u32 val; 1144 1145 if (afu->psa && afu->adapter->ps_size < 1146 (afu->native->pp_offset + afu->pp_size*afu->max_procs_virtualised)) { 1147 dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n"); 1148 return -ENODEV; 1149 } 1150 1151 if (afu->pp_psa && (afu->pp_size < PAGE_SIZE)) 1152 dev_warn(&afu->dev, "AFU uses pp_size(%#016llx) < PAGE_SIZE per-process PSA!\n", afu->pp_size); 1153 1154 for (i = 0; i < afu->crs_num; i++) { 1155 rc = cxl_ops->afu_cr_read32(afu, i, 0, &val); 1156 if (rc || val == 0) { 1157 dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i); 1158 return -EINVAL; 1159 } 1160 } 1161 1162 if ((afu->modes_supported & ~CXL_MODE_DEDICATED) && afu->max_procs_virtualised == 0) { 1163 /* 1164 * We could also check this for the dedicated process model 1165 * since the architecture indicates it should be set to 1, but 1166 * in that case we ignore the value and I'd rather not risk 1167 * breaking any existing dedicated process AFUs that left it as 1168 * 0 (not that I'm aware of any). It is clearly an error for an 1169 * AFU directed AFU to set this to 0, and would have previously 1170 * triggered a bug resulting in the maximum not being enforced 1171 * at all since idr_alloc treats 0 as no maximum. 1172 */ 1173 dev_err(&afu->dev, "AFU does not support any processes\n"); 1174 return -EINVAL; 1175 } 1176 1177 return 0; 1178 } 1179 1180 static int sanitise_afu_regs_psl9(struct cxl_afu *afu) 1181 { 1182 u64 reg; 1183 1184 /* 1185 * Clear out any regs that contain either an IVTE or address or may be 1186 * waiting on an acknowledgment to try to be a bit safer as we bring 1187 * it online 1188 */ 1189 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An); 1190 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) { 1191 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg); 1192 if (cxl_ops->afu_reset(afu)) 1193 return -EIO; 1194 if (cxl_afu_disable(afu)) 1195 return -EIO; 1196 if (cxl_psl_purge(afu)) 1197 return -EIO; 1198 } 1199 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000); 1200 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000); 1201 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An); 1202 if (reg) { 1203 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg); 1204 if (reg & CXL_PSL9_DSISR_An_TF) 1205 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); 1206 else 1207 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); 1208 } 1209 if (afu->adapter->native->sl_ops->register_serr_irq) { 1210 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An); 1211 if (reg) { 1212 if (reg & ~0x000000007fffffff) 1213 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg); 1214 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff); 1215 } 1216 } 1217 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); 1218 if (reg) { 1219 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg); 1220 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg); 1221 } 1222 1223 return 0; 1224 } 1225 1226 static int sanitise_afu_regs_psl8(struct cxl_afu *afu) 1227 { 1228 u64 reg; 1229 1230 /* 1231 * Clear out any regs that contain either an IVTE or address or may be 1232 * waiting on an acknowledgement to try to be a bit safer as we bring 1233 * it online 1234 */ 1235 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An); 1236 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) { 1237 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg); 1238 if (cxl_ops->afu_reset(afu)) 1239 return -EIO; 1240 if (cxl_afu_disable(afu)) 1241 return -EIO; 1242 if (cxl_psl_purge(afu)) 1243 return -EIO; 1244 } 1245 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000); 1246 cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000); 1247 cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000); 1248 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000); 1249 cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000); 1250 cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000); 1251 cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000); 1252 cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000); 1253 cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000); 1254 cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000); 1255 cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000); 1256 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An); 1257 if (reg) { 1258 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg); 1259 if (reg & CXL_PSL_DSISR_TRANS) 1260 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); 1261 else 1262 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); 1263 } 1264 if (afu->adapter->native->sl_ops->register_serr_irq) { 1265 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An); 1266 if (reg) { 1267 if (reg & ~0xffff) 1268 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg); 1269 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff); 1270 } 1271 } 1272 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); 1273 if (reg) { 1274 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg); 1275 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg); 1276 } 1277 1278 return 0; 1279 } 1280 1281 #define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE 1282 /* 1283 * afu_eb_read: 1284 * Called from sysfs and reads the afu error info buffer. The h/w only supports 1285 * 4/8 bytes aligned access. So in case the requested offset/count arent 8 byte 1286 * aligned the function uses a bounce buffer which can be max PAGE_SIZE. 1287 */ 1288 ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf, 1289 loff_t off, size_t count) 1290 { 1291 loff_t aligned_start, aligned_end; 1292 size_t aligned_length; 1293 void *tbuf; 1294 const void __iomem *ebuf = afu->native->afu_desc_mmio + afu->eb_offset; 1295 1296 if (count == 0 || off < 0 || (size_t)off >= afu->eb_len) 1297 return 0; 1298 1299 /* calculate aligned read window */ 1300 count = min((size_t)(afu->eb_len - off), count); 1301 aligned_start = round_down(off, 8); 1302 aligned_end = round_up(off + count, 8); 1303 aligned_length = aligned_end - aligned_start; 1304 1305 /* max we can copy in one read is PAGE_SIZE */ 1306 if (aligned_length > ERR_BUFF_MAX_COPY_SIZE) { 1307 aligned_length = ERR_BUFF_MAX_COPY_SIZE; 1308 count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7); 1309 } 1310 1311 /* use bounce buffer for copy */ 1312 tbuf = (void *)__get_free_page(GFP_KERNEL); 1313 if (!tbuf) 1314 return -ENOMEM; 1315 1316 /* perform aligned read from the mmio region */ 1317 memcpy_fromio(tbuf, ebuf + aligned_start, aligned_length); 1318 memcpy(buf, tbuf + (off & 0x7), count); 1319 1320 free_page((unsigned long)tbuf); 1321 1322 return count; 1323 } 1324 1325 static int pci_configure_afu(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev) 1326 { 1327 int rc; 1328 1329 if ((rc = pci_map_slice_regs(afu, adapter, dev))) 1330 return rc; 1331 1332 if (adapter->native->sl_ops->sanitise_afu_regs) { 1333 rc = adapter->native->sl_ops->sanitise_afu_regs(afu); 1334 if (rc) 1335 goto err1; 1336 } 1337 1338 /* We need to reset the AFU before we can read the AFU descriptor */ 1339 if ((rc = cxl_ops->afu_reset(afu))) 1340 goto err1; 1341 1342 if (cxl_verbose) 1343 dump_afu_descriptor(afu); 1344 1345 if ((rc = cxl_read_afu_descriptor(afu))) 1346 goto err1; 1347 1348 if ((rc = cxl_afu_descriptor_looks_ok(afu))) 1349 goto err1; 1350 1351 if (adapter->native->sl_ops->afu_regs_init) 1352 if ((rc = adapter->native->sl_ops->afu_regs_init(afu))) 1353 goto err1; 1354 1355 if (adapter->native->sl_ops->register_serr_irq) 1356 if ((rc = adapter->native->sl_ops->register_serr_irq(afu))) 1357 goto err1; 1358 1359 if ((rc = cxl_native_register_psl_irq(afu))) 1360 goto err2; 1361 1362 atomic_set(&afu->configured_state, 0); 1363 return 0; 1364 1365 err2: 1366 if (adapter->native->sl_ops->release_serr_irq) 1367 adapter->native->sl_ops->release_serr_irq(afu); 1368 err1: 1369 pci_unmap_slice_regs(afu); 1370 return rc; 1371 } 1372 1373 static void pci_deconfigure_afu(struct cxl_afu *afu) 1374 { 1375 /* 1376 * It's okay to deconfigure when AFU is already locked, otherwise wait 1377 * until there are no readers 1378 */ 1379 if (atomic_read(&afu->configured_state) != -1) { 1380 while (atomic_cmpxchg(&afu->configured_state, 0, -1) != -1) 1381 schedule(); 1382 } 1383 cxl_native_release_psl_irq(afu); 1384 if (afu->adapter->native->sl_ops->release_serr_irq) 1385 afu->adapter->native->sl_ops->release_serr_irq(afu); 1386 pci_unmap_slice_regs(afu); 1387 } 1388 1389 static int pci_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev) 1390 { 1391 struct cxl_afu *afu; 1392 int rc = -ENOMEM; 1393 1394 afu = cxl_alloc_afu(adapter, slice); 1395 if (!afu) 1396 return -ENOMEM; 1397 1398 afu->native = kzalloc(sizeof(struct cxl_afu_native), GFP_KERNEL); 1399 if (!afu->native) 1400 goto err_free_afu; 1401 1402 mutex_init(&afu->native->spa_mutex); 1403 1404 rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice); 1405 if (rc) 1406 goto err_free_native; 1407 1408 rc = pci_configure_afu(afu, adapter, dev); 1409 if (rc) 1410 goto err_free_native; 1411 1412 /* Don't care if this fails */ 1413 cxl_debugfs_afu_add(afu); 1414 1415 /* 1416 * After we call this function we must not free the afu directly, even 1417 * if it returns an error! 1418 */ 1419 if ((rc = cxl_register_afu(afu))) 1420 goto err_put1; 1421 1422 if ((rc = cxl_sysfs_afu_add(afu))) 1423 goto err_put1; 1424 1425 adapter->afu[afu->slice] = afu; 1426 1427 if ((rc = cxl_pci_vphb_add(afu))) 1428 dev_info(&afu->dev, "Can't register vPHB\n"); 1429 1430 return 0; 1431 1432 err_put1: 1433 pci_deconfigure_afu(afu); 1434 cxl_debugfs_afu_remove(afu); 1435 device_unregister(&afu->dev); 1436 return rc; 1437 1438 err_free_native: 1439 kfree(afu->native); 1440 err_free_afu: 1441 kfree(afu); 1442 return rc; 1443 1444 } 1445 1446 static void cxl_pci_remove_afu(struct cxl_afu *afu) 1447 { 1448 pr_devel("%s\n", __func__); 1449 1450 if (!afu) 1451 return; 1452 1453 cxl_pci_vphb_remove(afu); 1454 cxl_sysfs_afu_remove(afu); 1455 cxl_debugfs_afu_remove(afu); 1456 1457 spin_lock(&afu->adapter->afu_list_lock); 1458 afu->adapter->afu[afu->slice] = NULL; 1459 spin_unlock(&afu->adapter->afu_list_lock); 1460 1461 cxl_context_detach_all(afu); 1462 cxl_ops->afu_deactivate_mode(afu, afu->current_mode); 1463 1464 pci_deconfigure_afu(afu); 1465 device_unregister(&afu->dev); 1466 } 1467 1468 int cxl_pci_reset(struct cxl *adapter) 1469 { 1470 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 1471 int rc; 1472 1473 if (adapter->perst_same_image) { 1474 dev_warn(&dev->dev, 1475 "cxl: refusing to reset/reflash when perst_reloads_same_image is set.\n"); 1476 return -EINVAL; 1477 } 1478 1479 dev_info(&dev->dev, "CXL reset\n"); 1480 1481 /* 1482 * The adapter is about to be reset, so ignore errors. 1483 */ 1484 cxl_data_cache_flush(adapter); 1485 1486 /* pcie_warm_reset requests a fundamental pci reset which includes a 1487 * PERST assert/deassert. PERST triggers a loading of the image 1488 * if "user" or "factory" is selected in sysfs */ 1489 if ((rc = pci_set_pcie_reset_state(dev, pcie_warm_reset))) { 1490 dev_err(&dev->dev, "cxl: pcie_warm_reset failed\n"); 1491 return rc; 1492 } 1493 1494 return rc; 1495 } 1496 1497 static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev) 1498 { 1499 if (pci_request_region(dev, 2, "priv 2 regs")) 1500 goto err1; 1501 if (pci_request_region(dev, 0, "priv 1 regs")) 1502 goto err2; 1503 1504 pr_devel("cxl_map_adapter_regs: p1: %#016llx %#llx, p2: %#016llx %#llx", 1505 p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev)); 1506 1507 if (!(adapter->native->p1_mmio = ioremap(p1_base(dev), p1_size(dev)))) 1508 goto err3; 1509 1510 if (!(adapter->native->p2_mmio = ioremap(p2_base(dev), p2_size(dev)))) 1511 goto err4; 1512 1513 return 0; 1514 1515 err4: 1516 iounmap(adapter->native->p1_mmio); 1517 adapter->native->p1_mmio = NULL; 1518 err3: 1519 pci_release_region(dev, 0); 1520 err2: 1521 pci_release_region(dev, 2); 1522 err1: 1523 return -ENOMEM; 1524 } 1525 1526 static void cxl_unmap_adapter_regs(struct cxl *adapter) 1527 { 1528 if (adapter->native->p1_mmio) { 1529 iounmap(adapter->native->p1_mmio); 1530 adapter->native->p1_mmio = NULL; 1531 pci_release_region(to_pci_dev(adapter->dev.parent), 2); 1532 } 1533 if (adapter->native->p2_mmio) { 1534 iounmap(adapter->native->p2_mmio); 1535 adapter->native->p2_mmio = NULL; 1536 pci_release_region(to_pci_dev(adapter->dev.parent), 0); 1537 } 1538 } 1539 1540 static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev) 1541 { 1542 int vsec; 1543 u32 afu_desc_off, afu_desc_size; 1544 u32 ps_off, ps_size; 1545 u16 vseclen; 1546 u8 image_state; 1547 1548 if (!(vsec = find_cxl_vsec(dev))) { 1549 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n"); 1550 return -ENODEV; 1551 } 1552 1553 CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen); 1554 if (vseclen < CXL_VSEC_MIN_SIZE) { 1555 dev_err(&dev->dev, "ABORTING: CXL VSEC too short\n"); 1556 return -EINVAL; 1557 } 1558 1559 CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status); 1560 CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev); 1561 CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major); 1562 CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor); 1563 CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image); 1564 CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state); 1565 adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED); 1566 adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED); 1567 adapter->perst_loads_image = !!(image_state & CXL_VSEC_PERST_LOADS_IMAGE); 1568 1569 CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices); 1570 CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off); 1571 CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size); 1572 CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off); 1573 CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size); 1574 1575 /* Convert everything to bytes, because there is NO WAY I'd look at the 1576 * code a month later and forget what units these are in ;-) */ 1577 adapter->native->ps_off = ps_off * 64 * 1024; 1578 adapter->ps_size = ps_size * 64 * 1024; 1579 adapter->native->afu_desc_off = afu_desc_off * 64 * 1024; 1580 adapter->native->afu_desc_size = afu_desc_size * 64 * 1024; 1581 1582 /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */ 1583 adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices; 1584 1585 return 0; 1586 } 1587 1588 /* 1589 * Workaround a PCIe Host Bridge defect on some cards, that can cause 1590 * malformed Transaction Layer Packet (TLP) errors to be erroneously 1591 * reported. Mask this error in the Uncorrectable Error Mask Register. 1592 * 1593 * The upper nibble of the PSL revision is used to distinguish between 1594 * different cards. The affected ones have it set to 0. 1595 */ 1596 static void cxl_fixup_malformed_tlp(struct cxl *adapter, struct pci_dev *dev) 1597 { 1598 int aer; 1599 u32 data; 1600 1601 if (adapter->psl_rev & 0xf000) 1602 return; 1603 if (!(aer = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR))) 1604 return; 1605 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &data); 1606 if (data & PCI_ERR_UNC_MALF_TLP) 1607 if (data & PCI_ERR_UNC_INTN) 1608 return; 1609 data |= PCI_ERR_UNC_MALF_TLP; 1610 data |= PCI_ERR_UNC_INTN; 1611 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, data); 1612 } 1613 1614 static bool cxl_compatible_caia_version(struct cxl *adapter) 1615 { 1616 if (cxl_is_power8() && (adapter->caia_major == 1)) 1617 return true; 1618 1619 if (cxl_is_power9() && (adapter->caia_major == 2)) 1620 return true; 1621 1622 return false; 1623 } 1624 1625 static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev) 1626 { 1627 if (adapter->vsec_status & CXL_STATUS_SECOND_PORT) 1628 return -EBUSY; 1629 1630 if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) { 1631 dev_err(&dev->dev, "ABORTING: CXL requires unsupported features\n"); 1632 return -EINVAL; 1633 } 1634 1635 if (!cxl_compatible_caia_version(adapter)) { 1636 dev_info(&dev->dev, "Ignoring card. PSL type is not supported (caia version: %d)\n", 1637 adapter->caia_major); 1638 return -ENODEV; 1639 } 1640 1641 if (!adapter->slices) { 1642 /* Once we support dynamic reprogramming we can use the card if 1643 * it supports loadable AFUs */ 1644 dev_err(&dev->dev, "ABORTING: Device has no AFUs\n"); 1645 return -EINVAL; 1646 } 1647 1648 if (!adapter->native->afu_desc_off || !adapter->native->afu_desc_size) { 1649 dev_err(&dev->dev, "ABORTING: VSEC shows no AFU descriptors\n"); 1650 return -EINVAL; 1651 } 1652 1653 if (adapter->ps_size > p2_size(dev) - adapter->native->ps_off) { 1654 dev_err(&dev->dev, "ABORTING: Problem state size larger than " 1655 "available in BAR2: 0x%llx > 0x%llx\n", 1656 adapter->ps_size, p2_size(dev) - adapter->native->ps_off); 1657 return -EINVAL; 1658 } 1659 1660 return 0; 1661 } 1662 1663 ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len) 1664 { 1665 return pci_read_vpd(to_pci_dev(adapter->dev.parent), 0, len, buf); 1666 } 1667 1668 static void cxl_release_adapter(struct device *dev) 1669 { 1670 struct cxl *adapter = to_cxl_adapter(dev); 1671 1672 pr_devel("cxl_release_adapter\n"); 1673 1674 cxl_remove_adapter_nr(adapter); 1675 1676 kfree(adapter->native); 1677 kfree(adapter); 1678 } 1679 1680 #define CXL_PSL_ErrIVTE_tberror (0x1ull << (63-31)) 1681 1682 static int sanitise_adapter_regs(struct cxl *adapter) 1683 { 1684 int rc = 0; 1685 1686 /* Clear PSL tberror bit by writing 1 to it */ 1687 cxl_p1_write(adapter, CXL_PSL_ErrIVTE, CXL_PSL_ErrIVTE_tberror); 1688 1689 if (adapter->native->sl_ops->invalidate_all) { 1690 /* do not invalidate ERAT entries when not reloading on PERST */ 1691 if (cxl_is_power9() && (adapter->perst_loads_image)) 1692 return 0; 1693 rc = adapter->native->sl_ops->invalidate_all(adapter); 1694 } 1695 1696 return rc; 1697 } 1698 1699 /* This should contain *only* operations that can safely be done in 1700 * both creation and recovery. 1701 */ 1702 static int cxl_configure_adapter(struct cxl *adapter, struct pci_dev *dev) 1703 { 1704 int rc; 1705 1706 adapter->dev.parent = &dev->dev; 1707 adapter->dev.release = cxl_release_adapter; 1708 pci_set_drvdata(dev, adapter); 1709 1710 rc = pci_enable_device(dev); 1711 if (rc) { 1712 dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc); 1713 return rc; 1714 } 1715 1716 if ((rc = cxl_read_vsec(adapter, dev))) 1717 return rc; 1718 1719 if ((rc = cxl_vsec_looks_ok(adapter, dev))) 1720 return rc; 1721 1722 cxl_fixup_malformed_tlp(adapter, dev); 1723 1724 if ((rc = setup_cxl_bars(dev))) 1725 return rc; 1726 1727 if ((rc = setup_cxl_protocol_area(dev))) 1728 return rc; 1729 1730 if ((rc = cxl_update_image_control(adapter))) 1731 return rc; 1732 1733 if ((rc = cxl_map_adapter_regs(adapter, dev))) 1734 return rc; 1735 1736 if ((rc = sanitise_adapter_regs(adapter))) 1737 goto err; 1738 1739 if ((rc = adapter->native->sl_ops->adapter_regs_init(adapter, dev))) 1740 goto err; 1741 1742 /* Required for devices using CAPP DMA mode, harmless for others */ 1743 pci_set_master(dev); 1744 1745 adapter->tunneled_ops_supported = false; 1746 1747 if (cxl_is_power9()) { 1748 if (pnv_pci_set_tunnel_bar(dev, 0x00020000E0000000ull, 1)) 1749 dev_info(&dev->dev, "Tunneled operations unsupported\n"); 1750 else 1751 adapter->tunneled_ops_supported = true; 1752 } 1753 1754 if ((rc = pnv_phb_to_cxl_mode(dev, adapter->native->sl_ops->capi_mode))) 1755 goto err; 1756 1757 /* If recovery happened, the last step is to turn on snooping. 1758 * In the non-recovery case this has no effect */ 1759 if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON))) 1760 goto err; 1761 1762 /* Ignore error, adapter init is not dependant on timebase sync */ 1763 cxl_setup_psl_timebase(adapter, dev); 1764 1765 if ((rc = cxl_native_register_psl_err_irq(adapter))) 1766 goto err; 1767 1768 return 0; 1769 1770 err: 1771 cxl_unmap_adapter_regs(adapter); 1772 return rc; 1773 1774 } 1775 1776 static void cxl_deconfigure_adapter(struct cxl *adapter) 1777 { 1778 struct pci_dev *pdev = to_pci_dev(adapter->dev.parent); 1779 1780 if (cxl_is_power9()) 1781 pnv_pci_set_tunnel_bar(pdev, 0x00020000E0000000ull, 0); 1782 1783 cxl_native_release_psl_err_irq(adapter); 1784 cxl_unmap_adapter_regs(adapter); 1785 1786 pci_disable_device(pdev); 1787 } 1788 1789 static void cxl_stop_trace_psl9(struct cxl *adapter) 1790 { 1791 int traceid; 1792 u64 trace_state, trace_mask; 1793 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 1794 1795 /* read each tracearray state and issue mmio to stop them is needed */ 1796 for (traceid = 0; traceid <= CXL_PSL9_TRACEID_MAX; ++traceid) { 1797 trace_state = cxl_p1_read(adapter, CXL_PSL9_CTCCFG); 1798 trace_mask = (0x3ULL << (62 - traceid * 2)); 1799 trace_state = (trace_state & trace_mask) >> (62 - traceid * 2); 1800 dev_dbg(&dev->dev, "cxl: Traceid-%d trace_state=0x%0llX\n", 1801 traceid, trace_state); 1802 1803 /* issue mmio if the trace array isn't in FIN state */ 1804 if (trace_state != CXL_PSL9_TRACESTATE_FIN) 1805 cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 1806 0x8400000000000000ULL | traceid); 1807 } 1808 } 1809 1810 static void cxl_stop_trace_psl8(struct cxl *adapter) 1811 { 1812 int slice; 1813 1814 /* Stop the trace */ 1815 cxl_p1_write(adapter, CXL_PSL_TRACE, 0x8000000000000017LL); 1816 1817 /* Stop the slice traces */ 1818 spin_lock(&adapter->afu_list_lock); 1819 for (slice = 0; slice < adapter->slices; slice++) { 1820 if (adapter->afu[slice]) 1821 cxl_p1n_write(adapter->afu[slice], CXL_PSL_SLICE_TRACE, 1822 0x8000000000000000LL); 1823 } 1824 spin_unlock(&adapter->afu_list_lock); 1825 } 1826 1827 static const struct cxl_service_layer_ops psl9_ops = { 1828 .adapter_regs_init = init_implementation_adapter_regs_psl9, 1829 .invalidate_all = cxl_invalidate_all_psl9, 1830 .afu_regs_init = init_implementation_afu_regs_psl9, 1831 .sanitise_afu_regs = sanitise_afu_regs_psl9, 1832 .register_serr_irq = cxl_native_register_serr_irq, 1833 .release_serr_irq = cxl_native_release_serr_irq, 1834 .handle_interrupt = cxl_irq_psl9, 1835 .fail_irq = cxl_fail_irq_psl, 1836 .activate_dedicated_process = cxl_activate_dedicated_process_psl9, 1837 .attach_afu_directed = cxl_attach_afu_directed_psl9, 1838 .attach_dedicated_process = cxl_attach_dedicated_process_psl9, 1839 .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl9, 1840 .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl9, 1841 .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl9, 1842 .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl9, 1843 .err_irq_dump_registers = cxl_native_err_irq_dump_regs_psl9, 1844 .debugfs_stop_trace = cxl_stop_trace_psl9, 1845 .timebase_read = timebase_read_psl9, 1846 .capi_mode = OPAL_PHB_CAPI_MODE_CAPI, 1847 .needs_reset_before_disable = true, 1848 }; 1849 1850 static const struct cxl_service_layer_ops psl8_ops = { 1851 .adapter_regs_init = init_implementation_adapter_regs_psl8, 1852 .invalidate_all = cxl_invalidate_all_psl8, 1853 .afu_regs_init = init_implementation_afu_regs_psl8, 1854 .sanitise_afu_regs = sanitise_afu_regs_psl8, 1855 .register_serr_irq = cxl_native_register_serr_irq, 1856 .release_serr_irq = cxl_native_release_serr_irq, 1857 .handle_interrupt = cxl_irq_psl8, 1858 .fail_irq = cxl_fail_irq_psl, 1859 .activate_dedicated_process = cxl_activate_dedicated_process_psl8, 1860 .attach_afu_directed = cxl_attach_afu_directed_psl8, 1861 .attach_dedicated_process = cxl_attach_dedicated_process_psl8, 1862 .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl8, 1863 .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl8, 1864 .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl8, 1865 .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl8, 1866 .err_irq_dump_registers = cxl_native_err_irq_dump_regs_psl8, 1867 .debugfs_stop_trace = cxl_stop_trace_psl8, 1868 .write_timebase_ctrl = write_timebase_ctrl_psl8, 1869 .timebase_read = timebase_read_psl8, 1870 .capi_mode = OPAL_PHB_CAPI_MODE_CAPI, 1871 .needs_reset_before_disable = true, 1872 }; 1873 1874 static const struct cxl_service_layer_ops xsl_ops = { 1875 .adapter_regs_init = init_implementation_adapter_regs_xsl, 1876 .invalidate_all = cxl_invalidate_all_psl8, 1877 .sanitise_afu_regs = sanitise_afu_regs_psl8, 1878 .handle_interrupt = cxl_irq_psl8, 1879 .fail_irq = cxl_fail_irq_psl, 1880 .activate_dedicated_process = cxl_activate_dedicated_process_psl8, 1881 .attach_afu_directed = cxl_attach_afu_directed_psl8, 1882 .attach_dedicated_process = cxl_attach_dedicated_process_psl8, 1883 .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl8, 1884 .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_xsl, 1885 .write_timebase_ctrl = write_timebase_ctrl_xsl, 1886 .timebase_read = timebase_read_xsl, 1887 .capi_mode = OPAL_PHB_CAPI_MODE_DMA, 1888 }; 1889 1890 static void set_sl_ops(struct cxl *adapter, struct pci_dev *dev) 1891 { 1892 if (dev->vendor == PCI_VENDOR_ID_MELLANOX && dev->device == 0x1013) { 1893 /* Mellanox CX-4 */ 1894 dev_info(&dev->dev, "Device uses an XSL\n"); 1895 adapter->native->sl_ops = &xsl_ops; 1896 adapter->min_pe = 1; /* Workaround for CX-4 hardware bug */ 1897 } else { 1898 if (cxl_is_power8()) { 1899 dev_info(&dev->dev, "Device uses a PSL8\n"); 1900 adapter->native->sl_ops = &psl8_ops; 1901 } else { 1902 dev_info(&dev->dev, "Device uses a PSL9\n"); 1903 adapter->native->sl_ops = &psl9_ops; 1904 } 1905 } 1906 } 1907 1908 1909 static struct cxl *cxl_pci_init_adapter(struct pci_dev *dev) 1910 { 1911 struct cxl *adapter; 1912 int rc; 1913 1914 adapter = cxl_alloc_adapter(); 1915 if (!adapter) 1916 return ERR_PTR(-ENOMEM); 1917 1918 adapter->native = kzalloc(sizeof(struct cxl_native), GFP_KERNEL); 1919 if (!adapter->native) { 1920 rc = -ENOMEM; 1921 goto err_release; 1922 } 1923 1924 set_sl_ops(adapter, dev); 1925 1926 /* Set defaults for parameters which need to persist over 1927 * configure/reconfigure 1928 */ 1929 adapter->perst_loads_image = true; 1930 adapter->perst_same_image = false; 1931 1932 rc = cxl_configure_adapter(adapter, dev); 1933 if (rc) { 1934 pci_disable_device(dev); 1935 goto err_release; 1936 } 1937 1938 /* Don't care if this one fails: */ 1939 cxl_debugfs_adapter_add(adapter); 1940 1941 /* 1942 * After we call this function we must not free the adapter directly, 1943 * even if it returns an error! 1944 */ 1945 if ((rc = cxl_register_adapter(adapter))) 1946 goto err_put1; 1947 1948 if ((rc = cxl_sysfs_adapter_add(adapter))) 1949 goto err_put1; 1950 1951 /* Release the context lock as adapter is configured */ 1952 cxl_adapter_context_unlock(adapter); 1953 1954 return adapter; 1955 1956 err_put1: 1957 /* This should mirror cxl_remove_adapter, except without the 1958 * sysfs parts 1959 */ 1960 cxl_debugfs_adapter_remove(adapter); 1961 cxl_deconfigure_adapter(adapter); 1962 device_unregister(&adapter->dev); 1963 return ERR_PTR(rc); 1964 1965 err_release: 1966 cxl_release_adapter(&adapter->dev); 1967 return ERR_PTR(rc); 1968 } 1969 1970 static void cxl_pci_remove_adapter(struct cxl *adapter) 1971 { 1972 pr_devel("cxl_remove_adapter\n"); 1973 1974 cxl_sysfs_adapter_remove(adapter); 1975 cxl_debugfs_adapter_remove(adapter); 1976 1977 /* 1978 * Flush adapter datacache as its about to be removed. 1979 */ 1980 cxl_data_cache_flush(adapter); 1981 1982 cxl_deconfigure_adapter(adapter); 1983 1984 device_unregister(&adapter->dev); 1985 } 1986 1987 #define CXL_MAX_PCIEX_PARENT 2 1988 1989 int cxl_slot_is_switched(struct pci_dev *dev) 1990 { 1991 struct device_node *np; 1992 int depth = 0; 1993 const __be32 *prop; 1994 1995 if (!(np = pci_device_to_OF_node(dev))) { 1996 pr_err("cxl: np = NULL\n"); 1997 return -ENODEV; 1998 } 1999 of_node_get(np); 2000 while (np) { 2001 np = of_get_next_parent(np); 2002 prop = of_get_property(np, "device_type", NULL); 2003 if (!prop || strcmp((char *)prop, "pciex")) 2004 break; 2005 depth++; 2006 } 2007 of_node_put(np); 2008 return (depth > CXL_MAX_PCIEX_PARENT); 2009 } 2010 2011 bool cxl_slot_is_supported(struct pci_dev *dev, int flags) 2012 { 2013 if (!cpu_has_feature(CPU_FTR_HVMODE)) 2014 return false; 2015 2016 if ((flags & CXL_SLOT_FLAG_DMA) && (!pvr_version_is(PVR_POWER8NVL))) { 2017 /* 2018 * CAPP DMA mode is technically supported on regular P8, but 2019 * will EEH if the card attempts to access memory < 4GB, which 2020 * we cannot realistically avoid. We might be able to work 2021 * around the issue, but until then return unsupported: 2022 */ 2023 return false; 2024 } 2025 2026 if (cxl_slot_is_switched(dev)) 2027 return false; 2028 2029 /* 2030 * XXX: This gets a little tricky on regular P8 (not POWER8NVL) since 2031 * the CAPP can be connected to PHB 0, 1 or 2 on a first come first 2032 * served basis, which is racy to check from here. If we need to 2033 * support this in future we might need to consider having this 2034 * function effectively reserve it ahead of time. 2035 * 2036 * Currently, the only user of this API is the Mellanox CX4, which is 2037 * only supported on P8NVL due to the above mentioned limitation of 2038 * CAPP DMA mode and therefore does not need to worry about this. If the 2039 * issue with CAPP DMA mode is later worked around on P8 we might need 2040 * to revisit this. 2041 */ 2042 2043 return true; 2044 } 2045 EXPORT_SYMBOL_GPL(cxl_slot_is_supported); 2046 2047 2048 static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id) 2049 { 2050 struct cxl *adapter; 2051 int slice; 2052 int rc; 2053 2054 if (cxl_pci_is_vphb_device(dev)) { 2055 dev_dbg(&dev->dev, "cxl_init_adapter: Ignoring cxl vphb device\n"); 2056 return -ENODEV; 2057 } 2058 2059 if (cxl_slot_is_switched(dev)) { 2060 dev_info(&dev->dev, "Ignoring card on incompatible PCI slot\n"); 2061 return -ENODEV; 2062 } 2063 2064 if (cxl_is_power9() && !radix_enabled()) { 2065 dev_info(&dev->dev, "Only Radix mode supported\n"); 2066 return -ENODEV; 2067 } 2068 2069 if (cxl_verbose) 2070 dump_cxl_config_space(dev); 2071 2072 adapter = cxl_pci_init_adapter(dev); 2073 if (IS_ERR(adapter)) { 2074 dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter)); 2075 return PTR_ERR(adapter); 2076 } 2077 2078 for (slice = 0; slice < adapter->slices; slice++) { 2079 if ((rc = pci_init_afu(adapter, slice, dev))) { 2080 dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc); 2081 continue; 2082 } 2083 2084 rc = cxl_afu_select_best_mode(adapter->afu[slice]); 2085 if (rc) 2086 dev_err(&dev->dev, "AFU %i failed to start: %i\n", slice, rc); 2087 } 2088 2089 if (pnv_pci_on_cxl_phb(dev) && adapter->slices >= 1) 2090 pnv_cxl_phb_set_peer_afu(dev, adapter->afu[0]); 2091 2092 return 0; 2093 } 2094 2095 static void cxl_remove(struct pci_dev *dev) 2096 { 2097 struct cxl *adapter = pci_get_drvdata(dev); 2098 struct cxl_afu *afu; 2099 int i; 2100 2101 /* 2102 * Lock to prevent someone grabbing a ref through the adapter list as 2103 * we are removing it 2104 */ 2105 for (i = 0; i < adapter->slices; i++) { 2106 afu = adapter->afu[i]; 2107 cxl_pci_remove_afu(afu); 2108 } 2109 cxl_pci_remove_adapter(adapter); 2110 } 2111 2112 static pci_ers_result_t cxl_vphb_error_detected(struct cxl_afu *afu, 2113 pci_channel_state_t state) 2114 { 2115 struct pci_dev *afu_dev; 2116 pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET; 2117 pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET; 2118 2119 /* There should only be one entry, but go through the list 2120 * anyway 2121 */ 2122 if (afu->phb == NULL) 2123 return result; 2124 2125 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) { 2126 if (!afu_dev->driver) 2127 continue; 2128 2129 afu_dev->error_state = state; 2130 2131 if (afu_dev->driver->err_handler) 2132 afu_result = afu_dev->driver->err_handler->error_detected(afu_dev, 2133 state); 2134 /* Disconnect trumps all, NONE trumps NEED_RESET */ 2135 if (afu_result == PCI_ERS_RESULT_DISCONNECT) 2136 result = PCI_ERS_RESULT_DISCONNECT; 2137 else if ((afu_result == PCI_ERS_RESULT_NONE) && 2138 (result == PCI_ERS_RESULT_NEED_RESET)) 2139 result = PCI_ERS_RESULT_NONE; 2140 } 2141 return result; 2142 } 2143 2144 static pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, 2145 pci_channel_state_t state) 2146 { 2147 struct cxl *adapter = pci_get_drvdata(pdev); 2148 struct cxl_afu *afu; 2149 pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET, afu_result; 2150 int i; 2151 2152 /* At this point, we could still have an interrupt pending. 2153 * Let's try to get them out of the way before they do 2154 * anything we don't like. 2155 */ 2156 schedule(); 2157 2158 /* If we're permanently dead, give up. */ 2159 if (state == pci_channel_io_perm_failure) { 2160 for (i = 0; i < adapter->slices; i++) { 2161 afu = adapter->afu[i]; 2162 /* 2163 * Tell the AFU drivers; but we don't care what they 2164 * say, we're going away. 2165 */ 2166 cxl_vphb_error_detected(afu, state); 2167 } 2168 return PCI_ERS_RESULT_DISCONNECT; 2169 } 2170 2171 /* Are we reflashing? 2172 * 2173 * If we reflash, we could come back as something entirely 2174 * different, including a non-CAPI card. As such, by default 2175 * we don't participate in the process. We'll be unbound and 2176 * the slot re-probed. (TODO: check EEH doesn't blindly rebind 2177 * us!) 2178 * 2179 * However, this isn't the entire story: for reliablity 2180 * reasons, we usually want to reflash the FPGA on PERST in 2181 * order to get back to a more reliable known-good state. 2182 * 2183 * This causes us a bit of a problem: if we reflash we can't 2184 * trust that we'll come back the same - we could have a new 2185 * image and been PERSTed in order to load that 2186 * image. However, most of the time we actually *will* come 2187 * back the same - for example a regular EEH event. 2188 * 2189 * Therefore, we allow the user to assert that the image is 2190 * indeed the same and that we should continue on into EEH 2191 * anyway. 2192 */ 2193 if (adapter->perst_loads_image && !adapter->perst_same_image) { 2194 /* TODO take the PHB out of CXL mode */ 2195 dev_info(&pdev->dev, "reflashing, so opting out of EEH!\n"); 2196 return PCI_ERS_RESULT_NONE; 2197 } 2198 2199 /* 2200 * At this point, we want to try to recover. We'll always 2201 * need a complete slot reset: we don't trust any other reset. 2202 * 2203 * Now, we go through each AFU: 2204 * - We send the driver, if bound, an error_detected callback. 2205 * We expect it to clean up, but it can also tell us to give 2206 * up and permanently detach the card. To simplify things, if 2207 * any bound AFU driver doesn't support EEH, we give up on EEH. 2208 * 2209 * - We detach all contexts associated with the AFU. This 2210 * does not free them, but puts them into a CLOSED state 2211 * which causes any the associated files to return useful 2212 * errors to userland. It also unmaps, but does not free, 2213 * any IRQs. 2214 * 2215 * - We clean up our side: releasing and unmapping resources we hold 2216 * so we can wire them up again when the hardware comes back up. 2217 * 2218 * Driver authors should note: 2219 * 2220 * - Any contexts you create in your kernel driver (except 2221 * those associated with anonymous file descriptors) are 2222 * your responsibility to free and recreate. Likewise with 2223 * any attached resources. 2224 * 2225 * - We will take responsibility for re-initialising the 2226 * device context (the one set up for you in 2227 * cxl_pci_enable_device_hook and accessed through 2228 * cxl_get_context). If you've attached IRQs or other 2229 * resources to it, they remains yours to free. 2230 * 2231 * You can call the same functions to release resources as you 2232 * normally would: we make sure that these functions continue 2233 * to work when the hardware is down. 2234 * 2235 * Two examples: 2236 * 2237 * 1) If you normally free all your resources at the end of 2238 * each request, or if you use anonymous FDs, your 2239 * error_detected callback can simply set a flag to tell 2240 * your driver not to start any new calls. You can then 2241 * clear the flag in the resume callback. 2242 * 2243 * 2) If you normally allocate your resources on startup: 2244 * * Set a flag in error_detected as above. 2245 * * Let CXL detach your contexts. 2246 * * In slot_reset, free the old resources and allocate new ones. 2247 * * In resume, clear the flag to allow things to start. 2248 */ 2249 for (i = 0; i < adapter->slices; i++) { 2250 afu = adapter->afu[i]; 2251 2252 afu_result = cxl_vphb_error_detected(afu, state); 2253 2254 cxl_context_detach_all(afu); 2255 cxl_ops->afu_deactivate_mode(afu, afu->current_mode); 2256 pci_deconfigure_afu(afu); 2257 2258 /* Disconnect trumps all, NONE trumps NEED_RESET */ 2259 if (afu_result == PCI_ERS_RESULT_DISCONNECT) 2260 result = PCI_ERS_RESULT_DISCONNECT; 2261 else if ((afu_result == PCI_ERS_RESULT_NONE) && 2262 (result == PCI_ERS_RESULT_NEED_RESET)) 2263 result = PCI_ERS_RESULT_NONE; 2264 } 2265 2266 /* should take the context lock here */ 2267 if (cxl_adapter_context_lock(adapter) != 0) 2268 dev_warn(&adapter->dev, 2269 "Couldn't take context lock with %d active-contexts\n", 2270 atomic_read(&adapter->contexts_num)); 2271 2272 cxl_deconfigure_adapter(adapter); 2273 2274 return result; 2275 } 2276 2277 static pci_ers_result_t cxl_pci_slot_reset(struct pci_dev *pdev) 2278 { 2279 struct cxl *adapter = pci_get_drvdata(pdev); 2280 struct cxl_afu *afu; 2281 struct cxl_context *ctx; 2282 struct pci_dev *afu_dev; 2283 pci_ers_result_t afu_result = PCI_ERS_RESULT_RECOVERED; 2284 pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED; 2285 int i; 2286 2287 if (cxl_configure_adapter(adapter, pdev)) 2288 goto err; 2289 2290 /* 2291 * Unlock context activation for the adapter. Ideally this should be 2292 * done in cxl_pci_resume but cxlflash module tries to activate the 2293 * master context as part of slot_reset callback. 2294 */ 2295 cxl_adapter_context_unlock(adapter); 2296 2297 for (i = 0; i < adapter->slices; i++) { 2298 afu = adapter->afu[i]; 2299 2300 if (pci_configure_afu(afu, adapter, pdev)) 2301 goto err; 2302 2303 if (cxl_afu_select_best_mode(afu)) 2304 goto err; 2305 2306 if (afu->phb == NULL) 2307 continue; 2308 2309 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) { 2310 /* Reset the device context. 2311 * TODO: make this less disruptive 2312 */ 2313 ctx = cxl_get_context(afu_dev); 2314 2315 if (ctx && cxl_release_context(ctx)) 2316 goto err; 2317 2318 ctx = cxl_dev_context_init(afu_dev); 2319 if (IS_ERR(ctx)) 2320 goto err; 2321 2322 afu_dev->dev.archdata.cxl_ctx = ctx; 2323 2324 if (cxl_ops->afu_check_and_enable(afu)) 2325 goto err; 2326 2327 afu_dev->error_state = pci_channel_io_normal; 2328 2329 /* If there's a driver attached, allow it to 2330 * chime in on recovery. Drivers should check 2331 * if everything has come back OK, but 2332 * shouldn't start new work until we call 2333 * their resume function. 2334 */ 2335 if (!afu_dev->driver) 2336 continue; 2337 2338 if (afu_dev->driver->err_handler && 2339 afu_dev->driver->err_handler->slot_reset) 2340 afu_result = afu_dev->driver->err_handler->slot_reset(afu_dev); 2341 2342 if (afu_result == PCI_ERS_RESULT_DISCONNECT) 2343 result = PCI_ERS_RESULT_DISCONNECT; 2344 } 2345 } 2346 return result; 2347 2348 err: 2349 /* All the bits that happen in both error_detected and cxl_remove 2350 * should be idempotent, so we don't need to worry about leaving a mix 2351 * of unconfigured and reconfigured resources. 2352 */ 2353 dev_err(&pdev->dev, "EEH recovery failed. Asking to be disconnected.\n"); 2354 return PCI_ERS_RESULT_DISCONNECT; 2355 } 2356 2357 static void cxl_pci_resume(struct pci_dev *pdev) 2358 { 2359 struct cxl *adapter = pci_get_drvdata(pdev); 2360 struct cxl_afu *afu; 2361 struct pci_dev *afu_dev; 2362 int i; 2363 2364 /* Everything is back now. Drivers should restart work now. 2365 * This is not the place to be checking if everything came back up 2366 * properly, because there's no return value: do that in slot_reset. 2367 */ 2368 for (i = 0; i < adapter->slices; i++) { 2369 afu = adapter->afu[i]; 2370 2371 if (afu->phb == NULL) 2372 continue; 2373 2374 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) { 2375 if (afu_dev->driver && afu_dev->driver->err_handler && 2376 afu_dev->driver->err_handler->resume) 2377 afu_dev->driver->err_handler->resume(afu_dev); 2378 } 2379 } 2380 } 2381 2382 static const struct pci_error_handlers cxl_err_handler = { 2383 .error_detected = cxl_pci_error_detected, 2384 .slot_reset = cxl_pci_slot_reset, 2385 .resume = cxl_pci_resume, 2386 }; 2387 2388 struct pci_driver cxl_pci_driver = { 2389 .name = "cxl-pci", 2390 .id_table = cxl_pci_tbl, 2391 .probe = cxl_probe, 2392 .remove = cxl_remove, 2393 .shutdown = cxl_remove, 2394 .err_handler = &cxl_err_handler, 2395 }; 2396