1 /* 2 * Copyright 2014 IBM Corp. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 */ 9 10 #include <linux/pci_regs.h> 11 #include <linux/pci_ids.h> 12 #include <linux/device.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/slab.h> 16 #include <linux/sort.h> 17 #include <linux/pci.h> 18 #include <linux/of.h> 19 #include <linux/delay.h> 20 #include <asm/opal.h> 21 #include <asm/msi_bitmap.h> 22 #include <asm/pci-bridge.h> /* for struct pci_controller */ 23 #include <asm/pnv-pci.h> 24 25 #include "cxl.h" 26 27 28 #define CXL_PCI_VSEC_ID 0x1280 29 #define CXL_VSEC_MIN_SIZE 0x80 30 31 #define CXL_READ_VSEC_LENGTH(dev, vsec, dest) \ 32 { \ 33 pci_read_config_word(dev, vsec + 0x6, dest); \ 34 *dest >>= 4; \ 35 } 36 #define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \ 37 pci_read_config_byte(dev, vsec + 0x8, dest) 38 39 #define CXL_READ_VSEC_STATUS(dev, vsec, dest) \ 40 pci_read_config_byte(dev, vsec + 0x9, dest) 41 #define CXL_STATUS_SECOND_PORT 0x80 42 #define CXL_STATUS_MSI_X_FULL 0x40 43 #define CXL_STATUS_MSI_X_SINGLE 0x20 44 #define CXL_STATUS_FLASH_RW 0x08 45 #define CXL_STATUS_FLASH_RO 0x04 46 #define CXL_STATUS_LOADABLE_AFU 0x02 47 #define CXL_STATUS_LOADABLE_PSL 0x01 48 /* If we see these features we won't try to use the card */ 49 #define CXL_UNSUPPORTED_FEATURES \ 50 (CXL_STATUS_MSI_X_FULL | CXL_STATUS_MSI_X_SINGLE) 51 52 #define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \ 53 pci_read_config_byte(dev, vsec + 0xa, dest) 54 #define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \ 55 pci_write_config_byte(dev, vsec + 0xa, val) 56 #define CXL_VSEC_PROTOCOL_MASK 0xe0 57 #define CXL_VSEC_PROTOCOL_1024TB 0x80 58 #define CXL_VSEC_PROTOCOL_512TB 0x40 59 #define CXL_VSEC_PROTOCOL_256TB 0x20 /* Power 8 uses this */ 60 #define CXL_VSEC_PROTOCOL_ENABLE 0x01 61 62 #define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \ 63 pci_read_config_word(dev, vsec + 0xc, dest) 64 #define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \ 65 pci_read_config_byte(dev, vsec + 0xe, dest) 66 #define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \ 67 pci_read_config_byte(dev, vsec + 0xf, dest) 68 #define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \ 69 pci_read_config_word(dev, vsec + 0x10, dest) 70 71 #define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \ 72 pci_read_config_byte(dev, vsec + 0x13, dest) 73 #define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \ 74 pci_write_config_byte(dev, vsec + 0x13, val) 75 #define CXL_VSEC_USER_IMAGE_LOADED 0x80 /* RO */ 76 #define CXL_VSEC_PERST_LOADS_IMAGE 0x20 /* RW */ 77 #define CXL_VSEC_PERST_SELECT_USER 0x10 /* RW */ 78 79 #define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \ 80 pci_read_config_dword(dev, vsec + 0x20, dest) 81 #define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \ 82 pci_read_config_dword(dev, vsec + 0x24, dest) 83 #define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \ 84 pci_read_config_dword(dev, vsec + 0x28, dest) 85 #define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \ 86 pci_read_config_dword(dev, vsec + 0x2c, dest) 87 88 89 /* This works a little different than the p1/p2 register accesses to make it 90 * easier to pull out individual fields */ 91 #define AFUD_READ(afu, off) in_be64(afu->afu_desc_mmio + off) 92 #define EXTRACT_PPC_BIT(val, bit) (!!(val & PPC_BIT(bit))) 93 #define EXTRACT_PPC_BITS(val, bs, be) ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be)) 94 95 #define AFUD_READ_INFO(afu) AFUD_READ(afu, 0x0) 96 #define AFUD_NUM_INTS_PER_PROC(val) EXTRACT_PPC_BITS(val, 0, 15) 97 #define AFUD_NUM_PROCS(val) EXTRACT_PPC_BITS(val, 16, 31) 98 #define AFUD_NUM_CRS(val) EXTRACT_PPC_BITS(val, 32, 47) 99 #define AFUD_MULTIMODE(val) EXTRACT_PPC_BIT(val, 48) 100 #define AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55) 101 #define AFUD_DEDICATED_PROCESS(val) EXTRACT_PPC_BIT(val, 59) 102 #define AFUD_AFU_DIRECTED(val) EXTRACT_PPC_BIT(val, 61) 103 #define AFUD_TIME_SLICED(val) EXTRACT_PPC_BIT(val, 63) 104 #define AFUD_READ_CR(afu) AFUD_READ(afu, 0x20) 105 #define AFUD_CR_LEN(val) EXTRACT_PPC_BITS(val, 8, 63) 106 #define AFUD_READ_CR_OFF(afu) AFUD_READ(afu, 0x28) 107 #define AFUD_READ_PPPSA(afu) AFUD_READ(afu, 0x30) 108 #define AFUD_PPPSA_PP(val) EXTRACT_PPC_BIT(val, 6) 109 #define AFUD_PPPSA_PSA(val) EXTRACT_PPC_BIT(val, 7) 110 #define AFUD_PPPSA_LEN(val) EXTRACT_PPC_BITS(val, 8, 63) 111 #define AFUD_READ_PPPSA_OFF(afu) AFUD_READ(afu, 0x38) 112 #define AFUD_READ_EB(afu) AFUD_READ(afu, 0x40) 113 #define AFUD_EB_LEN(val) EXTRACT_PPC_BITS(val, 8, 63) 114 #define AFUD_READ_EB_OFF(afu) AFUD_READ(afu, 0x48) 115 116 static DEFINE_PCI_DEVICE_TABLE(cxl_pci_tbl) = { 117 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), }, 118 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), }, 119 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), }, 120 { PCI_DEVICE_CLASS(0x120000, ~0), }, 121 122 { } 123 }; 124 MODULE_DEVICE_TABLE(pci, cxl_pci_tbl); 125 126 127 /* 128 * Mostly using these wrappers to avoid confusion: 129 * priv 1 is BAR2, while priv 2 is BAR0 130 */ 131 static inline resource_size_t p1_base(struct pci_dev *dev) 132 { 133 return pci_resource_start(dev, 2); 134 } 135 136 static inline resource_size_t p1_size(struct pci_dev *dev) 137 { 138 return pci_resource_len(dev, 2); 139 } 140 141 static inline resource_size_t p2_base(struct pci_dev *dev) 142 { 143 return pci_resource_start(dev, 0); 144 } 145 146 static inline resource_size_t p2_size(struct pci_dev *dev) 147 { 148 return pci_resource_len(dev, 0); 149 } 150 151 static int find_cxl_vsec(struct pci_dev *dev) 152 { 153 int vsec = 0; 154 u16 val; 155 156 while ((vsec = pci_find_next_ext_capability(dev, vsec, PCI_EXT_CAP_ID_VNDR))) { 157 pci_read_config_word(dev, vsec + 0x4, &val); 158 if (val == CXL_PCI_VSEC_ID) 159 return vsec; 160 } 161 return 0; 162 163 } 164 165 static void dump_cxl_config_space(struct pci_dev *dev) 166 { 167 int vsec; 168 u32 val; 169 170 dev_info(&dev->dev, "dump_cxl_config_space\n"); 171 172 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val); 173 dev_info(&dev->dev, "BAR0: %#.8x\n", val); 174 pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val); 175 dev_info(&dev->dev, "BAR1: %#.8x\n", val); 176 pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val); 177 dev_info(&dev->dev, "BAR2: %#.8x\n", val); 178 pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val); 179 dev_info(&dev->dev, "BAR3: %#.8x\n", val); 180 pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val); 181 dev_info(&dev->dev, "BAR4: %#.8x\n", val); 182 pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val); 183 dev_info(&dev->dev, "BAR5: %#.8x\n", val); 184 185 dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n", 186 p1_base(dev), p1_size(dev)); 187 dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n", 188 p1_base(dev), p2_size(dev)); 189 dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n", 190 pci_resource_start(dev, 4), pci_resource_len(dev, 4)); 191 192 if (!(vsec = find_cxl_vsec(dev))) 193 return; 194 195 #define show_reg(name, what) \ 196 dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what) 197 198 pci_read_config_dword(dev, vsec + 0x0, &val); 199 show_reg("Cap ID", (val >> 0) & 0xffff); 200 show_reg("Cap Ver", (val >> 16) & 0xf); 201 show_reg("Next Cap Ptr", (val >> 20) & 0xfff); 202 pci_read_config_dword(dev, vsec + 0x4, &val); 203 show_reg("VSEC ID", (val >> 0) & 0xffff); 204 show_reg("VSEC Rev", (val >> 16) & 0xf); 205 show_reg("VSEC Length", (val >> 20) & 0xfff); 206 pci_read_config_dword(dev, vsec + 0x8, &val); 207 show_reg("Num AFUs", (val >> 0) & 0xff); 208 show_reg("Status", (val >> 8) & 0xff); 209 show_reg("Mode Control", (val >> 16) & 0xff); 210 show_reg("Reserved", (val >> 24) & 0xff); 211 pci_read_config_dword(dev, vsec + 0xc, &val); 212 show_reg("PSL Rev", (val >> 0) & 0xffff); 213 show_reg("CAIA Ver", (val >> 16) & 0xffff); 214 pci_read_config_dword(dev, vsec + 0x10, &val); 215 show_reg("Base Image Rev", (val >> 0) & 0xffff); 216 show_reg("Reserved", (val >> 16) & 0x0fff); 217 show_reg("Image Control", (val >> 28) & 0x3); 218 show_reg("Reserved", (val >> 30) & 0x1); 219 show_reg("Image Loaded", (val >> 31) & 0x1); 220 221 pci_read_config_dword(dev, vsec + 0x14, &val); 222 show_reg("Reserved", val); 223 pci_read_config_dword(dev, vsec + 0x18, &val); 224 show_reg("Reserved", val); 225 pci_read_config_dword(dev, vsec + 0x1c, &val); 226 show_reg("Reserved", val); 227 228 pci_read_config_dword(dev, vsec + 0x20, &val); 229 show_reg("AFU Descriptor Offset", val); 230 pci_read_config_dword(dev, vsec + 0x24, &val); 231 show_reg("AFU Descriptor Size", val); 232 pci_read_config_dword(dev, vsec + 0x28, &val); 233 show_reg("Problem State Offset", val); 234 pci_read_config_dword(dev, vsec + 0x2c, &val); 235 show_reg("Problem State Size", val); 236 237 pci_read_config_dword(dev, vsec + 0x30, &val); 238 show_reg("Reserved", val); 239 pci_read_config_dword(dev, vsec + 0x34, &val); 240 show_reg("Reserved", val); 241 pci_read_config_dword(dev, vsec + 0x38, &val); 242 show_reg("Reserved", val); 243 pci_read_config_dword(dev, vsec + 0x3c, &val); 244 show_reg("Reserved", val); 245 246 pci_read_config_dword(dev, vsec + 0x40, &val); 247 show_reg("PSL Programming Port", val); 248 pci_read_config_dword(dev, vsec + 0x44, &val); 249 show_reg("PSL Programming Control", val); 250 251 pci_read_config_dword(dev, vsec + 0x48, &val); 252 show_reg("Reserved", val); 253 pci_read_config_dword(dev, vsec + 0x4c, &val); 254 show_reg("Reserved", val); 255 256 pci_read_config_dword(dev, vsec + 0x50, &val); 257 show_reg("Flash Address Register", val); 258 pci_read_config_dword(dev, vsec + 0x54, &val); 259 show_reg("Flash Size Register", val); 260 pci_read_config_dword(dev, vsec + 0x58, &val); 261 show_reg("Flash Status/Control Register", val); 262 pci_read_config_dword(dev, vsec + 0x58, &val); 263 show_reg("Flash Data Port", val); 264 265 #undef show_reg 266 } 267 268 static void dump_afu_descriptor(struct cxl_afu *afu) 269 { 270 u64 val; 271 272 #define show_reg(name, what) \ 273 dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what) 274 275 val = AFUD_READ_INFO(afu); 276 show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val)); 277 show_reg("num_of_processes", AFUD_NUM_PROCS(val)); 278 show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val)); 279 show_reg("req_prog_mode", val & 0xffffULL); 280 281 val = AFUD_READ(afu, 0x8); 282 show_reg("Reserved", val); 283 val = AFUD_READ(afu, 0x10); 284 show_reg("Reserved", val); 285 val = AFUD_READ(afu, 0x18); 286 show_reg("Reserved", val); 287 288 val = AFUD_READ_CR(afu); 289 show_reg("Reserved", (val >> (63-7)) & 0xff); 290 show_reg("AFU_CR_len", AFUD_CR_LEN(val)); 291 292 val = AFUD_READ_CR_OFF(afu); 293 show_reg("AFU_CR_offset", val); 294 295 val = AFUD_READ_PPPSA(afu); 296 show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff); 297 show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val)); 298 299 val = AFUD_READ_PPPSA_OFF(afu); 300 show_reg("PerProcessPSA_offset", val); 301 302 val = AFUD_READ_EB(afu); 303 show_reg("Reserved", (val >> (63-7)) & 0xff); 304 show_reg("AFU_EB_len", AFUD_EB_LEN(val)); 305 306 val = AFUD_READ_EB_OFF(afu); 307 show_reg("AFU_EB_offset", val); 308 309 #undef show_reg 310 } 311 312 static int init_implementation_adapter_regs(struct cxl *adapter, struct pci_dev *dev) 313 { 314 struct device_node *np; 315 const __be32 *prop; 316 u64 psl_dsnctl; 317 u64 chipid; 318 319 if (!(np = pnv_pci_to_phb_node(dev))) 320 return -ENODEV; 321 322 while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL))) 323 np = of_get_next_parent(np); 324 if (!np) 325 return -ENODEV; 326 chipid = be32_to_cpup(prop); 327 of_node_put(np); 328 329 /* Tell PSL where to route data to */ 330 psl_dsnctl = 0x02E8900002000000ULL | (chipid << (63-5)); 331 cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl); 332 cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL); 333 /* snoop write mask */ 334 cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL); 335 /* set fir_accum */ 336 cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, 0x0800000000000000ULL); 337 /* for debugging with trace arrays */ 338 cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL); 339 340 return 0; 341 } 342 343 static int init_implementation_afu_regs(struct cxl_afu *afu) 344 { 345 /* read/write masks for this slice */ 346 cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL); 347 /* APC read/write masks for this slice */ 348 cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL); 349 /* for debugging with trace arrays */ 350 cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL); 351 cxl_p1n_write(afu, CXL_PSL_RXCTL_A, 0xF000000000000000ULL); 352 353 return 0; 354 } 355 356 int cxl_setup_irq(struct cxl *adapter, unsigned int hwirq, 357 unsigned int virq) 358 { 359 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 360 361 return pnv_cxl_ioda_msi_setup(dev, hwirq, virq); 362 } 363 364 int cxl_alloc_one_irq(struct cxl *adapter) 365 { 366 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 367 368 return pnv_cxl_alloc_hwirqs(dev, 1); 369 } 370 371 void cxl_release_one_irq(struct cxl *adapter, int hwirq) 372 { 373 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 374 375 return pnv_cxl_release_hwirqs(dev, hwirq, 1); 376 } 377 378 int cxl_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num) 379 { 380 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 381 382 return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num); 383 } 384 385 void cxl_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter) 386 { 387 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 388 389 pnv_cxl_release_hwirq_ranges(irqs, dev); 390 } 391 392 static int setup_cxl_bars(struct pci_dev *dev) 393 { 394 /* Safety check in case we get backported to < 3.17 without M64 */ 395 if ((p1_base(dev) < 0x100000000ULL) || 396 (p2_base(dev) < 0x100000000ULL)) { 397 dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n"); 398 return -ENODEV; 399 } 400 401 /* 402 * BAR 4/5 has a special meaning for CXL and must be programmed with a 403 * special value corresponding to the CXL protocol address range. 404 * For POWER 8 that means bits 48:49 must be set to 10 405 */ 406 pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000); 407 pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000); 408 409 return 0; 410 } 411 412 /* pciex node: ibm,opal-m64-window = <0x3d058 0x0 0x3d058 0x0 0x8 0x0>; */ 413 static int switch_card_to_cxl(struct pci_dev *dev) 414 { 415 int vsec; 416 u8 val; 417 int rc; 418 419 dev_info(&dev->dev, "switch card to CXL\n"); 420 421 if (!(vsec = find_cxl_vsec(dev))) { 422 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n"); 423 return -ENODEV; 424 } 425 426 if ((rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val))) { 427 dev_err(&dev->dev, "failed to read current mode control: %i", rc); 428 return rc; 429 } 430 val &= ~CXL_VSEC_PROTOCOL_MASK; 431 val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE; 432 if ((rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val))) { 433 dev_err(&dev->dev, "failed to enable CXL protocol: %i", rc); 434 return rc; 435 } 436 /* 437 * The CAIA spec (v0.12 11.6 Bi-modal Device Support) states 438 * we must wait 100ms after this mode switch before touching 439 * PCIe config space. 440 */ 441 msleep(100); 442 443 return 0; 444 } 445 446 static int cxl_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev) 447 { 448 u64 p1n_base, p2n_base, afu_desc; 449 const u64 p1n_size = 0x100; 450 const u64 p2n_size = 0x1000; 451 452 p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size); 453 p2n_base = p2_base(dev) + (afu->slice * p2n_size); 454 afu->psn_phys = p2_base(dev) + (adapter->ps_off + (afu->slice * adapter->ps_size)); 455 afu_desc = p2_base(dev) + adapter->afu_desc_off + (afu->slice * adapter->afu_desc_size); 456 457 if (!(afu->p1n_mmio = ioremap(p1n_base, p1n_size))) 458 goto err; 459 if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size))) 460 goto err1; 461 if (afu_desc) { 462 if (!(afu->afu_desc_mmio = ioremap(afu_desc, adapter->afu_desc_size))) 463 goto err2; 464 } 465 466 return 0; 467 err2: 468 iounmap(afu->p2n_mmio); 469 err1: 470 iounmap(afu->p1n_mmio); 471 err: 472 dev_err(&afu->dev, "Error mapping AFU MMIO regions\n"); 473 return -ENOMEM; 474 } 475 476 static void cxl_unmap_slice_regs(struct cxl_afu *afu) 477 { 478 if (afu->p1n_mmio) 479 iounmap(afu->p2n_mmio); 480 if (afu->p1n_mmio) 481 iounmap(afu->p1n_mmio); 482 } 483 484 static void cxl_release_afu(struct device *dev) 485 { 486 struct cxl_afu *afu = to_cxl_afu(dev); 487 488 pr_devel("cxl_release_afu\n"); 489 490 kfree(afu); 491 } 492 493 static struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice) 494 { 495 struct cxl_afu *afu; 496 497 if (!(afu = kzalloc(sizeof(struct cxl_afu), GFP_KERNEL))) 498 return NULL; 499 500 afu->adapter = adapter; 501 afu->dev.parent = &adapter->dev; 502 afu->dev.release = cxl_release_afu; 503 afu->slice = slice; 504 idr_init(&afu->contexts_idr); 505 mutex_init(&afu->contexts_lock); 506 spin_lock_init(&afu->afu_cntl_lock); 507 mutex_init(&afu->spa_mutex); 508 509 afu->prefault_mode = CXL_PREFAULT_NONE; 510 afu->irqs_max = afu->adapter->user_irqs; 511 512 return afu; 513 } 514 515 /* Expects AFU struct to have recently been zeroed out */ 516 static int cxl_read_afu_descriptor(struct cxl_afu *afu) 517 { 518 u64 val; 519 520 val = AFUD_READ_INFO(afu); 521 afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val); 522 afu->max_procs_virtualised = AFUD_NUM_PROCS(val); 523 524 if (AFUD_AFU_DIRECTED(val)) 525 afu->modes_supported |= CXL_MODE_DIRECTED; 526 if (AFUD_DEDICATED_PROCESS(val)) 527 afu->modes_supported |= CXL_MODE_DEDICATED; 528 if (AFUD_TIME_SLICED(val)) 529 afu->modes_supported |= CXL_MODE_TIME_SLICED; 530 531 val = AFUD_READ_PPPSA(afu); 532 afu->pp_size = AFUD_PPPSA_LEN(val) * 4096; 533 afu->psa = AFUD_PPPSA_PSA(val); 534 if ((afu->pp_psa = AFUD_PPPSA_PP(val))) 535 afu->pp_offset = AFUD_READ_PPPSA_OFF(afu); 536 537 return 0; 538 } 539 540 static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu) 541 { 542 if (afu->psa && afu->adapter->ps_size < 543 (afu->pp_offset + afu->pp_size*afu->max_procs_virtualised)) { 544 dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n"); 545 return -ENODEV; 546 } 547 548 if (afu->pp_psa && (afu->pp_size < PAGE_SIZE)) 549 dev_warn(&afu->dev, "AFU uses < PAGE_SIZE per-process PSA!"); 550 551 return 0; 552 } 553 554 static int sanitise_afu_regs(struct cxl_afu *afu) 555 { 556 u64 reg; 557 558 /* 559 * Clear out any regs that contain either an IVTE or address or may be 560 * waiting on an acknowledgement to try to be a bit safer as we bring 561 * it online 562 */ 563 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An); 564 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) { 565 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#.16llx\n", reg); 566 if (cxl_afu_reset(afu)) 567 return -EIO; 568 if (cxl_afu_disable(afu)) 569 return -EIO; 570 if (cxl_psl_purge(afu)) 571 return -EIO; 572 } 573 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000); 574 cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000); 575 cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000); 576 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000); 577 cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000); 578 cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000); 579 cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000); 580 cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000); 581 cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000); 582 cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000); 583 cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000); 584 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An); 585 if (reg) { 586 dev_warn(&afu->dev, "AFU had pending DSISR: %#.16llx\n", reg); 587 if (reg & CXL_PSL_DSISR_TRANS) 588 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); 589 else 590 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); 591 } 592 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An); 593 if (reg) { 594 if (reg & ~0xffff) 595 dev_warn(&afu->dev, "AFU had pending SERR: %#.16llx\n", reg); 596 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff); 597 } 598 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); 599 if (reg) { 600 dev_warn(&afu->dev, "AFU had pending error status: %#.16llx\n", reg); 601 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg); 602 } 603 604 return 0; 605 } 606 607 static int cxl_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev) 608 { 609 struct cxl_afu *afu; 610 bool free = true; 611 int rc; 612 613 if (!(afu = cxl_alloc_afu(adapter, slice))) 614 return -ENOMEM; 615 616 if ((rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice))) 617 goto err1; 618 619 if ((rc = cxl_map_slice_regs(afu, adapter, dev))) 620 goto err1; 621 622 if ((rc = sanitise_afu_regs(afu))) 623 goto err2; 624 625 /* We need to reset the AFU before we can read the AFU descriptor */ 626 if ((rc = cxl_afu_reset(afu))) 627 goto err2; 628 629 if (cxl_verbose) 630 dump_afu_descriptor(afu); 631 632 if ((rc = cxl_read_afu_descriptor(afu))) 633 goto err2; 634 635 if ((rc = cxl_afu_descriptor_looks_ok(afu))) 636 goto err2; 637 638 if ((rc = init_implementation_afu_regs(afu))) 639 goto err2; 640 641 if ((rc = cxl_register_serr_irq(afu))) 642 goto err2; 643 644 if ((rc = cxl_register_psl_irq(afu))) 645 goto err3; 646 647 /* Don't care if this fails */ 648 cxl_debugfs_afu_add(afu); 649 650 /* 651 * After we call this function we must not free the afu directly, even 652 * if it returns an error! 653 */ 654 if ((rc = cxl_register_afu(afu))) 655 goto err_put1; 656 657 if ((rc = cxl_sysfs_afu_add(afu))) 658 goto err_put1; 659 660 661 if ((rc = cxl_afu_select_best_mode(afu))) 662 goto err_put2; 663 664 adapter->afu[afu->slice] = afu; 665 666 return 0; 667 668 err_put2: 669 cxl_sysfs_afu_remove(afu); 670 err_put1: 671 device_unregister(&afu->dev); 672 free = false; 673 cxl_debugfs_afu_remove(afu); 674 cxl_release_psl_irq(afu); 675 err3: 676 cxl_release_serr_irq(afu); 677 err2: 678 cxl_unmap_slice_regs(afu); 679 err1: 680 if (free) 681 kfree(afu); 682 return rc; 683 } 684 685 static void cxl_remove_afu(struct cxl_afu *afu) 686 { 687 pr_devel("cxl_remove_afu\n"); 688 689 if (!afu) 690 return; 691 692 cxl_sysfs_afu_remove(afu); 693 cxl_debugfs_afu_remove(afu); 694 695 spin_lock(&afu->adapter->afu_list_lock); 696 afu->adapter->afu[afu->slice] = NULL; 697 spin_unlock(&afu->adapter->afu_list_lock); 698 699 cxl_context_detach_all(afu); 700 cxl_afu_deactivate_mode(afu); 701 702 cxl_release_psl_irq(afu); 703 cxl_release_serr_irq(afu); 704 cxl_unmap_slice_regs(afu); 705 706 device_unregister(&afu->dev); 707 } 708 709 710 static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev) 711 { 712 if (pci_request_region(dev, 2, "priv 2 regs")) 713 goto err1; 714 if (pci_request_region(dev, 0, "priv 1 regs")) 715 goto err2; 716 717 pr_devel("cxl_map_adapter_regs: p1: %#.16llx %#llx, p2: %#.16llx %#llx", 718 p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev)); 719 720 if (!(adapter->p1_mmio = ioremap(p1_base(dev), p1_size(dev)))) 721 goto err3; 722 723 if (!(adapter->p2_mmio = ioremap(p2_base(dev), p2_size(dev)))) 724 goto err4; 725 726 return 0; 727 728 err4: 729 iounmap(adapter->p1_mmio); 730 adapter->p1_mmio = NULL; 731 err3: 732 pci_release_region(dev, 0); 733 err2: 734 pci_release_region(dev, 2); 735 err1: 736 return -ENOMEM; 737 } 738 739 static void cxl_unmap_adapter_regs(struct cxl *adapter) 740 { 741 if (adapter->p1_mmio) 742 iounmap(adapter->p1_mmio); 743 if (adapter->p2_mmio) 744 iounmap(adapter->p2_mmio); 745 } 746 747 static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev) 748 { 749 int vsec; 750 u32 afu_desc_off, afu_desc_size; 751 u32 ps_off, ps_size; 752 u16 vseclen; 753 u8 image_state; 754 755 if (!(vsec = find_cxl_vsec(dev))) { 756 dev_err(&adapter->dev, "ABORTING: CXL VSEC not found!\n"); 757 return -ENODEV; 758 } 759 760 CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen); 761 if (vseclen < CXL_VSEC_MIN_SIZE) { 762 pr_err("ABORTING: CXL VSEC too short\n"); 763 return -EINVAL; 764 } 765 766 CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status); 767 CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev); 768 CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major); 769 CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor); 770 CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image); 771 CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state); 772 adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED); 773 adapter->perst_loads_image = !!(image_state & CXL_VSEC_PERST_LOADS_IMAGE); 774 adapter->perst_select_user = !!(image_state & CXL_VSEC_PERST_SELECT_USER); 775 776 CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices); 777 CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off); 778 CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size); 779 CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off); 780 CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size); 781 782 /* Convert everything to bytes, because there is NO WAY I'd look at the 783 * code a month later and forget what units these are in ;-) */ 784 adapter->ps_off = ps_off * 64 * 1024; 785 adapter->ps_size = ps_size * 64 * 1024; 786 adapter->afu_desc_off = afu_desc_off * 64 * 1024; 787 adapter->afu_desc_size = afu_desc_size *64 * 1024; 788 789 /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */ 790 adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices; 791 792 return 0; 793 } 794 795 static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev) 796 { 797 if (adapter->vsec_status & CXL_STATUS_SECOND_PORT) 798 return -EBUSY; 799 800 if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) { 801 dev_err(&adapter->dev, "ABORTING: CXL requires unsupported features\n"); 802 return -EINVAL; 803 } 804 805 if (!adapter->slices) { 806 /* Once we support dynamic reprogramming we can use the card if 807 * it supports loadable AFUs */ 808 dev_err(&adapter->dev, "ABORTING: Device has no AFUs\n"); 809 return -EINVAL; 810 } 811 812 if (!adapter->afu_desc_off || !adapter->afu_desc_size) { 813 dev_err(&adapter->dev, "ABORTING: VSEC shows no AFU descriptors\n"); 814 return -EINVAL; 815 } 816 817 if (adapter->ps_size > p2_size(dev) - adapter->ps_off) { 818 dev_err(&adapter->dev, "ABORTING: Problem state size larger than " 819 "available in BAR2: 0x%llx > 0x%llx\n", 820 adapter->ps_size, p2_size(dev) - adapter->ps_off); 821 return -EINVAL; 822 } 823 824 return 0; 825 } 826 827 static void cxl_release_adapter(struct device *dev) 828 { 829 struct cxl *adapter = to_cxl_adapter(dev); 830 831 pr_devel("cxl_release_adapter\n"); 832 833 kfree(adapter); 834 } 835 836 static struct cxl *cxl_alloc_adapter(struct pci_dev *dev) 837 { 838 struct cxl *adapter; 839 840 if (!(adapter = kzalloc(sizeof(struct cxl), GFP_KERNEL))) 841 return NULL; 842 843 adapter->dev.parent = &dev->dev; 844 adapter->dev.release = cxl_release_adapter; 845 pci_set_drvdata(dev, adapter); 846 spin_lock_init(&adapter->afu_list_lock); 847 848 return adapter; 849 } 850 851 static int sanitise_adapter_regs(struct cxl *adapter) 852 { 853 cxl_p1_write(adapter, CXL_PSL_ErrIVTE, 0x0000000000000000); 854 return cxl_tlb_slb_invalidate(adapter); 855 } 856 857 static struct cxl *cxl_init_adapter(struct pci_dev *dev) 858 { 859 struct cxl *adapter; 860 bool free = true; 861 int rc; 862 863 864 if (!(adapter = cxl_alloc_adapter(dev))) 865 return ERR_PTR(-ENOMEM); 866 867 if ((rc = switch_card_to_cxl(dev))) 868 goto err1; 869 870 if ((rc = cxl_alloc_adapter_nr(adapter))) 871 goto err1; 872 873 if ((rc = dev_set_name(&adapter->dev, "card%i", adapter->adapter_num))) 874 goto err2; 875 876 if ((rc = cxl_read_vsec(adapter, dev))) 877 goto err2; 878 879 if ((rc = cxl_vsec_looks_ok(adapter, dev))) 880 goto err2; 881 882 if ((rc = cxl_map_adapter_regs(adapter, dev))) 883 goto err2; 884 885 if ((rc = sanitise_adapter_regs(adapter))) 886 goto err2; 887 888 if ((rc = init_implementation_adapter_regs(adapter, dev))) 889 goto err3; 890 891 if ((rc = pnv_phb_to_cxl(dev))) 892 goto err3; 893 894 if ((rc = cxl_register_psl_err_irq(adapter))) 895 goto err3; 896 897 /* Don't care if this one fails: */ 898 cxl_debugfs_adapter_add(adapter); 899 900 /* 901 * After we call this function we must not free the adapter directly, 902 * even if it returns an error! 903 */ 904 if ((rc = cxl_register_adapter(adapter))) 905 goto err_put1; 906 907 if ((rc = cxl_sysfs_adapter_add(adapter))) 908 goto err_put1; 909 910 return adapter; 911 912 err_put1: 913 device_unregister(&adapter->dev); 914 free = false; 915 cxl_debugfs_adapter_remove(adapter); 916 cxl_release_psl_err_irq(adapter); 917 err3: 918 cxl_unmap_adapter_regs(adapter); 919 err2: 920 cxl_remove_adapter_nr(adapter); 921 err1: 922 if (free) 923 kfree(adapter); 924 return ERR_PTR(rc); 925 } 926 927 static void cxl_remove_adapter(struct cxl *adapter) 928 { 929 struct pci_dev *pdev = to_pci_dev(adapter->dev.parent); 930 931 pr_devel("cxl_release_adapter\n"); 932 933 cxl_sysfs_adapter_remove(adapter); 934 cxl_debugfs_adapter_remove(adapter); 935 cxl_release_psl_err_irq(adapter); 936 cxl_unmap_adapter_regs(adapter); 937 cxl_remove_adapter_nr(adapter); 938 939 device_unregister(&adapter->dev); 940 941 pci_release_region(pdev, 0); 942 pci_release_region(pdev, 2); 943 pci_disable_device(pdev); 944 } 945 946 static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id) 947 { 948 struct cxl *adapter; 949 int slice; 950 int rc; 951 952 pci_dev_get(dev); 953 954 if (cxl_verbose) 955 dump_cxl_config_space(dev); 956 957 if ((rc = setup_cxl_bars(dev))) 958 return rc; 959 960 if ((rc = pci_enable_device(dev))) { 961 dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc); 962 return rc; 963 } 964 965 adapter = cxl_init_adapter(dev); 966 if (IS_ERR(adapter)) { 967 dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter)); 968 return PTR_ERR(adapter); 969 } 970 971 for (slice = 0; slice < adapter->slices; slice++) { 972 if ((rc = cxl_init_afu(adapter, slice, dev))) 973 dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc); 974 } 975 976 return 0; 977 } 978 979 static void cxl_remove(struct pci_dev *dev) 980 { 981 struct cxl *adapter = pci_get_drvdata(dev); 982 int afu; 983 984 dev_warn(&dev->dev, "pci remove\n"); 985 986 /* 987 * Lock to prevent someone grabbing a ref through the adapter list as 988 * we are removing it 989 */ 990 for (afu = 0; afu < adapter->slices; afu++) 991 cxl_remove_afu(adapter->afu[afu]); 992 cxl_remove_adapter(adapter); 993 } 994 995 struct pci_driver cxl_pci_driver = { 996 .name = "cxl-pci", 997 .id_table = cxl_pci_tbl, 998 .probe = cxl_probe, 999 .remove = cxl_remove, 1000 }; 1001