1 /* 2 * Copyright 2014 IBM Corp. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 */ 9 10 #include <linux/spinlock.h> 11 #include <linux/sched.h> 12 #include <linux/slab.h> 13 #include <linux/sched.h> 14 #include <linux/mutex.h> 15 #include <linux/mm.h> 16 #include <linux/uaccess.h> 17 #include <asm/synch.h> 18 #include <misc/cxl-base.h> 19 20 #include "cxl.h" 21 #include "trace.h" 22 23 static int afu_control(struct cxl_afu *afu, u64 command, 24 u64 result, u64 mask, bool enabled) 25 { 26 u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); 27 unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); 28 int rc = 0; 29 30 spin_lock(&afu->afu_cntl_lock); 31 pr_devel("AFU command starting: %llx\n", command); 32 33 trace_cxl_afu_ctrl(afu, command); 34 35 cxl_p2n_write(afu, CXL_AFU_Cntl_An, AFU_Cntl | command); 36 37 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); 38 while ((AFU_Cntl & mask) != result) { 39 if (time_after_eq(jiffies, timeout)) { 40 dev_warn(&afu->dev, "WARNING: AFU control timed out!\n"); 41 rc = -EBUSY; 42 goto out; 43 } 44 pr_devel_ratelimited("AFU control... (0x%.16llx)\n", 45 AFU_Cntl | command); 46 cpu_relax(); 47 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); 48 }; 49 pr_devel("AFU command complete: %llx\n", command); 50 afu->enabled = enabled; 51 out: 52 trace_cxl_afu_ctrl_done(afu, command, rc); 53 spin_unlock(&afu->afu_cntl_lock); 54 55 return rc; 56 } 57 58 static int afu_enable(struct cxl_afu *afu) 59 { 60 pr_devel("AFU enable request\n"); 61 62 return afu_control(afu, CXL_AFU_Cntl_An_E, 63 CXL_AFU_Cntl_An_ES_Enabled, 64 CXL_AFU_Cntl_An_ES_MASK, true); 65 } 66 67 int cxl_afu_disable(struct cxl_afu *afu) 68 { 69 pr_devel("AFU disable request\n"); 70 71 return afu_control(afu, 0, CXL_AFU_Cntl_An_ES_Disabled, 72 CXL_AFU_Cntl_An_ES_MASK, false); 73 } 74 75 /* This will disable as well as reset */ 76 int __cxl_afu_reset(struct cxl_afu *afu) 77 { 78 pr_devel("AFU reset request\n"); 79 80 return afu_control(afu, CXL_AFU_Cntl_An_RA, 81 CXL_AFU_Cntl_An_RS_Complete | CXL_AFU_Cntl_An_ES_Disabled, 82 CXL_AFU_Cntl_An_RS_MASK | CXL_AFU_Cntl_An_ES_MASK, 83 false); 84 } 85 86 int cxl_afu_check_and_enable(struct cxl_afu *afu) 87 { 88 if (afu->enabled) 89 return 0; 90 return afu_enable(afu); 91 } 92 93 int cxl_psl_purge(struct cxl_afu *afu) 94 { 95 u64 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); 96 u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); 97 u64 dsisr, dar; 98 u64 start, end; 99 unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); 100 int rc = 0; 101 102 trace_cxl_psl_ctrl(afu, CXL_PSL_SCNTL_An_Pc); 103 104 pr_devel("PSL purge request\n"); 105 106 if ((AFU_Cntl & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) { 107 WARN(1, "psl_purge request while AFU not disabled!\n"); 108 cxl_afu_disable(afu); 109 } 110 111 cxl_p1n_write(afu, CXL_PSL_SCNTL_An, 112 PSL_CNTL | CXL_PSL_SCNTL_An_Pc); 113 start = local_clock(); 114 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); 115 while ((PSL_CNTL & CXL_PSL_SCNTL_An_Ps_MASK) 116 == CXL_PSL_SCNTL_An_Ps_Pending) { 117 if (time_after_eq(jiffies, timeout)) { 118 dev_warn(&afu->dev, "WARNING: PSL Purge timed out!\n"); 119 rc = -EBUSY; 120 goto out; 121 } 122 dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); 123 pr_devel_ratelimited("PSL purging... PSL_CNTL: 0x%.16llx PSL_DSISR: 0x%.16llx\n", PSL_CNTL, dsisr); 124 if (dsisr & CXL_PSL_DSISR_TRANS) { 125 dar = cxl_p2n_read(afu, CXL_PSL_DAR_An); 126 dev_notice(&afu->dev, "PSL purge terminating pending translation, DSISR: 0x%.16llx, DAR: 0x%.16llx\n", dsisr, dar); 127 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); 128 } else if (dsisr) { 129 dev_notice(&afu->dev, "PSL purge acknowledging pending non-translation fault, DSISR: 0x%.16llx\n", dsisr); 130 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); 131 } else { 132 cpu_relax(); 133 } 134 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); 135 }; 136 end = local_clock(); 137 pr_devel("PSL purged in %lld ns\n", end - start); 138 139 cxl_p1n_write(afu, CXL_PSL_SCNTL_An, 140 PSL_CNTL & ~CXL_PSL_SCNTL_An_Pc); 141 out: 142 trace_cxl_psl_ctrl_done(afu, CXL_PSL_SCNTL_An_Pc, rc); 143 return rc; 144 } 145 146 static int spa_max_procs(int spa_size) 147 { 148 /* 149 * From the CAIA: 150 * end_of_SPA_area = SPA_Base + ((n+4) * 128) + (( ((n*8) + 127) >> 7) * 128) + 255 151 * Most of that junk is really just an overly-complicated way of saying 152 * the last 256 bytes are __aligned(128), so it's really: 153 * end_of_SPA_area = end_of_PSL_queue_area + __aligned(128) 255 154 * and 155 * end_of_PSL_queue_area = SPA_Base + ((n+4) * 128) + (n*8) - 1 156 * so 157 * sizeof(SPA) = ((n+4) * 128) + (n*8) + __aligned(128) 256 158 * Ignore the alignment (which is safe in this case as long as we are 159 * careful with our rounding) and solve for n: 160 */ 161 return ((spa_size / 8) - 96) / 17; 162 } 163 164 static int alloc_spa(struct cxl_afu *afu) 165 { 166 u64 spap; 167 168 /* Work out how many pages to allocate */ 169 afu->spa_order = 0; 170 do { 171 afu->spa_order++; 172 afu->spa_size = (1 << afu->spa_order) * PAGE_SIZE; 173 afu->spa_max_procs = spa_max_procs(afu->spa_size); 174 } while (afu->spa_max_procs < afu->num_procs); 175 176 WARN_ON(afu->spa_size > 0x100000); /* Max size supported by the hardware */ 177 178 if (!(afu->spa = (struct cxl_process_element *) 179 __get_free_pages(GFP_KERNEL | __GFP_ZERO, afu->spa_order))) { 180 pr_err("cxl_alloc_spa: Unable to allocate scheduled process area\n"); 181 return -ENOMEM; 182 } 183 pr_devel("spa pages: %i afu->spa_max_procs: %i afu->num_procs: %i\n", 184 1<<afu->spa_order, afu->spa_max_procs, afu->num_procs); 185 186 afu->sw_command_status = (__be64 *)((char *)afu->spa + 187 ((afu->spa_max_procs + 3) * 128)); 188 189 spap = virt_to_phys(afu->spa) & CXL_PSL_SPAP_Addr; 190 spap |= ((afu->spa_size >> (12 - CXL_PSL_SPAP_Size_Shift)) - 1) & CXL_PSL_SPAP_Size; 191 spap |= CXL_PSL_SPAP_V; 192 pr_devel("cxl: SPA allocated at 0x%p. Max processes: %i, sw_command_status: 0x%p CXL_PSL_SPAP_An=0x%016llx\n", afu->spa, afu->spa_max_procs, afu->sw_command_status, spap); 193 cxl_p1n_write(afu, CXL_PSL_SPAP_An, spap); 194 195 return 0; 196 } 197 198 static void release_spa(struct cxl_afu *afu) 199 { 200 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); 201 free_pages((unsigned long) afu->spa, afu->spa_order); 202 } 203 204 int cxl_tlb_slb_invalidate(struct cxl *adapter) 205 { 206 unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); 207 208 pr_devel("CXL adapter wide TLBIA & SLBIA\n"); 209 210 cxl_p1_write(adapter, CXL_PSL_AFUSEL, CXL_PSL_AFUSEL_A); 211 212 cxl_p1_write(adapter, CXL_PSL_TLBIA, CXL_TLB_SLB_IQ_ALL); 213 while (cxl_p1_read(adapter, CXL_PSL_TLBIA) & CXL_TLB_SLB_P) { 214 if (time_after_eq(jiffies, timeout)) { 215 dev_warn(&adapter->dev, "WARNING: CXL adapter wide TLBIA timed out!\n"); 216 return -EBUSY; 217 } 218 cpu_relax(); 219 } 220 221 cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_ALL); 222 while (cxl_p1_read(adapter, CXL_PSL_SLBIA) & CXL_TLB_SLB_P) { 223 if (time_after_eq(jiffies, timeout)) { 224 dev_warn(&adapter->dev, "WARNING: CXL adapter wide SLBIA timed out!\n"); 225 return -EBUSY; 226 } 227 cpu_relax(); 228 } 229 return 0; 230 } 231 232 int cxl_afu_slbia(struct cxl_afu *afu) 233 { 234 unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); 235 236 pr_devel("cxl_afu_slbia issuing SLBIA command\n"); 237 cxl_p2n_write(afu, CXL_SLBIA_An, CXL_TLB_SLB_IQ_ALL); 238 while (cxl_p2n_read(afu, CXL_SLBIA_An) & CXL_TLB_SLB_P) { 239 if (time_after_eq(jiffies, timeout)) { 240 dev_warn(&afu->dev, "WARNING: CXL AFU SLBIA timed out!\n"); 241 return -EBUSY; 242 } 243 cpu_relax(); 244 } 245 return 0; 246 } 247 248 static int cxl_write_sstp(struct cxl_afu *afu, u64 sstp0, u64 sstp1) 249 { 250 int rc; 251 252 /* 1. Disable SSTP by writing 0 to SSTP1[V] */ 253 cxl_p2n_write(afu, CXL_SSTP1_An, 0); 254 255 /* 2. Invalidate all SLB entries */ 256 if ((rc = cxl_afu_slbia(afu))) 257 return rc; 258 259 /* 3. Set SSTP0_An */ 260 cxl_p2n_write(afu, CXL_SSTP0_An, sstp0); 261 262 /* 4. Set SSTP1_An */ 263 cxl_p2n_write(afu, CXL_SSTP1_An, sstp1); 264 265 return 0; 266 } 267 268 /* Using per slice version may improve performance here. (ie. SLBIA_An) */ 269 static void slb_invalid(struct cxl_context *ctx) 270 { 271 struct cxl *adapter = ctx->afu->adapter; 272 u64 slbia; 273 274 WARN_ON(!mutex_is_locked(&ctx->afu->spa_mutex)); 275 276 cxl_p1_write(adapter, CXL_PSL_LBISEL, 277 ((u64)be32_to_cpu(ctx->elem->common.pid) << 32) | 278 be32_to_cpu(ctx->elem->lpid)); 279 cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_LPIDPID); 280 281 while (1) { 282 slbia = cxl_p1_read(adapter, CXL_PSL_SLBIA); 283 if (!(slbia & CXL_TLB_SLB_P)) 284 break; 285 cpu_relax(); 286 } 287 } 288 289 static int do_process_element_cmd(struct cxl_context *ctx, 290 u64 cmd, u64 pe_state) 291 { 292 u64 state; 293 unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); 294 int rc = 0; 295 296 trace_cxl_llcmd(ctx, cmd); 297 298 WARN_ON(!ctx->afu->enabled); 299 300 ctx->elem->software_state = cpu_to_be32(pe_state); 301 smp_wmb(); 302 *(ctx->afu->sw_command_status) = cpu_to_be64(cmd | 0 | ctx->pe); 303 smp_mb(); 304 cxl_p1n_write(ctx->afu, CXL_PSL_LLCMD_An, cmd | ctx->pe); 305 while (1) { 306 if (time_after_eq(jiffies, timeout)) { 307 dev_warn(&ctx->afu->dev, "WARNING: Process Element Command timed out!\n"); 308 rc = -EBUSY; 309 goto out; 310 } 311 state = be64_to_cpup(ctx->afu->sw_command_status); 312 if (state == ~0ULL) { 313 pr_err("cxl: Error adding process element to AFU\n"); 314 rc = -1; 315 goto out; 316 } 317 if ((state & (CXL_SPA_SW_CMD_MASK | CXL_SPA_SW_STATE_MASK | CXL_SPA_SW_LINK_MASK)) == 318 (cmd | (cmd >> 16) | ctx->pe)) 319 break; 320 /* 321 * The command won't finish in the PSL if there are 322 * outstanding DSIs. Hence we need to yield here in 323 * case there are outstanding DSIs that we need to 324 * service. Tuning possiblity: we could wait for a 325 * while before sched 326 */ 327 schedule(); 328 329 } 330 out: 331 trace_cxl_llcmd_done(ctx, cmd, rc); 332 return rc; 333 } 334 335 static int add_process_element(struct cxl_context *ctx) 336 { 337 int rc = 0; 338 339 mutex_lock(&ctx->afu->spa_mutex); 340 pr_devel("%s Adding pe: %i started\n", __func__, ctx->pe); 341 if (!(rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_ADD, CXL_PE_SOFTWARE_STATE_V))) 342 ctx->pe_inserted = true; 343 pr_devel("%s Adding pe: %i finished\n", __func__, ctx->pe); 344 mutex_unlock(&ctx->afu->spa_mutex); 345 return rc; 346 } 347 348 static int terminate_process_element(struct cxl_context *ctx) 349 { 350 int rc = 0; 351 352 /* fast path terminate if it's already invalid */ 353 if (!(ctx->elem->software_state & cpu_to_be32(CXL_PE_SOFTWARE_STATE_V))) 354 return rc; 355 356 mutex_lock(&ctx->afu->spa_mutex); 357 pr_devel("%s Terminate pe: %i started\n", __func__, ctx->pe); 358 rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_TERMINATE, 359 CXL_PE_SOFTWARE_STATE_V | CXL_PE_SOFTWARE_STATE_T); 360 ctx->elem->software_state = 0; /* Remove Valid bit */ 361 pr_devel("%s Terminate pe: %i finished\n", __func__, ctx->pe); 362 mutex_unlock(&ctx->afu->spa_mutex); 363 return rc; 364 } 365 366 static int remove_process_element(struct cxl_context *ctx) 367 { 368 int rc = 0; 369 370 mutex_lock(&ctx->afu->spa_mutex); 371 pr_devel("%s Remove pe: %i started\n", __func__, ctx->pe); 372 if (!(rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_REMOVE, 0))) 373 ctx->pe_inserted = false; 374 slb_invalid(ctx); 375 pr_devel("%s Remove pe: %i finished\n", __func__, ctx->pe); 376 mutex_unlock(&ctx->afu->spa_mutex); 377 378 return rc; 379 } 380 381 382 void cxl_assign_psn_space(struct cxl_context *ctx) 383 { 384 if (!ctx->afu->pp_size || ctx->master) { 385 ctx->psn_phys = ctx->afu->psn_phys; 386 ctx->psn_size = ctx->afu->adapter->ps_size; 387 } else { 388 ctx->psn_phys = ctx->afu->psn_phys + 389 (ctx->afu->pp_offset + ctx->afu->pp_size * ctx->pe); 390 ctx->psn_size = ctx->afu->pp_size; 391 } 392 } 393 394 static int activate_afu_directed(struct cxl_afu *afu) 395 { 396 int rc; 397 398 dev_info(&afu->dev, "Activating AFU directed mode\n"); 399 400 if (alloc_spa(afu)) 401 return -ENOMEM; 402 403 cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_AFU); 404 cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL); 405 cxl_p1n_write(afu, CXL_PSL_ID_An, CXL_PSL_ID_An_F | CXL_PSL_ID_An_L); 406 407 afu->current_mode = CXL_MODE_DIRECTED; 408 afu->num_procs = afu->max_procs_virtualised; 409 410 if ((rc = cxl_chardev_m_afu_add(afu))) 411 return rc; 412 413 if ((rc = cxl_sysfs_afu_m_add(afu))) 414 goto err; 415 416 if ((rc = cxl_chardev_s_afu_add(afu))) 417 goto err1; 418 419 return 0; 420 err1: 421 cxl_sysfs_afu_m_remove(afu); 422 err: 423 cxl_chardev_afu_remove(afu); 424 return rc; 425 } 426 427 #ifdef CONFIG_CPU_LITTLE_ENDIAN 428 #define set_endian(sr) ((sr) |= CXL_PSL_SR_An_LE) 429 #else 430 #define set_endian(sr) ((sr) &= ~(CXL_PSL_SR_An_LE)) 431 #endif 432 433 static u64 calculate_sr(struct cxl_context *ctx) 434 { 435 u64 sr = 0; 436 437 if (ctx->master) 438 sr |= CXL_PSL_SR_An_MP; 439 if (mfspr(SPRN_LPCR) & LPCR_TC) 440 sr |= CXL_PSL_SR_An_TC; 441 if (ctx->kernel) { 442 sr |= CXL_PSL_SR_An_R | (mfmsr() & MSR_SF); 443 sr |= CXL_PSL_SR_An_HV; 444 } else { 445 sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R; 446 set_endian(sr); 447 sr &= ~(CXL_PSL_SR_An_HV); 448 if (!test_tsk_thread_flag(current, TIF_32BIT)) 449 sr |= CXL_PSL_SR_An_SF; 450 } 451 return sr; 452 } 453 454 static int attach_afu_directed(struct cxl_context *ctx, u64 wed, u64 amr) 455 { 456 u32 pid; 457 int r, result; 458 459 cxl_assign_psn_space(ctx); 460 461 ctx->elem->ctxtime = 0; /* disable */ 462 ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID)); 463 ctx->elem->haurp = 0; /* disable */ 464 ctx->elem->sdr = cpu_to_be64(mfspr(SPRN_SDR1)); 465 466 pid = current->pid; 467 if (ctx->kernel) 468 pid = 0; 469 ctx->elem->common.tid = 0; 470 ctx->elem->common.pid = cpu_to_be32(pid); 471 472 ctx->elem->sr = cpu_to_be64(calculate_sr(ctx)); 473 474 ctx->elem->common.csrp = 0; /* disable */ 475 ctx->elem->common.aurp0 = 0; /* disable */ 476 ctx->elem->common.aurp1 = 0; /* disable */ 477 478 cxl_prefault(ctx, wed); 479 480 ctx->elem->common.sstp0 = cpu_to_be64(ctx->sstp0); 481 ctx->elem->common.sstp1 = cpu_to_be64(ctx->sstp1); 482 483 for (r = 0; r < CXL_IRQ_RANGES; r++) { 484 ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]); 485 ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]); 486 } 487 488 ctx->elem->common.amr = cpu_to_be64(amr); 489 ctx->elem->common.wed = cpu_to_be64(wed); 490 491 /* first guy needs to enable */ 492 if ((result = cxl_afu_check_and_enable(ctx->afu))) 493 return result; 494 495 add_process_element(ctx); 496 497 return 0; 498 } 499 500 static int deactivate_afu_directed(struct cxl_afu *afu) 501 { 502 dev_info(&afu->dev, "Deactivating AFU directed mode\n"); 503 504 afu->current_mode = 0; 505 afu->num_procs = 0; 506 507 cxl_sysfs_afu_m_remove(afu); 508 cxl_chardev_afu_remove(afu); 509 510 __cxl_afu_reset(afu); 511 cxl_afu_disable(afu); 512 cxl_psl_purge(afu); 513 514 release_spa(afu); 515 516 return 0; 517 } 518 519 static int activate_dedicated_process(struct cxl_afu *afu) 520 { 521 dev_info(&afu->dev, "Activating dedicated process mode\n"); 522 523 cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_Process); 524 525 cxl_p1n_write(afu, CXL_PSL_CtxTime_An, 0); /* disable */ 526 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); /* disable */ 527 cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL); 528 cxl_p1n_write(afu, CXL_PSL_LPID_An, mfspr(SPRN_LPID)); 529 cxl_p1n_write(afu, CXL_HAURP_An, 0); /* disable */ 530 cxl_p1n_write(afu, CXL_PSL_SDR_An, mfspr(SPRN_SDR1)); 531 532 cxl_p2n_write(afu, CXL_CSRP_An, 0); /* disable */ 533 cxl_p2n_write(afu, CXL_AURP0_An, 0); /* disable */ 534 cxl_p2n_write(afu, CXL_AURP1_An, 0); /* disable */ 535 536 afu->current_mode = CXL_MODE_DEDICATED; 537 afu->num_procs = 1; 538 539 return cxl_chardev_d_afu_add(afu); 540 } 541 542 static int attach_dedicated(struct cxl_context *ctx, u64 wed, u64 amr) 543 { 544 struct cxl_afu *afu = ctx->afu; 545 u64 pid; 546 int rc; 547 548 pid = (u64)current->pid << 32; 549 if (ctx->kernel) 550 pid = 0; 551 cxl_p2n_write(afu, CXL_PSL_PID_TID_An, pid); 552 553 cxl_p1n_write(afu, CXL_PSL_SR_An, calculate_sr(ctx)); 554 555 if ((rc = cxl_write_sstp(afu, ctx->sstp0, ctx->sstp1))) 556 return rc; 557 558 cxl_prefault(ctx, wed); 559 560 cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 561 (((u64)ctx->irqs.offset[0] & 0xffff) << 48) | 562 (((u64)ctx->irqs.offset[1] & 0xffff) << 32) | 563 (((u64)ctx->irqs.offset[2] & 0xffff) << 16) | 564 ((u64)ctx->irqs.offset[3] & 0xffff)); 565 cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, (u64) 566 (((u64)ctx->irqs.range[0] & 0xffff) << 48) | 567 (((u64)ctx->irqs.range[1] & 0xffff) << 32) | 568 (((u64)ctx->irqs.range[2] & 0xffff) << 16) | 569 ((u64)ctx->irqs.range[3] & 0xffff)); 570 571 cxl_p2n_write(afu, CXL_PSL_AMR_An, amr); 572 573 /* master only context for dedicated */ 574 cxl_assign_psn_space(ctx); 575 576 if ((rc = __cxl_afu_reset(afu))) 577 return rc; 578 579 cxl_p2n_write(afu, CXL_PSL_WED_An, wed); 580 581 return afu_enable(afu); 582 } 583 584 static int deactivate_dedicated_process(struct cxl_afu *afu) 585 { 586 dev_info(&afu->dev, "Deactivating dedicated process mode\n"); 587 588 afu->current_mode = 0; 589 afu->num_procs = 0; 590 591 cxl_chardev_afu_remove(afu); 592 593 return 0; 594 } 595 596 int _cxl_afu_deactivate_mode(struct cxl_afu *afu, int mode) 597 { 598 if (mode == CXL_MODE_DIRECTED) 599 return deactivate_afu_directed(afu); 600 if (mode == CXL_MODE_DEDICATED) 601 return deactivate_dedicated_process(afu); 602 return 0; 603 } 604 605 int cxl_afu_deactivate_mode(struct cxl_afu *afu) 606 { 607 return _cxl_afu_deactivate_mode(afu, afu->current_mode); 608 } 609 610 int cxl_afu_activate_mode(struct cxl_afu *afu, int mode) 611 { 612 if (!mode) 613 return 0; 614 if (!(mode & afu->modes_supported)) 615 return -EINVAL; 616 617 if (mode == CXL_MODE_DIRECTED) 618 return activate_afu_directed(afu); 619 if (mode == CXL_MODE_DEDICATED) 620 return activate_dedicated_process(afu); 621 622 return -EINVAL; 623 } 624 625 int cxl_attach_process(struct cxl_context *ctx, bool kernel, u64 wed, u64 amr) 626 { 627 ctx->kernel = kernel; 628 if (ctx->afu->current_mode == CXL_MODE_DIRECTED) 629 return attach_afu_directed(ctx, wed, amr); 630 631 if (ctx->afu->current_mode == CXL_MODE_DEDICATED) 632 return attach_dedicated(ctx, wed, amr); 633 634 return -EINVAL; 635 } 636 637 static inline int detach_process_native_dedicated(struct cxl_context *ctx) 638 { 639 __cxl_afu_reset(ctx->afu); 640 cxl_afu_disable(ctx->afu); 641 cxl_psl_purge(ctx->afu); 642 return 0; 643 } 644 645 static inline int detach_process_native_afu_directed(struct cxl_context *ctx) 646 { 647 if (!ctx->pe_inserted) 648 return 0; 649 if (terminate_process_element(ctx)) 650 return -1; 651 if (remove_process_element(ctx)) 652 return -1; 653 654 return 0; 655 } 656 657 int cxl_detach_process(struct cxl_context *ctx) 658 { 659 trace_cxl_detach(ctx); 660 661 if (ctx->afu->current_mode == CXL_MODE_DEDICATED) 662 return detach_process_native_dedicated(ctx); 663 664 return detach_process_native_afu_directed(ctx); 665 } 666 667 int cxl_get_irq(struct cxl_afu *afu, struct cxl_irq_info *info) 668 { 669 u64 pidtid; 670 671 info->dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); 672 info->dar = cxl_p2n_read(afu, CXL_PSL_DAR_An); 673 info->dsr = cxl_p2n_read(afu, CXL_PSL_DSR_An); 674 pidtid = cxl_p2n_read(afu, CXL_PSL_PID_TID_An); 675 info->pid = pidtid >> 32; 676 info->tid = pidtid & 0xffffffff; 677 info->afu_err = cxl_p2n_read(afu, CXL_AFU_ERR_An); 678 info->errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); 679 680 return 0; 681 } 682 683 static void recover_psl_err(struct cxl_afu *afu, u64 errstat) 684 { 685 u64 dsisr; 686 687 pr_devel("RECOVERING FROM PSL ERROR... (0x%.16llx)\n", errstat); 688 689 /* Clear PSL_DSISR[PE] */ 690 dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); 691 cxl_p2n_write(afu, CXL_PSL_DSISR_An, dsisr & ~CXL_PSL_DSISR_An_PE); 692 693 /* Write 1s to clear error status bits */ 694 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, errstat); 695 } 696 697 int cxl_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask) 698 { 699 trace_cxl_psl_irq_ack(ctx, tfc); 700 if (tfc) 701 cxl_p2n_write(ctx->afu, CXL_PSL_TFC_An, tfc); 702 if (psl_reset_mask) 703 recover_psl_err(ctx->afu, psl_reset_mask); 704 705 return 0; 706 } 707 708 int cxl_check_error(struct cxl_afu *afu) 709 { 710 return (cxl_p1n_read(afu, CXL_PSL_SCNTL_An) == ~0ULL); 711 } 712