1f204e0b8SIan Munsie /* 2f204e0b8SIan Munsie * Copyright 2014 IBM Corp. 3f204e0b8SIan Munsie * 4f204e0b8SIan Munsie * This program is free software; you can redistribute it and/or 5f204e0b8SIan Munsie * modify it under the terms of the GNU General Public License 6f204e0b8SIan Munsie * as published by the Free Software Foundation; either version 7f204e0b8SIan Munsie * 2 of the License, or (at your option) any later version. 8f204e0b8SIan Munsie */ 9f204e0b8SIan Munsie 10f204e0b8SIan Munsie #include <linux/spinlock.h> 11f204e0b8SIan Munsie #include <linux/sched.h> 12f204e0b8SIan Munsie #include <linux/slab.h> 13f204e0b8SIan Munsie #include <linux/sched.h> 14f204e0b8SIan Munsie #include <linux/mutex.h> 15f204e0b8SIan Munsie #include <linux/mm.h> 16f204e0b8SIan Munsie #include <linux/uaccess.h> 172bc79ffcSMichael Neuling #include <linux/delay.h> 18f204e0b8SIan Munsie #include <asm/synch.h> 19ec249dd8SMichael Neuling #include <misc/cxl-base.h> 20f204e0b8SIan Munsie 21f204e0b8SIan Munsie #include "cxl.h" 229bcf28cdSIan Munsie #include "trace.h" 23f204e0b8SIan Munsie 245e7823c9SIan Munsie static int afu_control(struct cxl_afu *afu, u64 command, u64 clear, 25f204e0b8SIan Munsie u64 result, u64 mask, bool enabled) 26f204e0b8SIan Munsie { 275e7823c9SIan Munsie u64 AFU_Cntl; 28f204e0b8SIan Munsie unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); 299bcf28cdSIan Munsie int rc = 0; 30f204e0b8SIan Munsie 31f204e0b8SIan Munsie spin_lock(&afu->afu_cntl_lock); 32f204e0b8SIan Munsie pr_devel("AFU command starting: %llx\n", command); 33f204e0b8SIan Munsie 349bcf28cdSIan Munsie trace_cxl_afu_ctrl(afu, command); 359bcf28cdSIan Munsie 365e7823c9SIan Munsie AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); 375e7823c9SIan Munsie cxl_p2n_write(afu, CXL_AFU_Cntl_An, (AFU_Cntl & ~clear) | command); 38f204e0b8SIan Munsie 39f204e0b8SIan Munsie AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); 40f204e0b8SIan Munsie while ((AFU_Cntl & mask) != result) { 41f204e0b8SIan Munsie if (time_after_eq(jiffies, timeout)) { 42f204e0b8SIan Munsie dev_warn(&afu->dev, "WARNING: AFU control timed out!\n"); 439bcf28cdSIan Munsie rc = -EBUSY; 449bcf28cdSIan Munsie goto out; 45f204e0b8SIan Munsie } 460b3f9c75SDaniel Axtens 470d400f77SChristophe Lombard if (!cxl_ops->link_ok(afu->adapter, afu)) { 480b3f9c75SDaniel Axtens afu->enabled = enabled; 490b3f9c75SDaniel Axtens rc = -EIO; 500b3f9c75SDaniel Axtens goto out; 510b3f9c75SDaniel Axtens } 520b3f9c75SDaniel Axtens 53de369538SRasmus Villemoes pr_devel_ratelimited("AFU control... (0x%016llx)\n", 54f204e0b8SIan Munsie AFU_Cntl | command); 55f204e0b8SIan Munsie cpu_relax(); 56f204e0b8SIan Munsie AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); 573382a622SAndrew Donnellan } 582a4f667aSIan Munsie 592a4f667aSIan Munsie if (AFU_Cntl & CXL_AFU_Cntl_An_RA) { 602a4f667aSIan Munsie /* 612a4f667aSIan Munsie * Workaround for a bug in the XSL used in the Mellanox CX4 622a4f667aSIan Munsie * that fails to clear the RA bit after an AFU reset, 632a4f667aSIan Munsie * preventing subsequent AFU resets from working. 642a4f667aSIan Munsie */ 652a4f667aSIan Munsie cxl_p2n_write(afu, CXL_AFU_Cntl_An, AFU_Cntl & ~CXL_AFU_Cntl_An_RA); 662a4f667aSIan Munsie } 672a4f667aSIan Munsie 68f204e0b8SIan Munsie pr_devel("AFU command complete: %llx\n", command); 69f204e0b8SIan Munsie afu->enabled = enabled; 709bcf28cdSIan Munsie out: 719bcf28cdSIan Munsie trace_cxl_afu_ctrl_done(afu, command, rc); 72f204e0b8SIan Munsie spin_unlock(&afu->afu_cntl_lock); 73f204e0b8SIan Munsie 749bcf28cdSIan Munsie return rc; 75f204e0b8SIan Munsie } 76f204e0b8SIan Munsie 77f204e0b8SIan Munsie static int afu_enable(struct cxl_afu *afu) 78f204e0b8SIan Munsie { 79f204e0b8SIan Munsie pr_devel("AFU enable request\n"); 80f204e0b8SIan Munsie 815e7823c9SIan Munsie return afu_control(afu, CXL_AFU_Cntl_An_E, 0, 82f204e0b8SIan Munsie CXL_AFU_Cntl_An_ES_Enabled, 83f204e0b8SIan Munsie CXL_AFU_Cntl_An_ES_MASK, true); 84f204e0b8SIan Munsie } 85f204e0b8SIan Munsie 86f204e0b8SIan Munsie int cxl_afu_disable(struct cxl_afu *afu) 87f204e0b8SIan Munsie { 88f204e0b8SIan Munsie pr_devel("AFU disable request\n"); 89f204e0b8SIan Munsie 905e7823c9SIan Munsie return afu_control(afu, 0, CXL_AFU_Cntl_An_E, 915e7823c9SIan Munsie CXL_AFU_Cntl_An_ES_Disabled, 92f204e0b8SIan Munsie CXL_AFU_Cntl_An_ES_MASK, false); 93f204e0b8SIan Munsie } 94f204e0b8SIan Munsie 95f204e0b8SIan Munsie /* This will disable as well as reset */ 962b04cf31SFrederic Barrat static int native_afu_reset(struct cxl_afu *afu) 97f204e0b8SIan Munsie { 98f204e0b8SIan Munsie pr_devel("AFU reset request\n"); 99f204e0b8SIan Munsie 1005e7823c9SIan Munsie return afu_control(afu, CXL_AFU_Cntl_An_RA, 0, 101f204e0b8SIan Munsie CXL_AFU_Cntl_An_RS_Complete | CXL_AFU_Cntl_An_ES_Disabled, 102f204e0b8SIan Munsie CXL_AFU_Cntl_An_RS_MASK | CXL_AFU_Cntl_An_ES_MASK, 103f204e0b8SIan Munsie false); 104f204e0b8SIan Munsie } 105f204e0b8SIan Munsie 1062b04cf31SFrederic Barrat static int native_afu_check_and_enable(struct cxl_afu *afu) 107f204e0b8SIan Munsie { 1080d400f77SChristophe Lombard if (!cxl_ops->link_ok(afu->adapter, afu)) { 1090b3f9c75SDaniel Axtens WARN(1, "Refusing to enable afu while link down!\n"); 1100b3f9c75SDaniel Axtens return -EIO; 1110b3f9c75SDaniel Axtens } 112f204e0b8SIan Munsie if (afu->enabled) 113f204e0b8SIan Munsie return 0; 114f204e0b8SIan Munsie return afu_enable(afu); 115f204e0b8SIan Munsie } 116f204e0b8SIan Munsie 117f204e0b8SIan Munsie int cxl_psl_purge(struct cxl_afu *afu) 118f204e0b8SIan Munsie { 119f204e0b8SIan Munsie u64 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); 120f204e0b8SIan Munsie u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); 121f204e0b8SIan Munsie u64 dsisr, dar; 122f204e0b8SIan Munsie u64 start, end; 123f204e0b8SIan Munsie unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); 1249bcf28cdSIan Munsie int rc = 0; 1259bcf28cdSIan Munsie 1269bcf28cdSIan Munsie trace_cxl_psl_ctrl(afu, CXL_PSL_SCNTL_An_Pc); 127f204e0b8SIan Munsie 128f204e0b8SIan Munsie pr_devel("PSL purge request\n"); 129f204e0b8SIan Munsie 1300d400f77SChristophe Lombard if (!cxl_ops->link_ok(afu->adapter, afu)) { 1310b3f9c75SDaniel Axtens dev_warn(&afu->dev, "PSL Purge called with link down, ignoring\n"); 1320b3f9c75SDaniel Axtens rc = -EIO; 1330b3f9c75SDaniel Axtens goto out; 1340b3f9c75SDaniel Axtens } 1350b3f9c75SDaniel Axtens 136f204e0b8SIan Munsie if ((AFU_Cntl & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) { 137f204e0b8SIan Munsie WARN(1, "psl_purge request while AFU not disabled!\n"); 138f204e0b8SIan Munsie cxl_afu_disable(afu); 139f204e0b8SIan Munsie } 140f204e0b8SIan Munsie 141f204e0b8SIan Munsie cxl_p1n_write(afu, CXL_PSL_SCNTL_An, 142f204e0b8SIan Munsie PSL_CNTL | CXL_PSL_SCNTL_An_Pc); 143f204e0b8SIan Munsie start = local_clock(); 144f204e0b8SIan Munsie PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); 145f204e0b8SIan Munsie while ((PSL_CNTL & CXL_PSL_SCNTL_An_Ps_MASK) 146f204e0b8SIan Munsie == CXL_PSL_SCNTL_An_Ps_Pending) { 147f204e0b8SIan Munsie if (time_after_eq(jiffies, timeout)) { 148f204e0b8SIan Munsie dev_warn(&afu->dev, "WARNING: PSL Purge timed out!\n"); 1499bcf28cdSIan Munsie rc = -EBUSY; 1509bcf28cdSIan Munsie goto out; 151f204e0b8SIan Munsie } 1520d400f77SChristophe Lombard if (!cxl_ops->link_ok(afu->adapter, afu)) { 1530b3f9c75SDaniel Axtens rc = -EIO; 1540b3f9c75SDaniel Axtens goto out; 1550b3f9c75SDaniel Axtens } 1560b3f9c75SDaniel Axtens 157f204e0b8SIan Munsie dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); 158de369538SRasmus Villemoes pr_devel_ratelimited("PSL purging... PSL_CNTL: 0x%016llx PSL_DSISR: 0x%016llx\n", PSL_CNTL, dsisr); 159f204e0b8SIan Munsie if (dsisr & CXL_PSL_DSISR_TRANS) { 160f204e0b8SIan Munsie dar = cxl_p2n_read(afu, CXL_PSL_DAR_An); 161de369538SRasmus Villemoes dev_notice(&afu->dev, "PSL purge terminating pending translation, DSISR: 0x%016llx, DAR: 0x%016llx\n", dsisr, dar); 162f204e0b8SIan Munsie cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); 163f204e0b8SIan Munsie } else if (dsisr) { 164de369538SRasmus Villemoes dev_notice(&afu->dev, "PSL purge acknowledging pending non-translation fault, DSISR: 0x%016llx\n", dsisr); 165f204e0b8SIan Munsie cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); 166f204e0b8SIan Munsie } else { 167f204e0b8SIan Munsie cpu_relax(); 168f204e0b8SIan Munsie } 169f204e0b8SIan Munsie PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); 1703382a622SAndrew Donnellan } 171f204e0b8SIan Munsie end = local_clock(); 172f204e0b8SIan Munsie pr_devel("PSL purged in %lld ns\n", end - start); 173f204e0b8SIan Munsie 174f204e0b8SIan Munsie cxl_p1n_write(afu, CXL_PSL_SCNTL_An, 175f204e0b8SIan Munsie PSL_CNTL & ~CXL_PSL_SCNTL_An_Pc); 1769bcf28cdSIan Munsie out: 1779bcf28cdSIan Munsie trace_cxl_psl_ctrl_done(afu, CXL_PSL_SCNTL_An_Pc, rc); 1789bcf28cdSIan Munsie return rc; 179f204e0b8SIan Munsie } 180f204e0b8SIan Munsie 181f204e0b8SIan Munsie static int spa_max_procs(int spa_size) 182f204e0b8SIan Munsie { 183f204e0b8SIan Munsie /* 184f204e0b8SIan Munsie * From the CAIA: 185f204e0b8SIan Munsie * end_of_SPA_area = SPA_Base + ((n+4) * 128) + (( ((n*8) + 127) >> 7) * 128) + 255 186f204e0b8SIan Munsie * Most of that junk is really just an overly-complicated way of saying 187f204e0b8SIan Munsie * the last 256 bytes are __aligned(128), so it's really: 188f204e0b8SIan Munsie * end_of_SPA_area = end_of_PSL_queue_area + __aligned(128) 255 189f204e0b8SIan Munsie * and 190f204e0b8SIan Munsie * end_of_PSL_queue_area = SPA_Base + ((n+4) * 128) + (n*8) - 1 191f204e0b8SIan Munsie * so 192f204e0b8SIan Munsie * sizeof(SPA) = ((n+4) * 128) + (n*8) + __aligned(128) 256 193f204e0b8SIan Munsie * Ignore the alignment (which is safe in this case as long as we are 194f204e0b8SIan Munsie * careful with our rounding) and solve for n: 195f204e0b8SIan Munsie */ 196f204e0b8SIan Munsie return ((spa_size / 8) - 96) / 17; 197f204e0b8SIan Munsie } 198f204e0b8SIan Munsie 19905155772SDaniel Axtens int cxl_alloc_spa(struct cxl_afu *afu) 200f204e0b8SIan Munsie { 201895a7980SIan Munsie unsigned spa_size; 202895a7980SIan Munsie 203f204e0b8SIan Munsie /* Work out how many pages to allocate */ 2042224b671SIan Munsie afu->native->spa_order = -1; 205f204e0b8SIan Munsie do { 206cbffa3a5SChristophe Lombard afu->native->spa_order++; 207895a7980SIan Munsie spa_size = (1 << afu->native->spa_order) * PAGE_SIZE; 208895a7980SIan Munsie 209895a7980SIan Munsie if (spa_size > 0x100000) { 210895a7980SIan Munsie dev_warn(&afu->dev, "num_of_processes too large for the SPA, limiting to %i (0x%x)\n", 211895a7980SIan Munsie afu->native->spa_max_procs, afu->native->spa_size); 212895a7980SIan Munsie afu->num_procs = afu->native->spa_max_procs; 213895a7980SIan Munsie break; 214895a7980SIan Munsie } 215895a7980SIan Munsie 216895a7980SIan Munsie afu->native->spa_size = spa_size; 217cbffa3a5SChristophe Lombard afu->native->spa_max_procs = spa_max_procs(afu->native->spa_size); 218cbffa3a5SChristophe Lombard } while (afu->native->spa_max_procs < afu->num_procs); 219f204e0b8SIan Munsie 220cbffa3a5SChristophe Lombard if (!(afu->native->spa = (struct cxl_process_element *) 221cbffa3a5SChristophe Lombard __get_free_pages(GFP_KERNEL | __GFP_ZERO, afu->native->spa_order))) { 222f204e0b8SIan Munsie pr_err("cxl_alloc_spa: Unable to allocate scheduled process area\n"); 223f204e0b8SIan Munsie return -ENOMEM; 224f204e0b8SIan Munsie } 225f204e0b8SIan Munsie pr_devel("spa pages: %i afu->spa_max_procs: %i afu->num_procs: %i\n", 226cbffa3a5SChristophe Lombard 1<<afu->native->spa_order, afu->native->spa_max_procs, afu->num_procs); 227f204e0b8SIan Munsie 22805155772SDaniel Axtens return 0; 22905155772SDaniel Axtens } 23005155772SDaniel Axtens 23105155772SDaniel Axtens static void attach_spa(struct cxl_afu *afu) 23205155772SDaniel Axtens { 23305155772SDaniel Axtens u64 spap; 23405155772SDaniel Axtens 235cbffa3a5SChristophe Lombard afu->native->sw_command_status = (__be64 *)((char *)afu->native->spa + 236cbffa3a5SChristophe Lombard ((afu->native->spa_max_procs + 3) * 128)); 237f204e0b8SIan Munsie 238cbffa3a5SChristophe Lombard spap = virt_to_phys(afu->native->spa) & CXL_PSL_SPAP_Addr; 239cbffa3a5SChristophe Lombard spap |= ((afu->native->spa_size >> (12 - CXL_PSL_SPAP_Size_Shift)) - 1) & CXL_PSL_SPAP_Size; 240f204e0b8SIan Munsie spap |= CXL_PSL_SPAP_V; 241cbffa3a5SChristophe Lombard pr_devel("cxl: SPA allocated at 0x%p. Max processes: %i, sw_command_status: 0x%p CXL_PSL_SPAP_An=0x%016llx\n", 242cbffa3a5SChristophe Lombard afu->native->spa, afu->native->spa_max_procs, 243cbffa3a5SChristophe Lombard afu->native->sw_command_status, spap); 244f204e0b8SIan Munsie cxl_p1n_write(afu, CXL_PSL_SPAP_An, spap); 245f204e0b8SIan Munsie } 246f204e0b8SIan Munsie 24705155772SDaniel Axtens static inline void detach_spa(struct cxl_afu *afu) 248f204e0b8SIan Munsie { 249db7933f3SIan Munsie cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); 25005155772SDaniel Axtens } 25105155772SDaniel Axtens 25205155772SDaniel Axtens void cxl_release_spa(struct cxl_afu *afu) 25305155772SDaniel Axtens { 254cbffa3a5SChristophe Lombard if (afu->native->spa) { 255cbffa3a5SChristophe Lombard free_pages((unsigned long) afu->native->spa, 256cbffa3a5SChristophe Lombard afu->native->spa_order); 257cbffa3a5SChristophe Lombard afu->native->spa = NULL; 25805155772SDaniel Axtens } 259f204e0b8SIan Munsie } 260f204e0b8SIan Munsie 261f204e0b8SIan Munsie int cxl_tlb_slb_invalidate(struct cxl *adapter) 262f204e0b8SIan Munsie { 263f204e0b8SIan Munsie unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); 264f204e0b8SIan Munsie 265f204e0b8SIan Munsie pr_devel("CXL adapter wide TLBIA & SLBIA\n"); 266f204e0b8SIan Munsie 267f204e0b8SIan Munsie cxl_p1_write(adapter, CXL_PSL_AFUSEL, CXL_PSL_AFUSEL_A); 268f204e0b8SIan Munsie 269f204e0b8SIan Munsie cxl_p1_write(adapter, CXL_PSL_TLBIA, CXL_TLB_SLB_IQ_ALL); 270f204e0b8SIan Munsie while (cxl_p1_read(adapter, CXL_PSL_TLBIA) & CXL_TLB_SLB_P) { 271f204e0b8SIan Munsie if (time_after_eq(jiffies, timeout)) { 272f204e0b8SIan Munsie dev_warn(&adapter->dev, "WARNING: CXL adapter wide TLBIA timed out!\n"); 273f204e0b8SIan Munsie return -EBUSY; 274f204e0b8SIan Munsie } 2750d400f77SChristophe Lombard if (!cxl_ops->link_ok(adapter, NULL)) 2760b3f9c75SDaniel Axtens return -EIO; 277f204e0b8SIan Munsie cpu_relax(); 278f204e0b8SIan Munsie } 279f204e0b8SIan Munsie 280f204e0b8SIan Munsie cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_ALL); 281f204e0b8SIan Munsie while (cxl_p1_read(adapter, CXL_PSL_SLBIA) & CXL_TLB_SLB_P) { 282f204e0b8SIan Munsie if (time_after_eq(jiffies, timeout)) { 283f204e0b8SIan Munsie dev_warn(&adapter->dev, "WARNING: CXL adapter wide SLBIA timed out!\n"); 284f204e0b8SIan Munsie return -EBUSY; 285f204e0b8SIan Munsie } 2860d400f77SChristophe Lombard if (!cxl_ops->link_ok(adapter, NULL)) 2870b3f9c75SDaniel Axtens return -EIO; 288f204e0b8SIan Munsie cpu_relax(); 289f204e0b8SIan Munsie } 290f204e0b8SIan Munsie return 0; 291f204e0b8SIan Munsie } 292f204e0b8SIan Munsie 293aaa2245eSFrederic Barrat int cxl_data_cache_flush(struct cxl *adapter) 294aaa2245eSFrederic Barrat { 295aaa2245eSFrederic Barrat u64 reg; 296aaa2245eSFrederic Barrat unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); 297aaa2245eSFrederic Barrat 298aaa2245eSFrederic Barrat pr_devel("Flushing data cache\n"); 299aaa2245eSFrederic Barrat 300aaa2245eSFrederic Barrat reg = cxl_p1_read(adapter, CXL_PSL_Control); 301aaa2245eSFrederic Barrat reg |= CXL_PSL_Control_Fr; 302aaa2245eSFrederic Barrat cxl_p1_write(adapter, CXL_PSL_Control, reg); 303aaa2245eSFrederic Barrat 304aaa2245eSFrederic Barrat reg = cxl_p1_read(adapter, CXL_PSL_Control); 305aaa2245eSFrederic Barrat while ((reg & CXL_PSL_Control_Fs_MASK) != CXL_PSL_Control_Fs_Complete) { 306aaa2245eSFrederic Barrat if (time_after_eq(jiffies, timeout)) { 307aaa2245eSFrederic Barrat dev_warn(&adapter->dev, "WARNING: cache flush timed out!\n"); 308aaa2245eSFrederic Barrat return -EBUSY; 309aaa2245eSFrederic Barrat } 310aaa2245eSFrederic Barrat 311aaa2245eSFrederic Barrat if (!cxl_ops->link_ok(adapter, NULL)) { 312aaa2245eSFrederic Barrat dev_warn(&adapter->dev, "WARNING: link down when flushing cache\n"); 313aaa2245eSFrederic Barrat return -EIO; 314aaa2245eSFrederic Barrat } 315aaa2245eSFrederic Barrat cpu_relax(); 316aaa2245eSFrederic Barrat reg = cxl_p1_read(adapter, CXL_PSL_Control); 317aaa2245eSFrederic Barrat } 318aaa2245eSFrederic Barrat 319aaa2245eSFrederic Barrat reg &= ~CXL_PSL_Control_Fr; 320aaa2245eSFrederic Barrat cxl_p1_write(adapter, CXL_PSL_Control, reg); 321aaa2245eSFrederic Barrat return 0; 322aaa2245eSFrederic Barrat } 323aaa2245eSFrederic Barrat 324f204e0b8SIan Munsie static int cxl_write_sstp(struct cxl_afu *afu, u64 sstp0, u64 sstp1) 325f204e0b8SIan Munsie { 326f204e0b8SIan Munsie int rc; 327f204e0b8SIan Munsie 328f204e0b8SIan Munsie /* 1. Disable SSTP by writing 0 to SSTP1[V] */ 329f204e0b8SIan Munsie cxl_p2n_write(afu, CXL_SSTP1_An, 0); 330f204e0b8SIan Munsie 331f204e0b8SIan Munsie /* 2. Invalidate all SLB entries */ 332f204e0b8SIan Munsie if ((rc = cxl_afu_slbia(afu))) 333f204e0b8SIan Munsie return rc; 334f204e0b8SIan Munsie 335f204e0b8SIan Munsie /* 3. Set SSTP0_An */ 336f204e0b8SIan Munsie cxl_p2n_write(afu, CXL_SSTP0_An, sstp0); 337f204e0b8SIan Munsie 338f204e0b8SIan Munsie /* 4. Set SSTP1_An */ 339f204e0b8SIan Munsie cxl_p2n_write(afu, CXL_SSTP1_An, sstp1); 340f204e0b8SIan Munsie 341f204e0b8SIan Munsie return 0; 342f204e0b8SIan Munsie } 343f204e0b8SIan Munsie 344f204e0b8SIan Munsie /* Using per slice version may improve performance here. (ie. SLBIA_An) */ 345f204e0b8SIan Munsie static void slb_invalid(struct cxl_context *ctx) 346f204e0b8SIan Munsie { 347f204e0b8SIan Munsie struct cxl *adapter = ctx->afu->adapter; 348f204e0b8SIan Munsie u64 slbia; 349f204e0b8SIan Munsie 350cbffa3a5SChristophe Lombard WARN_ON(!mutex_is_locked(&ctx->afu->native->spa_mutex)); 351f204e0b8SIan Munsie 352f204e0b8SIan Munsie cxl_p1_write(adapter, CXL_PSL_LBISEL, 353f204e0b8SIan Munsie ((u64)be32_to_cpu(ctx->elem->common.pid) << 32) | 354f204e0b8SIan Munsie be32_to_cpu(ctx->elem->lpid)); 355f204e0b8SIan Munsie cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_LPIDPID); 356f204e0b8SIan Munsie 357f204e0b8SIan Munsie while (1) { 3580d400f77SChristophe Lombard if (!cxl_ops->link_ok(adapter, NULL)) 3590b3f9c75SDaniel Axtens break; 360f204e0b8SIan Munsie slbia = cxl_p1_read(adapter, CXL_PSL_SLBIA); 361f204e0b8SIan Munsie if (!(slbia & CXL_TLB_SLB_P)) 362f204e0b8SIan Munsie break; 363f204e0b8SIan Munsie cpu_relax(); 364f204e0b8SIan Munsie } 365f204e0b8SIan Munsie } 366f204e0b8SIan Munsie 367f204e0b8SIan Munsie static int do_process_element_cmd(struct cxl_context *ctx, 368f204e0b8SIan Munsie u64 cmd, u64 pe_state) 369f204e0b8SIan Munsie { 370f204e0b8SIan Munsie u64 state; 371a98e6e9fSIan Munsie unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); 3729bcf28cdSIan Munsie int rc = 0; 3739bcf28cdSIan Munsie 3749bcf28cdSIan Munsie trace_cxl_llcmd(ctx, cmd); 375f204e0b8SIan Munsie 376f204e0b8SIan Munsie WARN_ON(!ctx->afu->enabled); 377f204e0b8SIan Munsie 378f204e0b8SIan Munsie ctx->elem->software_state = cpu_to_be32(pe_state); 379f204e0b8SIan Munsie smp_wmb(); 380cbffa3a5SChristophe Lombard *(ctx->afu->native->sw_command_status) = cpu_to_be64(cmd | 0 | ctx->pe); 381f204e0b8SIan Munsie smp_mb(); 382f204e0b8SIan Munsie cxl_p1n_write(ctx->afu, CXL_PSL_LLCMD_An, cmd | ctx->pe); 383f204e0b8SIan Munsie while (1) { 384a98e6e9fSIan Munsie if (time_after_eq(jiffies, timeout)) { 385a98e6e9fSIan Munsie dev_warn(&ctx->afu->dev, "WARNING: Process Element Command timed out!\n"); 3869bcf28cdSIan Munsie rc = -EBUSY; 3879bcf28cdSIan Munsie goto out; 388a98e6e9fSIan Munsie } 3890d400f77SChristophe Lombard if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) { 3900b3f9c75SDaniel Axtens dev_warn(&ctx->afu->dev, "WARNING: Device link down, aborting Process Element Command!\n"); 3910b3f9c75SDaniel Axtens rc = -EIO; 3920b3f9c75SDaniel Axtens goto out; 3930b3f9c75SDaniel Axtens } 394cbffa3a5SChristophe Lombard state = be64_to_cpup(ctx->afu->native->sw_command_status); 395f204e0b8SIan Munsie if (state == ~0ULL) { 396f204e0b8SIan Munsie pr_err("cxl: Error adding process element to AFU\n"); 3979bcf28cdSIan Munsie rc = -1; 3989bcf28cdSIan Munsie goto out; 399f204e0b8SIan Munsie } 400f204e0b8SIan Munsie if ((state & (CXL_SPA_SW_CMD_MASK | CXL_SPA_SW_STATE_MASK | CXL_SPA_SW_LINK_MASK)) == 401f204e0b8SIan Munsie (cmd | (cmd >> 16) | ctx->pe)) 402f204e0b8SIan Munsie break; 403f204e0b8SIan Munsie /* 404f204e0b8SIan Munsie * The command won't finish in the PSL if there are 405f204e0b8SIan Munsie * outstanding DSIs. Hence we need to yield here in 406f204e0b8SIan Munsie * case there are outstanding DSIs that we need to 407f204e0b8SIan Munsie * service. Tuning possiblity: we could wait for a 408f204e0b8SIan Munsie * while before sched 409f204e0b8SIan Munsie */ 410f204e0b8SIan Munsie schedule(); 411f204e0b8SIan Munsie 412f204e0b8SIan Munsie } 4139bcf28cdSIan Munsie out: 4149bcf28cdSIan Munsie trace_cxl_llcmd_done(ctx, cmd, rc); 4159bcf28cdSIan Munsie return rc; 416f204e0b8SIan Munsie } 417f204e0b8SIan Munsie 418f204e0b8SIan Munsie static int add_process_element(struct cxl_context *ctx) 419f204e0b8SIan Munsie { 420f204e0b8SIan Munsie int rc = 0; 421f204e0b8SIan Munsie 422cbffa3a5SChristophe Lombard mutex_lock(&ctx->afu->native->spa_mutex); 423f204e0b8SIan Munsie pr_devel("%s Adding pe: %i started\n", __func__, ctx->pe); 424f204e0b8SIan Munsie if (!(rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_ADD, CXL_PE_SOFTWARE_STATE_V))) 425f204e0b8SIan Munsie ctx->pe_inserted = true; 426f204e0b8SIan Munsie pr_devel("%s Adding pe: %i finished\n", __func__, ctx->pe); 427cbffa3a5SChristophe Lombard mutex_unlock(&ctx->afu->native->spa_mutex); 428f204e0b8SIan Munsie return rc; 429f204e0b8SIan Munsie } 430f204e0b8SIan Munsie 431f204e0b8SIan Munsie static int terminate_process_element(struct cxl_context *ctx) 432f204e0b8SIan Munsie { 433f204e0b8SIan Munsie int rc = 0; 434f204e0b8SIan Munsie 435f204e0b8SIan Munsie /* fast path terminate if it's already invalid */ 436f204e0b8SIan Munsie if (!(ctx->elem->software_state & cpu_to_be32(CXL_PE_SOFTWARE_STATE_V))) 437f204e0b8SIan Munsie return rc; 438f204e0b8SIan Munsie 439cbffa3a5SChristophe Lombard mutex_lock(&ctx->afu->native->spa_mutex); 440f204e0b8SIan Munsie pr_devel("%s Terminate pe: %i started\n", __func__, ctx->pe); 4410b3f9c75SDaniel Axtens /* We could be asked to terminate when the hw is down. That 4420b3f9c75SDaniel Axtens * should always succeed: it's not running if the hw has gone 4430b3f9c75SDaniel Axtens * away and is being reset. 4440b3f9c75SDaniel Axtens */ 4450d400f77SChristophe Lombard if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) 446f204e0b8SIan Munsie rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_TERMINATE, 447f204e0b8SIan Munsie CXL_PE_SOFTWARE_STATE_V | CXL_PE_SOFTWARE_STATE_T); 448f204e0b8SIan Munsie ctx->elem->software_state = 0; /* Remove Valid bit */ 449f204e0b8SIan Munsie pr_devel("%s Terminate pe: %i finished\n", __func__, ctx->pe); 450cbffa3a5SChristophe Lombard mutex_unlock(&ctx->afu->native->spa_mutex); 451f204e0b8SIan Munsie return rc; 452f204e0b8SIan Munsie } 453f204e0b8SIan Munsie 454f204e0b8SIan Munsie static int remove_process_element(struct cxl_context *ctx) 455f204e0b8SIan Munsie { 456f204e0b8SIan Munsie int rc = 0; 457f204e0b8SIan Munsie 458cbffa3a5SChristophe Lombard mutex_lock(&ctx->afu->native->spa_mutex); 459f204e0b8SIan Munsie pr_devel("%s Remove pe: %i started\n", __func__, ctx->pe); 4600b3f9c75SDaniel Axtens 4610b3f9c75SDaniel Axtens /* We could be asked to remove when the hw is down. Again, if 4620b3f9c75SDaniel Axtens * the hw is down, the PE is gone, so we succeed. 4630b3f9c75SDaniel Axtens */ 4640d400f77SChristophe Lombard if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) 4650b3f9c75SDaniel Axtens rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_REMOVE, 0); 4660b3f9c75SDaniel Axtens 4670b3f9c75SDaniel Axtens if (!rc) 468f204e0b8SIan Munsie ctx->pe_inserted = false; 469f204e0b8SIan Munsie slb_invalid(ctx); 470f204e0b8SIan Munsie pr_devel("%s Remove pe: %i finished\n", __func__, ctx->pe); 471cbffa3a5SChristophe Lombard mutex_unlock(&ctx->afu->native->spa_mutex); 472f204e0b8SIan Munsie 473f204e0b8SIan Munsie return rc; 474f204e0b8SIan Munsie } 475f204e0b8SIan Munsie 4761a1a94b8SMichael Neuling void cxl_assign_psn_space(struct cxl_context *ctx) 477f204e0b8SIan Munsie { 478f204e0b8SIan Munsie if (!ctx->afu->pp_size || ctx->master) { 479f204e0b8SIan Munsie ctx->psn_phys = ctx->afu->psn_phys; 480f204e0b8SIan Munsie ctx->psn_size = ctx->afu->adapter->ps_size; 481f204e0b8SIan Munsie } else { 482f204e0b8SIan Munsie ctx->psn_phys = ctx->afu->psn_phys + 483cbffa3a5SChristophe Lombard (ctx->afu->native->pp_offset + ctx->afu->pp_size * ctx->pe); 484f204e0b8SIan Munsie ctx->psn_size = ctx->afu->pp_size; 485f204e0b8SIan Munsie } 486f204e0b8SIan Munsie } 487f204e0b8SIan Munsie 488f204e0b8SIan Munsie static int activate_afu_directed(struct cxl_afu *afu) 489f204e0b8SIan Munsie { 490f204e0b8SIan Munsie int rc; 491f204e0b8SIan Munsie 492f204e0b8SIan Munsie dev_info(&afu->dev, "Activating AFU directed mode\n"); 493f204e0b8SIan Munsie 4944108efb0SChristophe Lombard afu->num_procs = afu->max_procs_virtualised; 495cbffa3a5SChristophe Lombard if (afu->native->spa == NULL) { 49605155772SDaniel Axtens if (cxl_alloc_spa(afu)) 497f204e0b8SIan Munsie return -ENOMEM; 49805155772SDaniel Axtens } 49905155772SDaniel Axtens attach_spa(afu); 500f204e0b8SIan Munsie 501f204e0b8SIan Munsie cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_AFU); 502f204e0b8SIan Munsie cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL); 503f204e0b8SIan Munsie cxl_p1n_write(afu, CXL_PSL_ID_An, CXL_PSL_ID_An_F | CXL_PSL_ID_An_L); 504f204e0b8SIan Munsie 505f204e0b8SIan Munsie afu->current_mode = CXL_MODE_DIRECTED; 506f204e0b8SIan Munsie 507f204e0b8SIan Munsie if ((rc = cxl_chardev_m_afu_add(afu))) 508f204e0b8SIan Munsie return rc; 509f204e0b8SIan Munsie 510f204e0b8SIan Munsie if ((rc = cxl_sysfs_afu_m_add(afu))) 511f204e0b8SIan Munsie goto err; 512f204e0b8SIan Munsie 513f204e0b8SIan Munsie if ((rc = cxl_chardev_s_afu_add(afu))) 514f204e0b8SIan Munsie goto err1; 515f204e0b8SIan Munsie 516f204e0b8SIan Munsie return 0; 517f204e0b8SIan Munsie err1: 518f204e0b8SIan Munsie cxl_sysfs_afu_m_remove(afu); 519f204e0b8SIan Munsie err: 520f204e0b8SIan Munsie cxl_chardev_afu_remove(afu); 521f204e0b8SIan Munsie return rc; 522f204e0b8SIan Munsie } 523f204e0b8SIan Munsie 524f204e0b8SIan Munsie #ifdef CONFIG_CPU_LITTLE_ENDIAN 525f204e0b8SIan Munsie #define set_endian(sr) ((sr) |= CXL_PSL_SR_An_LE) 526f204e0b8SIan Munsie #else 527f204e0b8SIan Munsie #define set_endian(sr) ((sr) &= ~(CXL_PSL_SR_An_LE)) 528f204e0b8SIan Munsie #endif 529f204e0b8SIan Munsie 5302f663527SMichael Neuling static u64 calculate_sr(struct cxl_context *ctx) 5312f663527SMichael Neuling { 5322f663527SMichael Neuling u64 sr = 0; 5332f663527SMichael Neuling 534e606e035SFrederic Barrat set_endian(sr); 5352f663527SMichael Neuling if (ctx->master) 5362f663527SMichael Neuling sr |= CXL_PSL_SR_An_MP; 5372f663527SMichael Neuling if (mfspr(SPRN_LPCR) & LPCR_TC) 5382f663527SMichael Neuling sr |= CXL_PSL_SR_An_TC; 5392f663527SMichael Neuling if (ctx->kernel) { 5407a0d85d3SIan Munsie if (!ctx->real_mode) 5417a0d85d3SIan Munsie sr |= CXL_PSL_SR_An_R; 5427a0d85d3SIan Munsie sr |= (mfmsr() & MSR_SF) | CXL_PSL_SR_An_HV; 5432f663527SMichael Neuling } else { 5442f663527SMichael Neuling sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R; 5452f663527SMichael Neuling sr &= ~(CXL_PSL_SR_An_HV); 5462f663527SMichael Neuling if (!test_tsk_thread_flag(current, TIF_32BIT)) 5472f663527SMichael Neuling sr |= CXL_PSL_SR_An_SF; 5482f663527SMichael Neuling } 5492f663527SMichael Neuling return sr; 5502f663527SMichael Neuling } 5512f663527SMichael Neuling 552292841b0SIan Munsie static void update_ivtes_directed(struct cxl_context *ctx) 553292841b0SIan Munsie { 554292841b0SIan Munsie bool need_update = (ctx->status == STARTED); 555292841b0SIan Munsie int r; 556292841b0SIan Munsie 557292841b0SIan Munsie if (need_update) { 558292841b0SIan Munsie WARN_ON(terminate_process_element(ctx)); 559292841b0SIan Munsie WARN_ON(remove_process_element(ctx)); 560292841b0SIan Munsie } 561292841b0SIan Munsie 562292841b0SIan Munsie for (r = 0; r < CXL_IRQ_RANGES; r++) { 563292841b0SIan Munsie ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]); 564292841b0SIan Munsie ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]); 565292841b0SIan Munsie } 566292841b0SIan Munsie 567292841b0SIan Munsie /* 568292841b0SIan Munsie * Theoretically we could use the update llcmd, instead of a 569292841b0SIan Munsie * terminate/remove/add (or if an atomic update was required we could 570292841b0SIan Munsie * do a suspend/update/resume), however it seems there might be issues 571292841b0SIan Munsie * with the update llcmd on some cards (including those using an XSL on 572292841b0SIan Munsie * an ASIC) so for now it's safest to go with the commands that are 573292841b0SIan Munsie * known to work. In the future if we come across a situation where the 574292841b0SIan Munsie * card may be performing transactions using the same PE while we are 575292841b0SIan Munsie * doing this update we might need to revisit this. 576292841b0SIan Munsie */ 577292841b0SIan Munsie if (need_update) 578292841b0SIan Munsie WARN_ON(add_process_element(ctx)); 579292841b0SIan Munsie } 580292841b0SIan Munsie 581f204e0b8SIan Munsie static int attach_afu_directed(struct cxl_context *ctx, u64 wed, u64 amr) 582f204e0b8SIan Munsie { 5832f663527SMichael Neuling u32 pid; 584292841b0SIan Munsie int result; 585f204e0b8SIan Munsie 5861a1a94b8SMichael Neuling cxl_assign_psn_space(ctx); 587f204e0b8SIan Munsie 588f204e0b8SIan Munsie ctx->elem->ctxtime = 0; /* disable */ 589f204e0b8SIan Munsie ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID)); 590f204e0b8SIan Munsie ctx->elem->haurp = 0; /* disable */ 591f204e0b8SIan Munsie ctx->elem->sdr = cpu_to_be64(mfspr(SPRN_SDR1)); 592f204e0b8SIan Munsie 5932f663527SMichael Neuling pid = current->pid; 5942f663527SMichael Neuling if (ctx->kernel) 5952f663527SMichael Neuling pid = 0; 596f204e0b8SIan Munsie ctx->elem->common.tid = 0; 5972f663527SMichael Neuling ctx->elem->common.pid = cpu_to_be32(pid); 5982f663527SMichael Neuling 5992f663527SMichael Neuling ctx->elem->sr = cpu_to_be64(calculate_sr(ctx)); 600f204e0b8SIan Munsie 601f204e0b8SIan Munsie ctx->elem->common.csrp = 0; /* disable */ 602f204e0b8SIan Munsie ctx->elem->common.aurp0 = 0; /* disable */ 603f204e0b8SIan Munsie ctx->elem->common.aurp1 = 0; /* disable */ 604f204e0b8SIan Munsie 605f204e0b8SIan Munsie cxl_prefault(ctx, wed); 606f204e0b8SIan Munsie 607f204e0b8SIan Munsie ctx->elem->common.sstp0 = cpu_to_be64(ctx->sstp0); 608f204e0b8SIan Munsie ctx->elem->common.sstp1 = cpu_to_be64(ctx->sstp1); 609f204e0b8SIan Munsie 6103c206fa7SIan Munsie /* 6113c206fa7SIan Munsie * Ensure we have the multiplexed PSL interrupt set up to take faults 6123c206fa7SIan Munsie * for kernel contexts that may not have allocated any AFU IRQs at all: 6133c206fa7SIan Munsie */ 6143c206fa7SIan Munsie if (ctx->irqs.range[0] == 0) { 6153c206fa7SIan Munsie ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq; 6163c206fa7SIan Munsie ctx->irqs.range[0] = 1; 6173c206fa7SIan Munsie } 6183c206fa7SIan Munsie 619292841b0SIan Munsie update_ivtes_directed(ctx); 620f204e0b8SIan Munsie 621f204e0b8SIan Munsie ctx->elem->common.amr = cpu_to_be64(amr); 622f204e0b8SIan Munsie ctx->elem->common.wed = cpu_to_be64(wed); 623f204e0b8SIan Munsie 624f204e0b8SIan Munsie /* first guy needs to enable */ 6255be587b1SFrederic Barrat if ((result = cxl_ops->afu_check_and_enable(ctx->afu))) 626f204e0b8SIan Munsie return result; 627f204e0b8SIan Munsie 628368857c1SDaniel Axtens return add_process_element(ctx); 629f204e0b8SIan Munsie } 630f204e0b8SIan Munsie 631f204e0b8SIan Munsie static int deactivate_afu_directed(struct cxl_afu *afu) 632f204e0b8SIan Munsie { 633f204e0b8SIan Munsie dev_info(&afu->dev, "Deactivating AFU directed mode\n"); 634f204e0b8SIan Munsie 635f204e0b8SIan Munsie afu->current_mode = 0; 636f204e0b8SIan Munsie afu->num_procs = 0; 637f204e0b8SIan Munsie 638f204e0b8SIan Munsie cxl_sysfs_afu_m_remove(afu); 639f204e0b8SIan Munsie cxl_chardev_afu_remove(afu); 640f204e0b8SIan Munsie 6415e7823c9SIan Munsie /* 6425e7823c9SIan Munsie * The CAIA section 2.2.1 indicates that the procedure for starting and 6435e7823c9SIan Munsie * stopping an AFU in AFU directed mode is AFU specific, which is not 6445e7823c9SIan Munsie * ideal since this code is generic and with one exception has no 6455e7823c9SIan Munsie * knowledge of the AFU. This is in contrast to the procedure for 6465e7823c9SIan Munsie * disabling a dedicated process AFU, which is documented to just 6475e7823c9SIan Munsie * require a reset. The architecture does indicate that both an AFU 6485e7823c9SIan Munsie * reset and an AFU disable should result in the AFU being disabled and 6495e7823c9SIan Munsie * we do both followed by a PSL purge for safety. 6505e7823c9SIan Munsie * 6515e7823c9SIan Munsie * Notably we used to have some issues with the disable sequence on PSL 6525e7823c9SIan Munsie * cards, which is why we ended up using this heavy weight procedure in 6535e7823c9SIan Munsie * the first place, however a bug was discovered that had rendered the 6545e7823c9SIan Munsie * disable operation ineffective, so it is conceivable that was the 6555e7823c9SIan Munsie * sole explanation for those difficulties. Careful regression testing 6565e7823c9SIan Munsie * is recommended if anyone attempts to remove or reorder these 6575e7823c9SIan Munsie * operations. 6585e7823c9SIan Munsie * 6595e7823c9SIan Munsie * The XSL on the Mellanox CX4 behaves a little differently from the 6605e7823c9SIan Munsie * PSL based cards and will time out an AFU reset if the AFU is still 6615e7823c9SIan Munsie * enabled. That card is special in that we do have a means to identify 6625e7823c9SIan Munsie * it from this code, so in that case we skip the reset and just use a 6635e7823c9SIan Munsie * disable/purge to avoid the timeout and corresponding noise in the 6645e7823c9SIan Munsie * kernel log. 6655e7823c9SIan Munsie */ 6665e7823c9SIan Munsie if (afu->adapter->native->sl_ops->needs_reset_before_disable) 6675be587b1SFrederic Barrat cxl_ops->afu_reset(afu); 668f204e0b8SIan Munsie cxl_afu_disable(afu); 669f204e0b8SIan Munsie cxl_psl_purge(afu); 670f204e0b8SIan Munsie 671f204e0b8SIan Munsie return 0; 672f204e0b8SIan Munsie } 673f204e0b8SIan Munsie 674f204e0b8SIan Munsie static int activate_dedicated_process(struct cxl_afu *afu) 675f204e0b8SIan Munsie { 676f204e0b8SIan Munsie dev_info(&afu->dev, "Activating dedicated process mode\n"); 677f204e0b8SIan Munsie 678f204e0b8SIan Munsie cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_Process); 679f204e0b8SIan Munsie 680f204e0b8SIan Munsie cxl_p1n_write(afu, CXL_PSL_CtxTime_An, 0); /* disable */ 681f204e0b8SIan Munsie cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); /* disable */ 682f204e0b8SIan Munsie cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL); 683f204e0b8SIan Munsie cxl_p1n_write(afu, CXL_PSL_LPID_An, mfspr(SPRN_LPID)); 684f204e0b8SIan Munsie cxl_p1n_write(afu, CXL_HAURP_An, 0); /* disable */ 685f204e0b8SIan Munsie cxl_p1n_write(afu, CXL_PSL_SDR_An, mfspr(SPRN_SDR1)); 686f204e0b8SIan Munsie 687f204e0b8SIan Munsie cxl_p2n_write(afu, CXL_CSRP_An, 0); /* disable */ 688f204e0b8SIan Munsie cxl_p2n_write(afu, CXL_AURP0_An, 0); /* disable */ 689f204e0b8SIan Munsie cxl_p2n_write(afu, CXL_AURP1_An, 0); /* disable */ 690f204e0b8SIan Munsie 691f204e0b8SIan Munsie afu->current_mode = CXL_MODE_DEDICATED; 692f204e0b8SIan Munsie afu->num_procs = 1; 693f204e0b8SIan Munsie 694f204e0b8SIan Munsie return cxl_chardev_d_afu_add(afu); 695f204e0b8SIan Munsie } 696f204e0b8SIan Munsie 697292841b0SIan Munsie static void update_ivtes_dedicated(struct cxl_context *ctx) 698292841b0SIan Munsie { 699292841b0SIan Munsie struct cxl_afu *afu = ctx->afu; 700292841b0SIan Munsie 701292841b0SIan Munsie cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 702292841b0SIan Munsie (((u64)ctx->irqs.offset[0] & 0xffff) << 48) | 703292841b0SIan Munsie (((u64)ctx->irqs.offset[1] & 0xffff) << 32) | 704292841b0SIan Munsie (((u64)ctx->irqs.offset[2] & 0xffff) << 16) | 705292841b0SIan Munsie ((u64)ctx->irqs.offset[3] & 0xffff)); 706292841b0SIan Munsie cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, (u64) 707292841b0SIan Munsie (((u64)ctx->irqs.range[0] & 0xffff) << 48) | 708292841b0SIan Munsie (((u64)ctx->irqs.range[1] & 0xffff) << 32) | 709292841b0SIan Munsie (((u64)ctx->irqs.range[2] & 0xffff) << 16) | 710292841b0SIan Munsie ((u64)ctx->irqs.range[3] & 0xffff)); 711292841b0SIan Munsie } 712292841b0SIan Munsie 713f204e0b8SIan Munsie static int attach_dedicated(struct cxl_context *ctx, u64 wed, u64 amr) 714f204e0b8SIan Munsie { 715f204e0b8SIan Munsie struct cxl_afu *afu = ctx->afu; 7162f663527SMichael Neuling u64 pid; 717f204e0b8SIan Munsie int rc; 718f204e0b8SIan Munsie 7192f663527SMichael Neuling pid = (u64)current->pid << 32; 7202f663527SMichael Neuling if (ctx->kernel) 7212f663527SMichael Neuling pid = 0; 7222f663527SMichael Neuling cxl_p2n_write(afu, CXL_PSL_PID_TID_An, pid); 7232f663527SMichael Neuling 7242f663527SMichael Neuling cxl_p1n_write(afu, CXL_PSL_SR_An, calculate_sr(ctx)); 725f204e0b8SIan Munsie 726f204e0b8SIan Munsie if ((rc = cxl_write_sstp(afu, ctx->sstp0, ctx->sstp1))) 727f204e0b8SIan Munsie return rc; 728f204e0b8SIan Munsie 729f204e0b8SIan Munsie cxl_prefault(ctx, wed); 730f204e0b8SIan Munsie 731292841b0SIan Munsie update_ivtes_dedicated(ctx); 732f204e0b8SIan Munsie 733f204e0b8SIan Munsie cxl_p2n_write(afu, CXL_PSL_AMR_An, amr); 734f204e0b8SIan Munsie 735f204e0b8SIan Munsie /* master only context for dedicated */ 7361a1a94b8SMichael Neuling cxl_assign_psn_space(ctx); 737f204e0b8SIan Munsie 7385be587b1SFrederic Barrat if ((rc = cxl_ops->afu_reset(afu))) 739f204e0b8SIan Munsie return rc; 740f204e0b8SIan Munsie 741f204e0b8SIan Munsie cxl_p2n_write(afu, CXL_PSL_WED_An, wed); 742f204e0b8SIan Munsie 743f204e0b8SIan Munsie return afu_enable(afu); 744f204e0b8SIan Munsie } 745f204e0b8SIan Munsie 746f204e0b8SIan Munsie static int deactivate_dedicated_process(struct cxl_afu *afu) 747f204e0b8SIan Munsie { 748f204e0b8SIan Munsie dev_info(&afu->dev, "Deactivating dedicated process mode\n"); 749f204e0b8SIan Munsie 750f204e0b8SIan Munsie afu->current_mode = 0; 751f204e0b8SIan Munsie afu->num_procs = 0; 752f204e0b8SIan Munsie 753f204e0b8SIan Munsie cxl_chardev_afu_remove(afu); 754f204e0b8SIan Munsie 755f204e0b8SIan Munsie return 0; 756f204e0b8SIan Munsie } 757f204e0b8SIan Munsie 7582b04cf31SFrederic Barrat static int native_afu_deactivate_mode(struct cxl_afu *afu, int mode) 759f204e0b8SIan Munsie { 760f204e0b8SIan Munsie if (mode == CXL_MODE_DIRECTED) 761f204e0b8SIan Munsie return deactivate_afu_directed(afu); 762f204e0b8SIan Munsie if (mode == CXL_MODE_DEDICATED) 763f204e0b8SIan Munsie return deactivate_dedicated_process(afu); 764f204e0b8SIan Munsie return 0; 765f204e0b8SIan Munsie } 766f204e0b8SIan Munsie 7672b04cf31SFrederic Barrat static int native_afu_activate_mode(struct cxl_afu *afu, int mode) 768f204e0b8SIan Munsie { 769f204e0b8SIan Munsie if (!mode) 770f204e0b8SIan Munsie return 0; 771f204e0b8SIan Munsie if (!(mode & afu->modes_supported)) 772f204e0b8SIan Munsie return -EINVAL; 773f204e0b8SIan Munsie 7740d400f77SChristophe Lombard if (!cxl_ops->link_ok(afu->adapter, afu)) { 7750b3f9c75SDaniel Axtens WARN(1, "Device link is down, refusing to activate!\n"); 7760b3f9c75SDaniel Axtens return -EIO; 7770b3f9c75SDaniel Axtens } 7780b3f9c75SDaniel Axtens 779f204e0b8SIan Munsie if (mode == CXL_MODE_DIRECTED) 780f204e0b8SIan Munsie return activate_afu_directed(afu); 781f204e0b8SIan Munsie if (mode == CXL_MODE_DEDICATED) 782f204e0b8SIan Munsie return activate_dedicated_process(afu); 783f204e0b8SIan Munsie 784f204e0b8SIan Munsie return -EINVAL; 785f204e0b8SIan Munsie } 786f204e0b8SIan Munsie 7872b04cf31SFrederic Barrat static int native_attach_process(struct cxl_context *ctx, bool kernel, 7882b04cf31SFrederic Barrat u64 wed, u64 amr) 789f204e0b8SIan Munsie { 7900d400f77SChristophe Lombard if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) { 7910b3f9c75SDaniel Axtens WARN(1, "Device link is down, refusing to attach process!\n"); 7920b3f9c75SDaniel Axtens return -EIO; 7930b3f9c75SDaniel Axtens } 7940b3f9c75SDaniel Axtens 795f204e0b8SIan Munsie ctx->kernel = kernel; 796f204e0b8SIan Munsie if (ctx->afu->current_mode == CXL_MODE_DIRECTED) 797f204e0b8SIan Munsie return attach_afu_directed(ctx, wed, amr); 798f204e0b8SIan Munsie 799f204e0b8SIan Munsie if (ctx->afu->current_mode == CXL_MODE_DEDICATED) 800f204e0b8SIan Munsie return attach_dedicated(ctx, wed, amr); 801f204e0b8SIan Munsie 802f204e0b8SIan Munsie return -EINVAL; 803f204e0b8SIan Munsie } 804f204e0b8SIan Munsie 805f204e0b8SIan Munsie static inline int detach_process_native_dedicated(struct cxl_context *ctx) 806f204e0b8SIan Munsie { 8075e7823c9SIan Munsie /* 8085e7823c9SIan Munsie * The CAIA section 2.1.1 indicates that we need to do an AFU reset to 8095e7823c9SIan Munsie * stop the AFU in dedicated mode (we therefore do not make that 8105e7823c9SIan Munsie * optional like we do in the afu directed path). It does not indicate 8115e7823c9SIan Munsie * that we need to do an explicit disable (which should occur 8125e7823c9SIan Munsie * implicitly as part of the reset) or purge, but we do these as well 8135e7823c9SIan Munsie * to be on the safe side. 8145e7823c9SIan Munsie * 8155e7823c9SIan Munsie * Notably we used to have some issues with the disable sequence 8165e7823c9SIan Munsie * (before the sequence was spelled out in the architecture) which is 8175e7823c9SIan Munsie * why we were so heavy weight in the first place, however a bug was 8185e7823c9SIan Munsie * discovered that had rendered the disable operation ineffective, so 8195e7823c9SIan Munsie * it is conceivable that was the sole explanation for those 8205e7823c9SIan Munsie * difficulties. Point is, we should be careful and do some regression 8215e7823c9SIan Munsie * testing if we ever attempt to remove any part of this procedure. 8225e7823c9SIan Munsie */ 8235be587b1SFrederic Barrat cxl_ops->afu_reset(ctx->afu); 824f204e0b8SIan Munsie cxl_afu_disable(ctx->afu); 825f204e0b8SIan Munsie cxl_psl_purge(ctx->afu); 826f204e0b8SIan Munsie return 0; 827f204e0b8SIan Munsie } 828f204e0b8SIan Munsie 829292841b0SIan Munsie static void native_update_ivtes(struct cxl_context *ctx) 830292841b0SIan Munsie { 831292841b0SIan Munsie if (ctx->afu->current_mode == CXL_MODE_DIRECTED) 832292841b0SIan Munsie return update_ivtes_directed(ctx); 833292841b0SIan Munsie if (ctx->afu->current_mode == CXL_MODE_DEDICATED) 834292841b0SIan Munsie return update_ivtes_dedicated(ctx); 835292841b0SIan Munsie WARN(1, "native_update_ivtes: Bad mode\n"); 836292841b0SIan Munsie } 837292841b0SIan Munsie 838f204e0b8SIan Munsie static inline int detach_process_native_afu_directed(struct cxl_context *ctx) 839f204e0b8SIan Munsie { 840f204e0b8SIan Munsie if (!ctx->pe_inserted) 841f204e0b8SIan Munsie return 0; 842f204e0b8SIan Munsie if (terminate_process_element(ctx)) 843f204e0b8SIan Munsie return -1; 844f204e0b8SIan Munsie if (remove_process_element(ctx)) 845f204e0b8SIan Munsie return -1; 846f204e0b8SIan Munsie 847f204e0b8SIan Munsie return 0; 848f204e0b8SIan Munsie } 849f204e0b8SIan Munsie 8502b04cf31SFrederic Barrat static int native_detach_process(struct cxl_context *ctx) 851f204e0b8SIan Munsie { 8529bcf28cdSIan Munsie trace_cxl_detach(ctx); 8539bcf28cdSIan Munsie 854f204e0b8SIan Munsie if (ctx->afu->current_mode == CXL_MODE_DEDICATED) 855f204e0b8SIan Munsie return detach_process_native_dedicated(ctx); 856f204e0b8SIan Munsie 857f204e0b8SIan Munsie return detach_process_native_afu_directed(ctx); 858f204e0b8SIan Munsie } 859f204e0b8SIan Munsie 8602b04cf31SFrederic Barrat static int native_get_irq_info(struct cxl_afu *afu, struct cxl_irq_info *info) 861f204e0b8SIan Munsie { 862f204e0b8SIan Munsie u64 pidtid; 863f204e0b8SIan Munsie 8640b3f9c75SDaniel Axtens /* If the adapter has gone away, we can't get any meaningful 8650b3f9c75SDaniel Axtens * information. 8660b3f9c75SDaniel Axtens */ 8670d400f77SChristophe Lombard if (!cxl_ops->link_ok(afu->adapter, afu)) 8680b3f9c75SDaniel Axtens return -EIO; 8690b3f9c75SDaniel Axtens 870bc78b05bSIan Munsie info->dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); 871bc78b05bSIan Munsie info->dar = cxl_p2n_read(afu, CXL_PSL_DAR_An); 872bc78b05bSIan Munsie info->dsr = cxl_p2n_read(afu, CXL_PSL_DSR_An); 873bc78b05bSIan Munsie pidtid = cxl_p2n_read(afu, CXL_PSL_PID_TID_An); 874f204e0b8SIan Munsie info->pid = pidtid >> 32; 875f204e0b8SIan Munsie info->tid = pidtid & 0xffffffff; 876bc78b05bSIan Munsie info->afu_err = cxl_p2n_read(afu, CXL_AFU_ERR_An); 877bc78b05bSIan Munsie info->errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); 878444c4ba4SChristophe Lombard info->proc_handle = 0; 879f204e0b8SIan Munsie 880f204e0b8SIan Munsie return 0; 881f204e0b8SIan Munsie } 882f204e0b8SIan Munsie 8836d382616SFrederic Barrat void cxl_native_psl_irq_dump_regs(struct cxl_context *ctx) 884d56d301bSFrederic Barrat { 885d56d301bSFrederic Barrat u64 fir1, fir2, fir_slice, serr, afu_debug; 886d56d301bSFrederic Barrat 887d56d301bSFrederic Barrat fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR1); 888d56d301bSFrederic Barrat fir2 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR2); 889d56d301bSFrederic Barrat fir_slice = cxl_p1n_read(ctx->afu, CXL_PSL_FIR_SLICE_An); 890d56d301bSFrederic Barrat afu_debug = cxl_p1n_read(ctx->afu, CXL_AFU_DEBUG_An); 891d56d301bSFrederic Barrat 892d56d301bSFrederic Barrat dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1); 893d56d301bSFrederic Barrat dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%016llx\n", fir2); 8946d382616SFrederic Barrat if (ctx->afu->adapter->native->sl_ops->register_serr_irq) { 8956d382616SFrederic Barrat serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An); 8966e0c50f9SPhilippe Bergheaud cxl_afu_decode_psl_serr(ctx->afu, serr); 8976d382616SFrederic Barrat } 898d56d301bSFrederic Barrat dev_crit(&ctx->afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice); 899d56d301bSFrederic Barrat dev_crit(&ctx->afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug); 9006d382616SFrederic Barrat } 901d56d301bSFrederic Barrat 9026d382616SFrederic Barrat static irqreturn_t native_handle_psl_slice_error(struct cxl_context *ctx, 9036d382616SFrederic Barrat u64 dsisr, u64 errstat) 9046d382616SFrederic Barrat { 9056d382616SFrederic Barrat 9066d382616SFrederic Barrat dev_crit(&ctx->afu->dev, "PSL ERROR STATUS: 0x%016llx\n", errstat); 9076d382616SFrederic Barrat 9086d382616SFrederic Barrat if (ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers) 9096d382616SFrederic Barrat ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers(ctx); 9106d382616SFrederic Barrat 9116d382616SFrederic Barrat if (ctx->afu->adapter->native->sl_ops->debugfs_stop_trace) { 912d56d301bSFrederic Barrat dev_crit(&ctx->afu->dev, "STOPPING CXL TRACE\n"); 9136d382616SFrederic Barrat ctx->afu->adapter->native->sl_ops->debugfs_stop_trace(ctx->afu->adapter); 9146d382616SFrederic Barrat } 915d56d301bSFrederic Barrat 9165be587b1SFrederic Barrat return cxl_ops->ack_irq(ctx, 0, errstat); 917d56d301bSFrederic Barrat } 918d56d301bSFrederic Barrat 919d56d301bSFrederic Barrat static irqreturn_t fail_psl_irq(struct cxl_afu *afu, struct cxl_irq_info *irq_info) 920d56d301bSFrederic Barrat { 921d56d301bSFrederic Barrat if (irq_info->dsisr & CXL_PSL_DSISR_TRANS) 922d56d301bSFrederic Barrat cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); 923d56d301bSFrederic Barrat else 924d56d301bSFrederic Barrat cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); 925d56d301bSFrederic Barrat 926d56d301bSFrederic Barrat return IRQ_HANDLED; 927d56d301bSFrederic Barrat } 928d56d301bSFrederic Barrat 9292b04cf31SFrederic Barrat static irqreturn_t native_irq_multiplexed(int irq, void *data) 930d56d301bSFrederic Barrat { 931d56d301bSFrederic Barrat struct cxl_afu *afu = data; 932d56d301bSFrederic Barrat struct cxl_context *ctx; 933d56d301bSFrederic Barrat struct cxl_irq_info irq_info; 934abf051beSVaibhav Jain u64 phreg = cxl_p2n_read(afu, CXL_PSL_PEHandle_An); 935abf051beSVaibhav Jain int ph, ret; 936d56d301bSFrederic Barrat 937abf051beSVaibhav Jain /* check if eeh kicked in while the interrupt was in flight */ 938abf051beSVaibhav Jain if (unlikely(phreg == ~0ULL)) { 939abf051beSVaibhav Jain dev_warn(&afu->dev, 940abf051beSVaibhav Jain "Ignoring slice interrupt(%d) due to fenced card", 941abf051beSVaibhav Jain irq); 942abf051beSVaibhav Jain return IRQ_HANDLED; 943abf051beSVaibhav Jain } 944abf051beSVaibhav Jain /* Mask the pe-handle from register value */ 945abf051beSVaibhav Jain ph = phreg & 0xffff; 9462b04cf31SFrederic Barrat if ((ret = native_get_irq_info(afu, &irq_info))) { 947d56d301bSFrederic Barrat WARN(1, "Unable to get CXL IRQ Info: %i\n", ret); 948d56d301bSFrederic Barrat return fail_psl_irq(afu, &irq_info); 949d56d301bSFrederic Barrat } 950d56d301bSFrederic Barrat 951d56d301bSFrederic Barrat rcu_read_lock(); 952d56d301bSFrederic Barrat ctx = idr_find(&afu->contexts_idr, ph); 953d56d301bSFrederic Barrat if (ctx) { 954d56d301bSFrederic Barrat ret = cxl_irq(irq, ctx, &irq_info); 955d56d301bSFrederic Barrat rcu_read_unlock(); 956d56d301bSFrederic Barrat return ret; 957d56d301bSFrederic Barrat } 958d56d301bSFrederic Barrat rcu_read_unlock(); 959d56d301bSFrederic Barrat 960d56d301bSFrederic Barrat WARN(1, "Unable to demultiplex CXL PSL IRQ for PE %i DSISR %016llx DAR" 961d56d301bSFrederic Barrat " %016llx\n(Possible AFU HW issue - was a term/remove acked" 962d56d301bSFrederic Barrat " with outstanding transactions?)\n", ph, irq_info.dsisr, 963d56d301bSFrederic Barrat irq_info.dar); 964d56d301bSFrederic Barrat return fail_psl_irq(afu, &irq_info); 965d56d301bSFrederic Barrat } 966d56d301bSFrederic Barrat 9676fd40f19SAndrew Donnellan static void native_irq_wait(struct cxl_context *ctx) 9682bc79ffcSMichael Neuling { 9692bc79ffcSMichael Neuling u64 dsisr; 9702bc79ffcSMichael Neuling int timeout = 1000; 9712bc79ffcSMichael Neuling int ph; 9722bc79ffcSMichael Neuling 9732bc79ffcSMichael Neuling /* 9742bc79ffcSMichael Neuling * Wait until no further interrupts are presented by the PSL 9752bc79ffcSMichael Neuling * for this context. 9762bc79ffcSMichael Neuling */ 9772bc79ffcSMichael Neuling while (timeout--) { 9782bc79ffcSMichael Neuling ph = cxl_p2n_read(ctx->afu, CXL_PSL_PEHandle_An) & 0xffff; 9792bc79ffcSMichael Neuling if (ph != ctx->pe) 9802bc79ffcSMichael Neuling return; 9812bc79ffcSMichael Neuling dsisr = cxl_p2n_read(ctx->afu, CXL_PSL_DSISR_An); 9822bc79ffcSMichael Neuling if ((dsisr & CXL_PSL_DSISR_PENDING) == 0) 9832bc79ffcSMichael Neuling return; 9842bc79ffcSMichael Neuling /* 9852bc79ffcSMichael Neuling * We are waiting for the workqueue to process our 9862bc79ffcSMichael Neuling * irq, so need to let that run here. 9872bc79ffcSMichael Neuling */ 9882bc79ffcSMichael Neuling msleep(1); 9892bc79ffcSMichael Neuling } 9902bc79ffcSMichael Neuling 9912bc79ffcSMichael Neuling dev_warn(&ctx->afu->dev, "WARNING: waiting on DSI for PE %i" 9922bc79ffcSMichael Neuling " DSISR %016llx!\n", ph, dsisr); 9932bc79ffcSMichael Neuling return; 9942bc79ffcSMichael Neuling } 9952bc79ffcSMichael Neuling 9962b04cf31SFrederic Barrat static irqreturn_t native_slice_irq_err(int irq, void *data) 997d56d301bSFrederic Barrat { 998d56d301bSFrederic Barrat struct cxl_afu *afu = data; 9996e0c50f9SPhilippe Bergheaud u64 fir_slice, errstat, serr, afu_debug, afu_error, dsisr; 1000d56d301bSFrederic Barrat 10016d382616SFrederic Barrat /* 10026d382616SFrederic Barrat * slice err interrupt is only used with full PSL (no XSL) 10036d382616SFrederic Barrat */ 1004d56d301bSFrederic Barrat serr = cxl_p1n_read(afu, CXL_PSL_SERR_An); 1005d56d301bSFrederic Barrat fir_slice = cxl_p1n_read(afu, CXL_PSL_FIR_SLICE_An); 1006d56d301bSFrederic Barrat errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); 1007d56d301bSFrederic Barrat afu_debug = cxl_p1n_read(afu, CXL_AFU_DEBUG_An); 10086e0c50f9SPhilippe Bergheaud afu_error = cxl_p2n_read(afu, CXL_AFU_ERR_An); 10096e0c50f9SPhilippe Bergheaud dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); 10106e0c50f9SPhilippe Bergheaud cxl_afu_decode_psl_serr(afu, serr); 1011d56d301bSFrederic Barrat dev_crit(&afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice); 1012d56d301bSFrederic Barrat dev_crit(&afu->dev, "CXL_PSL_ErrStat_An: 0x%016llx\n", errstat); 1013d56d301bSFrederic Barrat dev_crit(&afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug); 10146e0c50f9SPhilippe Bergheaud dev_crit(&afu->dev, "AFU_ERR_An: 0x%.16llx\n", afu_error); 10156e0c50f9SPhilippe Bergheaud dev_crit(&afu->dev, "PSL_DSISR_An: 0x%.16llx\n", dsisr); 1016d56d301bSFrederic Barrat 1017d56d301bSFrederic Barrat cxl_p1n_write(afu, CXL_PSL_SERR_An, serr); 1018d56d301bSFrederic Barrat 1019d56d301bSFrederic Barrat return IRQ_HANDLED; 1020d56d301bSFrederic Barrat } 1021d56d301bSFrederic Barrat 10226d382616SFrederic Barrat void cxl_native_err_irq_dump_regs(struct cxl *adapter) 10236d382616SFrederic Barrat { 10246d382616SFrederic Barrat u64 fir1, fir2; 10256d382616SFrederic Barrat 10266d382616SFrederic Barrat fir1 = cxl_p1_read(adapter, CXL_PSL_FIR1); 10276d382616SFrederic Barrat fir2 = cxl_p1_read(adapter, CXL_PSL_FIR2); 10286d382616SFrederic Barrat 10296d382616SFrederic Barrat dev_crit(&adapter->dev, "PSL_FIR1: 0x%016llx\nPSL_FIR2: 0x%016llx\n", fir1, fir2); 10306d382616SFrederic Barrat } 10316d382616SFrederic Barrat 10322b04cf31SFrederic Barrat static irqreturn_t native_irq_err(int irq, void *data) 1033d56d301bSFrederic Barrat { 1034d56d301bSFrederic Barrat struct cxl *adapter = data; 10356d382616SFrederic Barrat u64 err_ivte; 1036d56d301bSFrederic Barrat 1037d56d301bSFrederic Barrat WARN(1, "CXL ERROR interrupt %i\n", irq); 1038d56d301bSFrederic Barrat 1039d56d301bSFrederic Barrat err_ivte = cxl_p1_read(adapter, CXL_PSL_ErrIVTE); 1040d56d301bSFrederic Barrat dev_crit(&adapter->dev, "PSL_ErrIVTE: 0x%016llx\n", err_ivte); 1041d56d301bSFrederic Barrat 10426d382616SFrederic Barrat if (adapter->native->sl_ops->debugfs_stop_trace) { 1043d56d301bSFrederic Barrat dev_crit(&adapter->dev, "STOPPING CXL TRACE\n"); 10446d382616SFrederic Barrat adapter->native->sl_ops->debugfs_stop_trace(adapter); 10456d382616SFrederic Barrat } 1046d56d301bSFrederic Barrat 10476d382616SFrederic Barrat if (adapter->native->sl_ops->err_irq_dump_registers) 10486d382616SFrederic Barrat adapter->native->sl_ops->err_irq_dump_registers(adapter); 1049d56d301bSFrederic Barrat 1050d56d301bSFrederic Barrat return IRQ_HANDLED; 1051d56d301bSFrederic Barrat } 1052d56d301bSFrederic Barrat 10532b04cf31SFrederic Barrat int cxl_native_register_psl_err_irq(struct cxl *adapter) 1054d56d301bSFrederic Barrat { 1055d56d301bSFrederic Barrat int rc; 1056d56d301bSFrederic Barrat 1057d56d301bSFrederic Barrat adapter->irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err", 1058d56d301bSFrederic Barrat dev_name(&adapter->dev)); 1059d56d301bSFrederic Barrat if (!adapter->irq_name) 1060d56d301bSFrederic Barrat return -ENOMEM; 1061d56d301bSFrederic Barrat 10622b04cf31SFrederic Barrat if ((rc = cxl_register_one_irq(adapter, native_irq_err, adapter, 1063cbffa3a5SChristophe Lombard &adapter->native->err_hwirq, 1064cbffa3a5SChristophe Lombard &adapter->native->err_virq, 1065d56d301bSFrederic Barrat adapter->irq_name))) { 1066d56d301bSFrederic Barrat kfree(adapter->irq_name); 1067d56d301bSFrederic Barrat adapter->irq_name = NULL; 1068d56d301bSFrederic Barrat return rc; 1069d56d301bSFrederic Barrat } 1070d56d301bSFrederic Barrat 1071cbffa3a5SChristophe Lombard cxl_p1_write(adapter, CXL_PSL_ErrIVTE, adapter->native->err_hwirq & 0xffff); 1072d56d301bSFrederic Barrat 1073d56d301bSFrederic Barrat return 0; 1074d56d301bSFrederic Barrat } 1075d56d301bSFrederic Barrat 10762b04cf31SFrederic Barrat void cxl_native_release_psl_err_irq(struct cxl *adapter) 1077d56d301bSFrederic Barrat { 1078cbffa3a5SChristophe Lombard if (adapter->native->err_virq != irq_find_mapping(NULL, adapter->native->err_hwirq)) 1079d56d301bSFrederic Barrat return; 1080d56d301bSFrederic Barrat 1081d56d301bSFrederic Barrat cxl_p1_write(adapter, CXL_PSL_ErrIVTE, 0x0000000000000000); 1082cbffa3a5SChristophe Lombard cxl_unmap_irq(adapter->native->err_virq, adapter); 1083cbffa3a5SChristophe Lombard cxl_ops->release_one_irq(adapter, adapter->native->err_hwirq); 1084d56d301bSFrederic Barrat kfree(adapter->irq_name); 1085d56d301bSFrederic Barrat } 1086d56d301bSFrederic Barrat 10872b04cf31SFrederic Barrat int cxl_native_register_serr_irq(struct cxl_afu *afu) 1088d56d301bSFrederic Barrat { 1089d56d301bSFrederic Barrat u64 serr; 1090d56d301bSFrederic Barrat int rc; 1091d56d301bSFrederic Barrat 1092d56d301bSFrederic Barrat afu->err_irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err", 1093d56d301bSFrederic Barrat dev_name(&afu->dev)); 1094d56d301bSFrederic Barrat if (!afu->err_irq_name) 1095d56d301bSFrederic Barrat return -ENOMEM; 1096d56d301bSFrederic Barrat 10972b04cf31SFrederic Barrat if ((rc = cxl_register_one_irq(afu->adapter, native_slice_irq_err, afu, 1098d56d301bSFrederic Barrat &afu->serr_hwirq, 1099d56d301bSFrederic Barrat &afu->serr_virq, afu->err_irq_name))) { 1100d56d301bSFrederic Barrat kfree(afu->err_irq_name); 1101d56d301bSFrederic Barrat afu->err_irq_name = NULL; 1102d56d301bSFrederic Barrat return rc; 1103d56d301bSFrederic Barrat } 1104d56d301bSFrederic Barrat 1105d56d301bSFrederic Barrat serr = cxl_p1n_read(afu, CXL_PSL_SERR_An); 1106d56d301bSFrederic Barrat serr = (serr & 0x00ffffffffff0000ULL) | (afu->serr_hwirq & 0xffff); 1107d56d301bSFrederic Barrat cxl_p1n_write(afu, CXL_PSL_SERR_An, serr); 1108d56d301bSFrederic Barrat 1109d56d301bSFrederic Barrat return 0; 1110d56d301bSFrederic Barrat } 1111d56d301bSFrederic Barrat 11122b04cf31SFrederic Barrat void cxl_native_release_serr_irq(struct cxl_afu *afu) 1113d56d301bSFrederic Barrat { 1114d56d301bSFrederic Barrat if (afu->serr_virq != irq_find_mapping(NULL, afu->serr_hwirq)) 1115d56d301bSFrederic Barrat return; 1116d56d301bSFrederic Barrat 1117d56d301bSFrederic Barrat cxl_p1n_write(afu, CXL_PSL_SERR_An, 0x0000000000000000); 1118d56d301bSFrederic Barrat cxl_unmap_irq(afu->serr_virq, afu); 11195be587b1SFrederic Barrat cxl_ops->release_one_irq(afu->adapter, afu->serr_hwirq); 1120d56d301bSFrederic Barrat kfree(afu->err_irq_name); 1121d56d301bSFrederic Barrat } 1122d56d301bSFrederic Barrat 11232b04cf31SFrederic Barrat int cxl_native_register_psl_irq(struct cxl_afu *afu) 1124d56d301bSFrederic Barrat { 1125d56d301bSFrederic Barrat int rc; 1126d56d301bSFrederic Barrat 1127d56d301bSFrederic Barrat afu->psl_irq_name = kasprintf(GFP_KERNEL, "cxl-%s", 1128d56d301bSFrederic Barrat dev_name(&afu->dev)); 1129d56d301bSFrederic Barrat if (!afu->psl_irq_name) 1130d56d301bSFrederic Barrat return -ENOMEM; 1131d56d301bSFrederic Barrat 1132cbffa3a5SChristophe Lombard if ((rc = cxl_register_one_irq(afu->adapter, native_irq_multiplexed, 1133cbffa3a5SChristophe Lombard afu, &afu->native->psl_hwirq, &afu->native->psl_virq, 1134d56d301bSFrederic Barrat afu->psl_irq_name))) { 1135d56d301bSFrederic Barrat kfree(afu->psl_irq_name); 1136d56d301bSFrederic Barrat afu->psl_irq_name = NULL; 1137d56d301bSFrederic Barrat } 1138d56d301bSFrederic Barrat return rc; 1139d56d301bSFrederic Barrat } 1140d56d301bSFrederic Barrat 11412b04cf31SFrederic Barrat void cxl_native_release_psl_irq(struct cxl_afu *afu) 1142d56d301bSFrederic Barrat { 1143cbffa3a5SChristophe Lombard if (afu->native->psl_virq != irq_find_mapping(NULL, afu->native->psl_hwirq)) 1144d56d301bSFrederic Barrat return; 1145d56d301bSFrederic Barrat 1146cbffa3a5SChristophe Lombard cxl_unmap_irq(afu->native->psl_virq, afu); 1147cbffa3a5SChristophe Lombard cxl_ops->release_one_irq(afu->adapter, afu->native->psl_hwirq); 1148d56d301bSFrederic Barrat kfree(afu->psl_irq_name); 1149d56d301bSFrederic Barrat } 1150d56d301bSFrederic Barrat 1151f204e0b8SIan Munsie static void recover_psl_err(struct cxl_afu *afu, u64 errstat) 1152f204e0b8SIan Munsie { 1153f204e0b8SIan Munsie u64 dsisr; 1154f204e0b8SIan Munsie 1155de369538SRasmus Villemoes pr_devel("RECOVERING FROM PSL ERROR... (0x%016llx)\n", errstat); 1156f204e0b8SIan Munsie 1157f204e0b8SIan Munsie /* Clear PSL_DSISR[PE] */ 1158f204e0b8SIan Munsie dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); 1159f204e0b8SIan Munsie cxl_p2n_write(afu, CXL_PSL_DSISR_An, dsisr & ~CXL_PSL_DSISR_An_PE); 1160f204e0b8SIan Munsie 1161f204e0b8SIan Munsie /* Write 1s to clear error status bits */ 1162f204e0b8SIan Munsie cxl_p2n_write(afu, CXL_PSL_ErrStat_An, errstat); 1163f204e0b8SIan Munsie } 1164f204e0b8SIan Munsie 11652b04cf31SFrederic Barrat static int native_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask) 1166f204e0b8SIan Munsie { 11679bcf28cdSIan Munsie trace_cxl_psl_irq_ack(ctx, tfc); 1168f204e0b8SIan Munsie if (tfc) 1169f204e0b8SIan Munsie cxl_p2n_write(ctx->afu, CXL_PSL_TFC_An, tfc); 1170f204e0b8SIan Munsie if (psl_reset_mask) 1171f204e0b8SIan Munsie recover_psl_err(ctx->afu, psl_reset_mask); 1172f204e0b8SIan Munsie 1173f204e0b8SIan Munsie return 0; 1174f204e0b8SIan Munsie } 1175f204e0b8SIan Munsie 1176f204e0b8SIan Munsie int cxl_check_error(struct cxl_afu *afu) 1177f204e0b8SIan Munsie { 1178f204e0b8SIan Munsie return (cxl_p1n_read(afu, CXL_PSL_SCNTL_An) == ~0ULL); 1179f204e0b8SIan Munsie } 1180d56d301bSFrederic Barrat 11814752876cSChristophe Lombard static bool native_support_attributes(const char *attr_name, 11824752876cSChristophe Lombard enum cxl_attrs type) 11834752876cSChristophe Lombard { 11844752876cSChristophe Lombard return true; 11854752876cSChristophe Lombard } 11864752876cSChristophe Lombard 11872b04cf31SFrederic Barrat static int native_afu_cr_read64(struct cxl_afu *afu, int cr, u64 off, u64 *out) 1188d56d301bSFrederic Barrat { 11890d400f77SChristophe Lombard if (unlikely(!cxl_ops->link_ok(afu->adapter, afu))) 11905be587b1SFrederic Barrat return -EIO; 11915be587b1SFrederic Barrat if (unlikely(off >= afu->crs_len)) 11925be587b1SFrederic Barrat return -ERANGE; 1193cbffa3a5SChristophe Lombard *out = in_le64(afu->native->afu_desc_mmio + afu->crs_offset + 11945be587b1SFrederic Barrat (cr * afu->crs_len) + off); 11955be587b1SFrederic Barrat return 0; 1196d56d301bSFrederic Barrat } 1197d56d301bSFrederic Barrat 11982b04cf31SFrederic Barrat static int native_afu_cr_read32(struct cxl_afu *afu, int cr, u64 off, u32 *out) 1199d56d301bSFrederic Barrat { 12000d400f77SChristophe Lombard if (unlikely(!cxl_ops->link_ok(afu->adapter, afu))) 12015be587b1SFrederic Barrat return -EIO; 12025be587b1SFrederic Barrat if (unlikely(off >= afu->crs_len)) 12035be587b1SFrederic Barrat return -ERANGE; 1204cbffa3a5SChristophe Lombard *out = in_le32(afu->native->afu_desc_mmio + afu->crs_offset + 12055be587b1SFrederic Barrat (cr * afu->crs_len) + off); 12065be587b1SFrederic Barrat return 0; 1207d56d301bSFrederic Barrat } 1208d56d301bSFrederic Barrat 12092b04cf31SFrederic Barrat static int native_afu_cr_read16(struct cxl_afu *afu, int cr, u64 off, u16 *out) 1210d56d301bSFrederic Barrat { 1211d56d301bSFrederic Barrat u64 aligned_off = off & ~0x3L; 1212d56d301bSFrederic Barrat u32 val; 12135be587b1SFrederic Barrat int rc; 1214d56d301bSFrederic Barrat 12152b04cf31SFrederic Barrat rc = native_afu_cr_read32(afu, cr, aligned_off, &val); 12165be587b1SFrederic Barrat if (!rc) 12175be587b1SFrederic Barrat *out = (val >> ((off & 0x3) * 8)) & 0xffff; 12185be587b1SFrederic Barrat return rc; 1219d56d301bSFrederic Barrat } 1220d56d301bSFrederic Barrat 12212b04cf31SFrederic Barrat static int native_afu_cr_read8(struct cxl_afu *afu, int cr, u64 off, u8 *out) 1222d56d301bSFrederic Barrat { 1223d56d301bSFrederic Barrat u64 aligned_off = off & ~0x3L; 1224d56d301bSFrederic Barrat u32 val; 12255be587b1SFrederic Barrat int rc; 1226d56d301bSFrederic Barrat 12272b04cf31SFrederic Barrat rc = native_afu_cr_read32(afu, cr, aligned_off, &val); 12285be587b1SFrederic Barrat if (!rc) 12295be587b1SFrederic Barrat *out = (val >> ((off & 0x3) * 8)) & 0xff; 12305be587b1SFrederic Barrat return rc; 1231d56d301bSFrederic Barrat } 12325be587b1SFrederic Barrat 1233d601ea91SFrederic Barrat static int native_afu_cr_write32(struct cxl_afu *afu, int cr, u64 off, u32 in) 1234d601ea91SFrederic Barrat { 12350d400f77SChristophe Lombard if (unlikely(!cxl_ops->link_ok(afu->adapter, afu))) 1236d601ea91SFrederic Barrat return -EIO; 1237d601ea91SFrederic Barrat if (unlikely(off >= afu->crs_len)) 1238d601ea91SFrederic Barrat return -ERANGE; 1239d601ea91SFrederic Barrat out_le32(afu->native->afu_desc_mmio + afu->crs_offset + 1240d601ea91SFrederic Barrat (cr * afu->crs_len) + off, in); 1241d601ea91SFrederic Barrat return 0; 1242d601ea91SFrederic Barrat } 1243d601ea91SFrederic Barrat 1244d601ea91SFrederic Barrat static int native_afu_cr_write16(struct cxl_afu *afu, int cr, u64 off, u16 in) 1245d601ea91SFrederic Barrat { 1246d601ea91SFrederic Barrat u64 aligned_off = off & ~0x3L; 1247d601ea91SFrederic Barrat u32 val32, mask, shift; 1248d601ea91SFrederic Barrat int rc; 1249d601ea91SFrederic Barrat 1250d601ea91SFrederic Barrat rc = native_afu_cr_read32(afu, cr, aligned_off, &val32); 1251d601ea91SFrederic Barrat if (rc) 1252d601ea91SFrederic Barrat return rc; 1253d601ea91SFrederic Barrat shift = (off & 0x3) * 8; 1254d601ea91SFrederic Barrat WARN_ON(shift == 24); 1255d601ea91SFrederic Barrat mask = 0xffff << shift; 1256d601ea91SFrederic Barrat val32 = (val32 & ~mask) | (in << shift); 1257d601ea91SFrederic Barrat 1258d601ea91SFrederic Barrat rc = native_afu_cr_write32(afu, cr, aligned_off, val32); 1259d601ea91SFrederic Barrat return rc; 1260d601ea91SFrederic Barrat } 1261d601ea91SFrederic Barrat 1262d601ea91SFrederic Barrat static int native_afu_cr_write8(struct cxl_afu *afu, int cr, u64 off, u8 in) 1263d601ea91SFrederic Barrat { 1264d601ea91SFrederic Barrat u64 aligned_off = off & ~0x3L; 1265d601ea91SFrederic Barrat u32 val32, mask, shift; 1266d601ea91SFrederic Barrat int rc; 1267d601ea91SFrederic Barrat 1268d601ea91SFrederic Barrat rc = native_afu_cr_read32(afu, cr, aligned_off, &val32); 1269d601ea91SFrederic Barrat if (rc) 1270d601ea91SFrederic Barrat return rc; 1271d601ea91SFrederic Barrat shift = (off & 0x3) * 8; 1272d601ea91SFrederic Barrat mask = 0xff << shift; 1273d601ea91SFrederic Barrat val32 = (val32 & ~mask) | (in << shift); 1274d601ea91SFrederic Barrat 1275d601ea91SFrederic Barrat rc = native_afu_cr_write32(afu, cr, aligned_off, val32); 1276d601ea91SFrederic Barrat return rc; 1277d601ea91SFrederic Barrat } 1278d601ea91SFrederic Barrat 12795be587b1SFrederic Barrat const struct cxl_backend_ops cxl_native_ops = { 12805be587b1SFrederic Barrat .module = THIS_MODULE, 12812b04cf31SFrederic Barrat .adapter_reset = cxl_pci_reset, 12822b04cf31SFrederic Barrat .alloc_one_irq = cxl_pci_alloc_one_irq, 12832b04cf31SFrederic Barrat .release_one_irq = cxl_pci_release_one_irq, 12842b04cf31SFrederic Barrat .alloc_irq_ranges = cxl_pci_alloc_irq_ranges, 12852b04cf31SFrederic Barrat .release_irq_ranges = cxl_pci_release_irq_ranges, 12862b04cf31SFrederic Barrat .setup_irq = cxl_pci_setup_irq, 12872b04cf31SFrederic Barrat .handle_psl_slice_error = native_handle_psl_slice_error, 12885be587b1SFrederic Barrat .psl_interrupt = NULL, 12892b04cf31SFrederic Barrat .ack_irq = native_ack_irq, 12902bc79ffcSMichael Neuling .irq_wait = native_irq_wait, 12912b04cf31SFrederic Barrat .attach_process = native_attach_process, 12922b04cf31SFrederic Barrat .detach_process = native_detach_process, 1293292841b0SIan Munsie .update_ivtes = native_update_ivtes, 12944752876cSChristophe Lombard .support_attributes = native_support_attributes, 12955be587b1SFrederic Barrat .link_ok = cxl_adapter_link_ok, 12962b04cf31SFrederic Barrat .release_afu = cxl_pci_release_afu, 12972b04cf31SFrederic Barrat .afu_read_err_buffer = cxl_pci_afu_read_err_buffer, 12982b04cf31SFrederic Barrat .afu_check_and_enable = native_afu_check_and_enable, 12992b04cf31SFrederic Barrat .afu_activate_mode = native_afu_activate_mode, 13002b04cf31SFrederic Barrat .afu_deactivate_mode = native_afu_deactivate_mode, 13012b04cf31SFrederic Barrat .afu_reset = native_afu_reset, 13022b04cf31SFrederic Barrat .afu_cr_read8 = native_afu_cr_read8, 13032b04cf31SFrederic Barrat .afu_cr_read16 = native_afu_cr_read16, 13042b04cf31SFrederic Barrat .afu_cr_read32 = native_afu_cr_read32, 13052b04cf31SFrederic Barrat .afu_cr_read64 = native_afu_cr_read64, 1306d601ea91SFrederic Barrat .afu_cr_write8 = native_afu_cr_write8, 1307d601ea91SFrederic Barrat .afu_cr_write16 = native_afu_cr_write16, 1308d601ea91SFrederic Barrat .afu_cr_write32 = native_afu_cr_write32, 1309d601ea91SFrederic Barrat .read_adapter_vpd = cxl_pci_read_adapter_vpd, 13105be587b1SFrederic Barrat }; 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