1f204e0b8SIan Munsie /* 2f204e0b8SIan Munsie * Copyright 2014 IBM Corp. 3f204e0b8SIan Munsie * 4f204e0b8SIan Munsie * This program is free software; you can redistribute it and/or 5f204e0b8SIan Munsie * modify it under the terms of the GNU General Public License 6f204e0b8SIan Munsie * as published by the Free Software Foundation; either version 7f204e0b8SIan Munsie * 2 of the License, or (at your option) any later version. 8f204e0b8SIan Munsie */ 9f204e0b8SIan Munsie 10f204e0b8SIan Munsie #include <linux/spinlock.h> 11f204e0b8SIan Munsie #include <linux/sched.h> 12f204e0b8SIan Munsie #include <linux/slab.h> 13f204e0b8SIan Munsie #include <linux/sched.h> 14f204e0b8SIan Munsie #include <linux/mutex.h> 15f204e0b8SIan Munsie #include <linux/mm.h> 16f204e0b8SIan Munsie #include <linux/uaccess.h> 172bc79ffcSMichael Neuling #include <linux/delay.h> 18f204e0b8SIan Munsie #include <asm/synch.h> 19ec249dd8SMichael Neuling #include <misc/cxl-base.h> 20f204e0b8SIan Munsie 21f204e0b8SIan Munsie #include "cxl.h" 229bcf28cdSIan Munsie #include "trace.h" 23f204e0b8SIan Munsie 245e7823c9SIan Munsie static int afu_control(struct cxl_afu *afu, u64 command, u64 clear, 25f204e0b8SIan Munsie u64 result, u64 mask, bool enabled) 26f204e0b8SIan Munsie { 275e7823c9SIan Munsie u64 AFU_Cntl; 28f204e0b8SIan Munsie unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); 299bcf28cdSIan Munsie int rc = 0; 30f204e0b8SIan Munsie 31f204e0b8SIan Munsie spin_lock(&afu->afu_cntl_lock); 32f204e0b8SIan Munsie pr_devel("AFU command starting: %llx\n", command); 33f204e0b8SIan Munsie 349bcf28cdSIan Munsie trace_cxl_afu_ctrl(afu, command); 359bcf28cdSIan Munsie 365e7823c9SIan Munsie AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); 375e7823c9SIan Munsie cxl_p2n_write(afu, CXL_AFU_Cntl_An, (AFU_Cntl & ~clear) | command); 38f204e0b8SIan Munsie 39f204e0b8SIan Munsie AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); 40f204e0b8SIan Munsie while ((AFU_Cntl & mask) != result) { 41f204e0b8SIan Munsie if (time_after_eq(jiffies, timeout)) { 42f204e0b8SIan Munsie dev_warn(&afu->dev, "WARNING: AFU control timed out!\n"); 439bcf28cdSIan Munsie rc = -EBUSY; 449bcf28cdSIan Munsie goto out; 45f204e0b8SIan Munsie } 460b3f9c75SDaniel Axtens 470d400f77SChristophe Lombard if (!cxl_ops->link_ok(afu->adapter, afu)) { 480b3f9c75SDaniel Axtens afu->enabled = enabled; 490b3f9c75SDaniel Axtens rc = -EIO; 500b3f9c75SDaniel Axtens goto out; 510b3f9c75SDaniel Axtens } 520b3f9c75SDaniel Axtens 53de369538SRasmus Villemoes pr_devel_ratelimited("AFU control... (0x%016llx)\n", 54f204e0b8SIan Munsie AFU_Cntl | command); 55f204e0b8SIan Munsie cpu_relax(); 56f204e0b8SIan Munsie AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); 57f204e0b8SIan Munsie }; 582a4f667aSIan Munsie 592a4f667aSIan Munsie if (AFU_Cntl & CXL_AFU_Cntl_An_RA) { 602a4f667aSIan Munsie /* 612a4f667aSIan Munsie * Workaround for a bug in the XSL used in the Mellanox CX4 622a4f667aSIan Munsie * that fails to clear the RA bit after an AFU reset, 632a4f667aSIan Munsie * preventing subsequent AFU resets from working. 642a4f667aSIan Munsie */ 652a4f667aSIan Munsie cxl_p2n_write(afu, CXL_AFU_Cntl_An, AFU_Cntl & ~CXL_AFU_Cntl_An_RA); 662a4f667aSIan Munsie } 672a4f667aSIan Munsie 68f204e0b8SIan Munsie pr_devel("AFU command complete: %llx\n", command); 69f204e0b8SIan Munsie afu->enabled = enabled; 709bcf28cdSIan Munsie out: 719bcf28cdSIan Munsie trace_cxl_afu_ctrl_done(afu, command, rc); 72f204e0b8SIan Munsie spin_unlock(&afu->afu_cntl_lock); 73f204e0b8SIan Munsie 749bcf28cdSIan Munsie return rc; 75f204e0b8SIan Munsie } 76f204e0b8SIan Munsie 77f204e0b8SIan Munsie static int afu_enable(struct cxl_afu *afu) 78f204e0b8SIan Munsie { 79f204e0b8SIan Munsie pr_devel("AFU enable request\n"); 80f204e0b8SIan Munsie 815e7823c9SIan Munsie return afu_control(afu, CXL_AFU_Cntl_An_E, 0, 82f204e0b8SIan Munsie CXL_AFU_Cntl_An_ES_Enabled, 83f204e0b8SIan Munsie CXL_AFU_Cntl_An_ES_MASK, true); 84f204e0b8SIan Munsie } 85f204e0b8SIan Munsie 86f204e0b8SIan Munsie int cxl_afu_disable(struct cxl_afu *afu) 87f204e0b8SIan Munsie { 88f204e0b8SIan Munsie pr_devel("AFU disable request\n"); 89f204e0b8SIan Munsie 905e7823c9SIan Munsie return afu_control(afu, 0, CXL_AFU_Cntl_An_E, 915e7823c9SIan Munsie CXL_AFU_Cntl_An_ES_Disabled, 92f204e0b8SIan Munsie CXL_AFU_Cntl_An_ES_MASK, false); 93f204e0b8SIan Munsie } 94f204e0b8SIan Munsie 95f204e0b8SIan Munsie /* This will disable as well as reset */ 962b04cf31SFrederic Barrat static int native_afu_reset(struct cxl_afu *afu) 97f204e0b8SIan Munsie { 98f204e0b8SIan Munsie pr_devel("AFU reset request\n"); 99f204e0b8SIan Munsie 1005e7823c9SIan Munsie return afu_control(afu, CXL_AFU_Cntl_An_RA, 0, 101f204e0b8SIan Munsie CXL_AFU_Cntl_An_RS_Complete | CXL_AFU_Cntl_An_ES_Disabled, 102f204e0b8SIan Munsie CXL_AFU_Cntl_An_RS_MASK | CXL_AFU_Cntl_An_ES_MASK, 103f204e0b8SIan Munsie false); 104f204e0b8SIan Munsie } 105f204e0b8SIan Munsie 1062b04cf31SFrederic Barrat static int native_afu_check_and_enable(struct cxl_afu *afu) 107f204e0b8SIan Munsie { 1080d400f77SChristophe Lombard if (!cxl_ops->link_ok(afu->adapter, afu)) { 1090b3f9c75SDaniel Axtens WARN(1, "Refusing to enable afu while link down!\n"); 1100b3f9c75SDaniel Axtens return -EIO; 1110b3f9c75SDaniel Axtens } 112f204e0b8SIan Munsie if (afu->enabled) 113f204e0b8SIan Munsie return 0; 114f204e0b8SIan Munsie return afu_enable(afu); 115f204e0b8SIan Munsie } 116f204e0b8SIan Munsie 117f204e0b8SIan Munsie int cxl_psl_purge(struct cxl_afu *afu) 118f204e0b8SIan Munsie { 119f204e0b8SIan Munsie u64 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); 120f204e0b8SIan Munsie u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); 121f204e0b8SIan Munsie u64 dsisr, dar; 122f204e0b8SIan Munsie u64 start, end; 123f204e0b8SIan Munsie unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); 1249bcf28cdSIan Munsie int rc = 0; 1259bcf28cdSIan Munsie 1269bcf28cdSIan Munsie trace_cxl_psl_ctrl(afu, CXL_PSL_SCNTL_An_Pc); 127f204e0b8SIan Munsie 128f204e0b8SIan Munsie pr_devel("PSL purge request\n"); 129f204e0b8SIan Munsie 1300d400f77SChristophe Lombard if (!cxl_ops->link_ok(afu->adapter, afu)) { 1310b3f9c75SDaniel Axtens dev_warn(&afu->dev, "PSL Purge called with link down, ignoring\n"); 1320b3f9c75SDaniel Axtens rc = -EIO; 1330b3f9c75SDaniel Axtens goto out; 1340b3f9c75SDaniel Axtens } 1350b3f9c75SDaniel Axtens 136f204e0b8SIan Munsie if ((AFU_Cntl & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) { 137f204e0b8SIan Munsie WARN(1, "psl_purge request while AFU not disabled!\n"); 138f204e0b8SIan Munsie cxl_afu_disable(afu); 139f204e0b8SIan Munsie } 140f204e0b8SIan Munsie 141f204e0b8SIan Munsie cxl_p1n_write(afu, CXL_PSL_SCNTL_An, 142f204e0b8SIan Munsie PSL_CNTL | CXL_PSL_SCNTL_An_Pc); 143f204e0b8SIan Munsie start = local_clock(); 144f204e0b8SIan Munsie PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); 145f204e0b8SIan Munsie while ((PSL_CNTL & CXL_PSL_SCNTL_An_Ps_MASK) 146f204e0b8SIan Munsie == CXL_PSL_SCNTL_An_Ps_Pending) { 147f204e0b8SIan Munsie if (time_after_eq(jiffies, timeout)) { 148f204e0b8SIan Munsie dev_warn(&afu->dev, "WARNING: PSL Purge timed out!\n"); 1499bcf28cdSIan Munsie rc = -EBUSY; 1509bcf28cdSIan Munsie goto out; 151f204e0b8SIan Munsie } 1520d400f77SChristophe Lombard if (!cxl_ops->link_ok(afu->adapter, afu)) { 1530b3f9c75SDaniel Axtens rc = -EIO; 1540b3f9c75SDaniel Axtens goto out; 1550b3f9c75SDaniel Axtens } 1560b3f9c75SDaniel Axtens 157f204e0b8SIan Munsie dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); 158de369538SRasmus Villemoes pr_devel_ratelimited("PSL purging... PSL_CNTL: 0x%016llx PSL_DSISR: 0x%016llx\n", PSL_CNTL, dsisr); 159f204e0b8SIan Munsie if (dsisr & CXL_PSL_DSISR_TRANS) { 160f204e0b8SIan Munsie dar = cxl_p2n_read(afu, CXL_PSL_DAR_An); 161de369538SRasmus Villemoes dev_notice(&afu->dev, "PSL purge terminating pending translation, DSISR: 0x%016llx, DAR: 0x%016llx\n", dsisr, dar); 162f204e0b8SIan Munsie cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); 163f204e0b8SIan Munsie } else if (dsisr) { 164de369538SRasmus Villemoes dev_notice(&afu->dev, "PSL purge acknowledging pending non-translation fault, DSISR: 0x%016llx\n", dsisr); 165f204e0b8SIan Munsie cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); 166f204e0b8SIan Munsie } else { 167f204e0b8SIan Munsie cpu_relax(); 168f204e0b8SIan Munsie } 169f204e0b8SIan Munsie PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); 170f204e0b8SIan Munsie }; 171f204e0b8SIan Munsie end = local_clock(); 172f204e0b8SIan Munsie pr_devel("PSL purged in %lld ns\n", end - start); 173f204e0b8SIan Munsie 174f204e0b8SIan Munsie cxl_p1n_write(afu, CXL_PSL_SCNTL_An, 175f204e0b8SIan Munsie PSL_CNTL & ~CXL_PSL_SCNTL_An_Pc); 1769bcf28cdSIan Munsie out: 1779bcf28cdSIan Munsie trace_cxl_psl_ctrl_done(afu, CXL_PSL_SCNTL_An_Pc, rc); 1789bcf28cdSIan Munsie return rc; 179f204e0b8SIan Munsie } 180f204e0b8SIan Munsie 181f204e0b8SIan Munsie static int spa_max_procs(int spa_size) 182f204e0b8SIan Munsie { 183f204e0b8SIan Munsie /* 184f204e0b8SIan Munsie * From the CAIA: 185f204e0b8SIan Munsie * end_of_SPA_area = SPA_Base + ((n+4) * 128) + (( ((n*8) + 127) >> 7) * 128) + 255 186f204e0b8SIan Munsie * Most of that junk is really just an overly-complicated way of saying 187f204e0b8SIan Munsie * the last 256 bytes are __aligned(128), so it's really: 188f204e0b8SIan Munsie * end_of_SPA_area = end_of_PSL_queue_area + __aligned(128) 255 189f204e0b8SIan Munsie * and 190f204e0b8SIan Munsie * end_of_PSL_queue_area = SPA_Base + ((n+4) * 128) + (n*8) - 1 191f204e0b8SIan Munsie * so 192f204e0b8SIan Munsie * sizeof(SPA) = ((n+4) * 128) + (n*8) + __aligned(128) 256 193f204e0b8SIan Munsie * Ignore the alignment (which is safe in this case as long as we are 194f204e0b8SIan Munsie * careful with our rounding) and solve for n: 195f204e0b8SIan Munsie */ 196f204e0b8SIan Munsie return ((spa_size / 8) - 96) / 17; 197f204e0b8SIan Munsie } 198f204e0b8SIan Munsie 19905155772SDaniel Axtens int cxl_alloc_spa(struct cxl_afu *afu) 200f204e0b8SIan Munsie { 201895a7980SIan Munsie unsigned spa_size; 202895a7980SIan Munsie 203f204e0b8SIan Munsie /* Work out how many pages to allocate */ 2042224b671SIan Munsie afu->native->spa_order = -1; 205f204e0b8SIan Munsie do { 206cbffa3a5SChristophe Lombard afu->native->spa_order++; 207895a7980SIan Munsie spa_size = (1 << afu->native->spa_order) * PAGE_SIZE; 208895a7980SIan Munsie 209895a7980SIan Munsie if (spa_size > 0x100000) { 210895a7980SIan Munsie dev_warn(&afu->dev, "num_of_processes too large for the SPA, limiting to %i (0x%x)\n", 211895a7980SIan Munsie afu->native->spa_max_procs, afu->native->spa_size); 212895a7980SIan Munsie afu->num_procs = afu->native->spa_max_procs; 213895a7980SIan Munsie break; 214895a7980SIan Munsie } 215895a7980SIan Munsie 216895a7980SIan Munsie afu->native->spa_size = spa_size; 217cbffa3a5SChristophe Lombard afu->native->spa_max_procs = spa_max_procs(afu->native->spa_size); 218cbffa3a5SChristophe Lombard } while (afu->native->spa_max_procs < afu->num_procs); 219f204e0b8SIan Munsie 220cbffa3a5SChristophe Lombard if (!(afu->native->spa = (struct cxl_process_element *) 221cbffa3a5SChristophe Lombard __get_free_pages(GFP_KERNEL | __GFP_ZERO, afu->native->spa_order))) { 222f204e0b8SIan Munsie pr_err("cxl_alloc_spa: Unable to allocate scheduled process area\n"); 223f204e0b8SIan Munsie return -ENOMEM; 224f204e0b8SIan Munsie } 225f204e0b8SIan Munsie pr_devel("spa pages: %i afu->spa_max_procs: %i afu->num_procs: %i\n", 226cbffa3a5SChristophe Lombard 1<<afu->native->spa_order, afu->native->spa_max_procs, afu->num_procs); 227f204e0b8SIan Munsie 22805155772SDaniel Axtens return 0; 22905155772SDaniel Axtens } 23005155772SDaniel Axtens 23105155772SDaniel Axtens static void attach_spa(struct cxl_afu *afu) 23205155772SDaniel Axtens { 23305155772SDaniel Axtens u64 spap; 23405155772SDaniel Axtens 235cbffa3a5SChristophe Lombard afu->native->sw_command_status = (__be64 *)((char *)afu->native->spa + 236cbffa3a5SChristophe Lombard ((afu->native->spa_max_procs + 3) * 128)); 237f204e0b8SIan Munsie 238cbffa3a5SChristophe Lombard spap = virt_to_phys(afu->native->spa) & CXL_PSL_SPAP_Addr; 239cbffa3a5SChristophe Lombard spap |= ((afu->native->spa_size >> (12 - CXL_PSL_SPAP_Size_Shift)) - 1) & CXL_PSL_SPAP_Size; 240f204e0b8SIan Munsie spap |= CXL_PSL_SPAP_V; 241cbffa3a5SChristophe Lombard pr_devel("cxl: SPA allocated at 0x%p. Max processes: %i, sw_command_status: 0x%p CXL_PSL_SPAP_An=0x%016llx\n", 242cbffa3a5SChristophe Lombard afu->native->spa, afu->native->spa_max_procs, 243cbffa3a5SChristophe Lombard afu->native->sw_command_status, spap); 244f204e0b8SIan Munsie cxl_p1n_write(afu, CXL_PSL_SPAP_An, spap); 245f204e0b8SIan Munsie } 246f204e0b8SIan Munsie 24705155772SDaniel Axtens static inline void detach_spa(struct cxl_afu *afu) 248f204e0b8SIan Munsie { 249db7933f3SIan Munsie cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); 25005155772SDaniel Axtens } 25105155772SDaniel Axtens 25205155772SDaniel Axtens void cxl_release_spa(struct cxl_afu *afu) 25305155772SDaniel Axtens { 254cbffa3a5SChristophe Lombard if (afu->native->spa) { 255cbffa3a5SChristophe Lombard free_pages((unsigned long) afu->native->spa, 256cbffa3a5SChristophe Lombard afu->native->spa_order); 257cbffa3a5SChristophe Lombard afu->native->spa = NULL; 25805155772SDaniel Axtens } 259f204e0b8SIan Munsie } 260f204e0b8SIan Munsie 261f204e0b8SIan Munsie int cxl_tlb_slb_invalidate(struct cxl *adapter) 262f204e0b8SIan Munsie { 263f204e0b8SIan Munsie unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); 264f204e0b8SIan Munsie 265f204e0b8SIan Munsie pr_devel("CXL adapter wide TLBIA & SLBIA\n"); 266f204e0b8SIan Munsie 267f204e0b8SIan Munsie cxl_p1_write(adapter, CXL_PSL_AFUSEL, CXL_PSL_AFUSEL_A); 268f204e0b8SIan Munsie 269f204e0b8SIan Munsie cxl_p1_write(adapter, CXL_PSL_TLBIA, CXL_TLB_SLB_IQ_ALL); 270f204e0b8SIan Munsie while (cxl_p1_read(adapter, CXL_PSL_TLBIA) & CXL_TLB_SLB_P) { 271f204e0b8SIan Munsie if (time_after_eq(jiffies, timeout)) { 272f204e0b8SIan Munsie dev_warn(&adapter->dev, "WARNING: CXL adapter wide TLBIA timed out!\n"); 273f204e0b8SIan Munsie return -EBUSY; 274f204e0b8SIan Munsie } 2750d400f77SChristophe Lombard if (!cxl_ops->link_ok(adapter, NULL)) 2760b3f9c75SDaniel Axtens return -EIO; 277f204e0b8SIan Munsie cpu_relax(); 278f204e0b8SIan Munsie } 279f204e0b8SIan Munsie 280f204e0b8SIan Munsie cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_ALL); 281f204e0b8SIan Munsie while (cxl_p1_read(adapter, CXL_PSL_SLBIA) & CXL_TLB_SLB_P) { 282f204e0b8SIan Munsie if (time_after_eq(jiffies, timeout)) { 283f204e0b8SIan Munsie dev_warn(&adapter->dev, "WARNING: CXL adapter wide SLBIA timed out!\n"); 284f204e0b8SIan Munsie return -EBUSY; 285f204e0b8SIan Munsie } 2860d400f77SChristophe Lombard if (!cxl_ops->link_ok(adapter, NULL)) 2870b3f9c75SDaniel Axtens return -EIO; 288f204e0b8SIan Munsie cpu_relax(); 289f204e0b8SIan Munsie } 290f204e0b8SIan Munsie return 0; 291f204e0b8SIan Munsie } 292f204e0b8SIan Munsie 293f204e0b8SIan Munsie static int cxl_write_sstp(struct cxl_afu *afu, u64 sstp0, u64 sstp1) 294f204e0b8SIan Munsie { 295f204e0b8SIan Munsie int rc; 296f204e0b8SIan Munsie 297f204e0b8SIan Munsie /* 1. Disable SSTP by writing 0 to SSTP1[V] */ 298f204e0b8SIan Munsie cxl_p2n_write(afu, CXL_SSTP1_An, 0); 299f204e0b8SIan Munsie 300f204e0b8SIan Munsie /* 2. Invalidate all SLB entries */ 301f204e0b8SIan Munsie if ((rc = cxl_afu_slbia(afu))) 302f204e0b8SIan Munsie return rc; 303f204e0b8SIan Munsie 304f204e0b8SIan Munsie /* 3. Set SSTP0_An */ 305f204e0b8SIan Munsie cxl_p2n_write(afu, CXL_SSTP0_An, sstp0); 306f204e0b8SIan Munsie 307f204e0b8SIan Munsie /* 4. Set SSTP1_An */ 308f204e0b8SIan Munsie cxl_p2n_write(afu, CXL_SSTP1_An, sstp1); 309f204e0b8SIan Munsie 310f204e0b8SIan Munsie return 0; 311f204e0b8SIan Munsie } 312f204e0b8SIan Munsie 313f204e0b8SIan Munsie /* Using per slice version may improve performance here. (ie. SLBIA_An) */ 314f204e0b8SIan Munsie static void slb_invalid(struct cxl_context *ctx) 315f204e0b8SIan Munsie { 316f204e0b8SIan Munsie struct cxl *adapter = ctx->afu->adapter; 317f204e0b8SIan Munsie u64 slbia; 318f204e0b8SIan Munsie 319cbffa3a5SChristophe Lombard WARN_ON(!mutex_is_locked(&ctx->afu->native->spa_mutex)); 320f204e0b8SIan Munsie 321f204e0b8SIan Munsie cxl_p1_write(adapter, CXL_PSL_LBISEL, 322f204e0b8SIan Munsie ((u64)be32_to_cpu(ctx->elem->common.pid) << 32) | 323f204e0b8SIan Munsie be32_to_cpu(ctx->elem->lpid)); 324f204e0b8SIan Munsie cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_LPIDPID); 325f204e0b8SIan Munsie 326f204e0b8SIan Munsie while (1) { 3270d400f77SChristophe Lombard if (!cxl_ops->link_ok(adapter, NULL)) 3280b3f9c75SDaniel Axtens break; 329f204e0b8SIan Munsie slbia = cxl_p1_read(adapter, CXL_PSL_SLBIA); 330f204e0b8SIan Munsie if (!(slbia & CXL_TLB_SLB_P)) 331f204e0b8SIan Munsie break; 332f204e0b8SIan Munsie cpu_relax(); 333f204e0b8SIan Munsie } 334f204e0b8SIan Munsie } 335f204e0b8SIan Munsie 336f204e0b8SIan Munsie static int do_process_element_cmd(struct cxl_context *ctx, 337f204e0b8SIan Munsie u64 cmd, u64 pe_state) 338f204e0b8SIan Munsie { 339f204e0b8SIan Munsie u64 state; 340a98e6e9fSIan Munsie unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); 3419bcf28cdSIan Munsie int rc = 0; 3429bcf28cdSIan Munsie 3439bcf28cdSIan Munsie trace_cxl_llcmd(ctx, cmd); 344f204e0b8SIan Munsie 345f204e0b8SIan Munsie WARN_ON(!ctx->afu->enabled); 346f204e0b8SIan Munsie 347f204e0b8SIan Munsie ctx->elem->software_state = cpu_to_be32(pe_state); 348f204e0b8SIan Munsie smp_wmb(); 349cbffa3a5SChristophe Lombard *(ctx->afu->native->sw_command_status) = cpu_to_be64(cmd | 0 | ctx->pe); 350f204e0b8SIan Munsie smp_mb(); 351f204e0b8SIan Munsie cxl_p1n_write(ctx->afu, CXL_PSL_LLCMD_An, cmd | ctx->pe); 352f204e0b8SIan Munsie while (1) { 353a98e6e9fSIan Munsie if (time_after_eq(jiffies, timeout)) { 354a98e6e9fSIan Munsie dev_warn(&ctx->afu->dev, "WARNING: Process Element Command timed out!\n"); 3559bcf28cdSIan Munsie rc = -EBUSY; 3569bcf28cdSIan Munsie goto out; 357a98e6e9fSIan Munsie } 3580d400f77SChristophe Lombard if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) { 3590b3f9c75SDaniel Axtens dev_warn(&ctx->afu->dev, "WARNING: Device link down, aborting Process Element Command!\n"); 3600b3f9c75SDaniel Axtens rc = -EIO; 3610b3f9c75SDaniel Axtens goto out; 3620b3f9c75SDaniel Axtens } 363cbffa3a5SChristophe Lombard state = be64_to_cpup(ctx->afu->native->sw_command_status); 364f204e0b8SIan Munsie if (state == ~0ULL) { 365f204e0b8SIan Munsie pr_err("cxl: Error adding process element to AFU\n"); 3669bcf28cdSIan Munsie rc = -1; 3679bcf28cdSIan Munsie goto out; 368f204e0b8SIan Munsie } 369f204e0b8SIan Munsie if ((state & (CXL_SPA_SW_CMD_MASK | CXL_SPA_SW_STATE_MASK | CXL_SPA_SW_LINK_MASK)) == 370f204e0b8SIan Munsie (cmd | (cmd >> 16) | ctx->pe)) 371f204e0b8SIan Munsie break; 372f204e0b8SIan Munsie /* 373f204e0b8SIan Munsie * The command won't finish in the PSL if there are 374f204e0b8SIan Munsie * outstanding DSIs. Hence we need to yield here in 375f204e0b8SIan Munsie * case there are outstanding DSIs that we need to 376f204e0b8SIan Munsie * service. Tuning possiblity: we could wait for a 377f204e0b8SIan Munsie * while before sched 378f204e0b8SIan Munsie */ 379f204e0b8SIan Munsie schedule(); 380f204e0b8SIan Munsie 381f204e0b8SIan Munsie } 3829bcf28cdSIan Munsie out: 3839bcf28cdSIan Munsie trace_cxl_llcmd_done(ctx, cmd, rc); 3849bcf28cdSIan Munsie return rc; 385f204e0b8SIan Munsie } 386f204e0b8SIan Munsie 387f204e0b8SIan Munsie static int add_process_element(struct cxl_context *ctx) 388f204e0b8SIan Munsie { 389f204e0b8SIan Munsie int rc = 0; 390f204e0b8SIan Munsie 391cbffa3a5SChristophe Lombard mutex_lock(&ctx->afu->native->spa_mutex); 392f204e0b8SIan Munsie pr_devel("%s Adding pe: %i started\n", __func__, ctx->pe); 393f204e0b8SIan Munsie if (!(rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_ADD, CXL_PE_SOFTWARE_STATE_V))) 394f204e0b8SIan Munsie ctx->pe_inserted = true; 395f204e0b8SIan Munsie pr_devel("%s Adding pe: %i finished\n", __func__, ctx->pe); 396cbffa3a5SChristophe Lombard mutex_unlock(&ctx->afu->native->spa_mutex); 397f204e0b8SIan Munsie return rc; 398f204e0b8SIan Munsie } 399f204e0b8SIan Munsie 400f204e0b8SIan Munsie static int terminate_process_element(struct cxl_context *ctx) 401f204e0b8SIan Munsie { 402f204e0b8SIan Munsie int rc = 0; 403f204e0b8SIan Munsie 404f204e0b8SIan Munsie /* fast path terminate if it's already invalid */ 405f204e0b8SIan Munsie if (!(ctx->elem->software_state & cpu_to_be32(CXL_PE_SOFTWARE_STATE_V))) 406f204e0b8SIan Munsie return rc; 407f204e0b8SIan Munsie 408cbffa3a5SChristophe Lombard mutex_lock(&ctx->afu->native->spa_mutex); 409f204e0b8SIan Munsie pr_devel("%s Terminate pe: %i started\n", __func__, ctx->pe); 4100b3f9c75SDaniel Axtens /* We could be asked to terminate when the hw is down. That 4110b3f9c75SDaniel Axtens * should always succeed: it's not running if the hw has gone 4120b3f9c75SDaniel Axtens * away and is being reset. 4130b3f9c75SDaniel Axtens */ 4140d400f77SChristophe Lombard if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) 415f204e0b8SIan Munsie rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_TERMINATE, 416f204e0b8SIan Munsie CXL_PE_SOFTWARE_STATE_V | CXL_PE_SOFTWARE_STATE_T); 417f204e0b8SIan Munsie ctx->elem->software_state = 0; /* Remove Valid bit */ 418f204e0b8SIan Munsie pr_devel("%s Terminate pe: %i finished\n", __func__, ctx->pe); 419cbffa3a5SChristophe Lombard mutex_unlock(&ctx->afu->native->spa_mutex); 420f204e0b8SIan Munsie return rc; 421f204e0b8SIan Munsie } 422f204e0b8SIan Munsie 423f204e0b8SIan Munsie static int remove_process_element(struct cxl_context *ctx) 424f204e0b8SIan Munsie { 425f204e0b8SIan Munsie int rc = 0; 426f204e0b8SIan Munsie 427cbffa3a5SChristophe Lombard mutex_lock(&ctx->afu->native->spa_mutex); 428f204e0b8SIan Munsie pr_devel("%s Remove pe: %i started\n", __func__, ctx->pe); 4290b3f9c75SDaniel Axtens 4300b3f9c75SDaniel Axtens /* We could be asked to remove when the hw is down. Again, if 4310b3f9c75SDaniel Axtens * the hw is down, the PE is gone, so we succeed. 4320b3f9c75SDaniel Axtens */ 4330d400f77SChristophe Lombard if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) 4340b3f9c75SDaniel Axtens rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_REMOVE, 0); 4350b3f9c75SDaniel Axtens 4360b3f9c75SDaniel Axtens if (!rc) 437f204e0b8SIan Munsie ctx->pe_inserted = false; 438f204e0b8SIan Munsie slb_invalid(ctx); 439f204e0b8SIan Munsie pr_devel("%s Remove pe: %i finished\n", __func__, ctx->pe); 440cbffa3a5SChristophe Lombard mutex_unlock(&ctx->afu->native->spa_mutex); 441f204e0b8SIan Munsie 442f204e0b8SIan Munsie return rc; 443f204e0b8SIan Munsie } 444f204e0b8SIan Munsie 4451a1a94b8SMichael Neuling void cxl_assign_psn_space(struct cxl_context *ctx) 446f204e0b8SIan Munsie { 447f204e0b8SIan Munsie if (!ctx->afu->pp_size || ctx->master) { 448f204e0b8SIan Munsie ctx->psn_phys = ctx->afu->psn_phys; 449f204e0b8SIan Munsie ctx->psn_size = ctx->afu->adapter->ps_size; 450f204e0b8SIan Munsie } else { 451f204e0b8SIan Munsie ctx->psn_phys = ctx->afu->psn_phys + 452cbffa3a5SChristophe Lombard (ctx->afu->native->pp_offset + ctx->afu->pp_size * ctx->pe); 453f204e0b8SIan Munsie ctx->psn_size = ctx->afu->pp_size; 454f204e0b8SIan Munsie } 455f204e0b8SIan Munsie } 456f204e0b8SIan Munsie 457f204e0b8SIan Munsie static int activate_afu_directed(struct cxl_afu *afu) 458f204e0b8SIan Munsie { 459f204e0b8SIan Munsie int rc; 460f204e0b8SIan Munsie 461f204e0b8SIan Munsie dev_info(&afu->dev, "Activating AFU directed mode\n"); 462f204e0b8SIan Munsie 4634108efb0SChristophe Lombard afu->num_procs = afu->max_procs_virtualised; 464cbffa3a5SChristophe Lombard if (afu->native->spa == NULL) { 46505155772SDaniel Axtens if (cxl_alloc_spa(afu)) 466f204e0b8SIan Munsie return -ENOMEM; 46705155772SDaniel Axtens } 46805155772SDaniel Axtens attach_spa(afu); 469f204e0b8SIan Munsie 470f204e0b8SIan Munsie cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_AFU); 471f204e0b8SIan Munsie cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL); 472f204e0b8SIan Munsie cxl_p1n_write(afu, CXL_PSL_ID_An, CXL_PSL_ID_An_F | CXL_PSL_ID_An_L); 473f204e0b8SIan Munsie 474f204e0b8SIan Munsie afu->current_mode = CXL_MODE_DIRECTED; 475f204e0b8SIan Munsie 476f204e0b8SIan Munsie if ((rc = cxl_chardev_m_afu_add(afu))) 477f204e0b8SIan Munsie return rc; 478f204e0b8SIan Munsie 479f204e0b8SIan Munsie if ((rc = cxl_sysfs_afu_m_add(afu))) 480f204e0b8SIan Munsie goto err; 481f204e0b8SIan Munsie 482f204e0b8SIan Munsie if ((rc = cxl_chardev_s_afu_add(afu))) 483f204e0b8SIan Munsie goto err1; 484f204e0b8SIan Munsie 485f204e0b8SIan Munsie return 0; 486f204e0b8SIan Munsie err1: 487f204e0b8SIan Munsie cxl_sysfs_afu_m_remove(afu); 488f204e0b8SIan Munsie err: 489f204e0b8SIan Munsie cxl_chardev_afu_remove(afu); 490f204e0b8SIan Munsie return rc; 491f204e0b8SIan Munsie } 492f204e0b8SIan Munsie 493f204e0b8SIan Munsie #ifdef CONFIG_CPU_LITTLE_ENDIAN 494f204e0b8SIan Munsie #define set_endian(sr) ((sr) |= CXL_PSL_SR_An_LE) 495f204e0b8SIan Munsie #else 496f204e0b8SIan Munsie #define set_endian(sr) ((sr) &= ~(CXL_PSL_SR_An_LE)) 497f204e0b8SIan Munsie #endif 498f204e0b8SIan Munsie 4992f663527SMichael Neuling static u64 calculate_sr(struct cxl_context *ctx) 5002f663527SMichael Neuling { 5012f663527SMichael Neuling u64 sr = 0; 5022f663527SMichael Neuling 503e606e035SFrederic Barrat set_endian(sr); 5042f663527SMichael Neuling if (ctx->master) 5052f663527SMichael Neuling sr |= CXL_PSL_SR_An_MP; 5062f663527SMichael Neuling if (mfspr(SPRN_LPCR) & LPCR_TC) 5072f663527SMichael Neuling sr |= CXL_PSL_SR_An_TC; 5082f663527SMichael Neuling if (ctx->kernel) { 5097a0d85d3SIan Munsie if (!ctx->real_mode) 5107a0d85d3SIan Munsie sr |= CXL_PSL_SR_An_R; 5117a0d85d3SIan Munsie sr |= (mfmsr() & MSR_SF) | CXL_PSL_SR_An_HV; 5122f663527SMichael Neuling } else { 5132f663527SMichael Neuling sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R; 5142f663527SMichael Neuling sr &= ~(CXL_PSL_SR_An_HV); 5152f663527SMichael Neuling if (!test_tsk_thread_flag(current, TIF_32BIT)) 5162f663527SMichael Neuling sr |= CXL_PSL_SR_An_SF; 5172f663527SMichael Neuling } 5182f663527SMichael Neuling return sr; 5192f663527SMichael Neuling } 5202f663527SMichael Neuling 521292841b0SIan Munsie static void update_ivtes_directed(struct cxl_context *ctx) 522292841b0SIan Munsie { 523292841b0SIan Munsie bool need_update = (ctx->status == STARTED); 524292841b0SIan Munsie int r; 525292841b0SIan Munsie 526292841b0SIan Munsie if (need_update) { 527292841b0SIan Munsie WARN_ON(terminate_process_element(ctx)); 528292841b0SIan Munsie WARN_ON(remove_process_element(ctx)); 529292841b0SIan Munsie } 530292841b0SIan Munsie 531292841b0SIan Munsie for (r = 0; r < CXL_IRQ_RANGES; r++) { 532292841b0SIan Munsie ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]); 533292841b0SIan Munsie ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]); 534292841b0SIan Munsie } 535292841b0SIan Munsie 536292841b0SIan Munsie /* 537292841b0SIan Munsie * Theoretically we could use the update llcmd, instead of a 538292841b0SIan Munsie * terminate/remove/add (or if an atomic update was required we could 539292841b0SIan Munsie * do a suspend/update/resume), however it seems there might be issues 540292841b0SIan Munsie * with the update llcmd on some cards (including those using an XSL on 541292841b0SIan Munsie * an ASIC) so for now it's safest to go with the commands that are 542292841b0SIan Munsie * known to work. In the future if we come across a situation where the 543292841b0SIan Munsie * card may be performing transactions using the same PE while we are 544292841b0SIan Munsie * doing this update we might need to revisit this. 545292841b0SIan Munsie */ 546292841b0SIan Munsie if (need_update) 547292841b0SIan Munsie WARN_ON(add_process_element(ctx)); 548292841b0SIan Munsie } 549292841b0SIan Munsie 550f204e0b8SIan Munsie static int attach_afu_directed(struct cxl_context *ctx, u64 wed, u64 amr) 551f204e0b8SIan Munsie { 5522f663527SMichael Neuling u32 pid; 553292841b0SIan Munsie int result; 554f204e0b8SIan Munsie 5551a1a94b8SMichael Neuling cxl_assign_psn_space(ctx); 556f204e0b8SIan Munsie 557f204e0b8SIan Munsie ctx->elem->ctxtime = 0; /* disable */ 558f204e0b8SIan Munsie ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID)); 559f204e0b8SIan Munsie ctx->elem->haurp = 0; /* disable */ 560f204e0b8SIan Munsie ctx->elem->sdr = cpu_to_be64(mfspr(SPRN_SDR1)); 561f204e0b8SIan Munsie 5622f663527SMichael Neuling pid = current->pid; 5632f663527SMichael Neuling if (ctx->kernel) 5642f663527SMichael Neuling pid = 0; 565f204e0b8SIan Munsie ctx->elem->common.tid = 0; 5662f663527SMichael Neuling ctx->elem->common.pid = cpu_to_be32(pid); 5672f663527SMichael Neuling 5682f663527SMichael Neuling ctx->elem->sr = cpu_to_be64(calculate_sr(ctx)); 569f204e0b8SIan Munsie 570f204e0b8SIan Munsie ctx->elem->common.csrp = 0; /* disable */ 571f204e0b8SIan Munsie ctx->elem->common.aurp0 = 0; /* disable */ 572f204e0b8SIan Munsie ctx->elem->common.aurp1 = 0; /* disable */ 573f204e0b8SIan Munsie 574f204e0b8SIan Munsie cxl_prefault(ctx, wed); 575f204e0b8SIan Munsie 576f204e0b8SIan Munsie ctx->elem->common.sstp0 = cpu_to_be64(ctx->sstp0); 577f204e0b8SIan Munsie ctx->elem->common.sstp1 = cpu_to_be64(ctx->sstp1); 578f204e0b8SIan Munsie 5793c206fa7SIan Munsie /* 5803c206fa7SIan Munsie * Ensure we have the multiplexed PSL interrupt set up to take faults 5813c206fa7SIan Munsie * for kernel contexts that may not have allocated any AFU IRQs at all: 5823c206fa7SIan Munsie */ 5833c206fa7SIan Munsie if (ctx->irqs.range[0] == 0) { 5843c206fa7SIan Munsie ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq; 5853c206fa7SIan Munsie ctx->irqs.range[0] = 1; 5863c206fa7SIan Munsie } 5873c206fa7SIan Munsie 588292841b0SIan Munsie update_ivtes_directed(ctx); 589f204e0b8SIan Munsie 590f204e0b8SIan Munsie ctx->elem->common.amr = cpu_to_be64(amr); 591f204e0b8SIan Munsie ctx->elem->common.wed = cpu_to_be64(wed); 592f204e0b8SIan Munsie 593f204e0b8SIan Munsie /* first guy needs to enable */ 5945be587b1SFrederic Barrat if ((result = cxl_ops->afu_check_and_enable(ctx->afu))) 595f204e0b8SIan Munsie return result; 596f204e0b8SIan Munsie 597368857c1SDaniel Axtens return add_process_element(ctx); 598f204e0b8SIan Munsie } 599f204e0b8SIan Munsie 600f204e0b8SIan Munsie static int deactivate_afu_directed(struct cxl_afu *afu) 601f204e0b8SIan Munsie { 602f204e0b8SIan Munsie dev_info(&afu->dev, "Deactivating AFU directed mode\n"); 603f204e0b8SIan Munsie 604f204e0b8SIan Munsie afu->current_mode = 0; 605f204e0b8SIan Munsie afu->num_procs = 0; 606f204e0b8SIan Munsie 607f204e0b8SIan Munsie cxl_sysfs_afu_m_remove(afu); 608f204e0b8SIan Munsie cxl_chardev_afu_remove(afu); 609f204e0b8SIan Munsie 6105e7823c9SIan Munsie /* 6115e7823c9SIan Munsie * The CAIA section 2.2.1 indicates that the procedure for starting and 6125e7823c9SIan Munsie * stopping an AFU in AFU directed mode is AFU specific, which is not 6135e7823c9SIan Munsie * ideal since this code is generic and with one exception has no 6145e7823c9SIan Munsie * knowledge of the AFU. This is in contrast to the procedure for 6155e7823c9SIan Munsie * disabling a dedicated process AFU, which is documented to just 6165e7823c9SIan Munsie * require a reset. The architecture does indicate that both an AFU 6175e7823c9SIan Munsie * reset and an AFU disable should result in the AFU being disabled and 6185e7823c9SIan Munsie * we do both followed by a PSL purge for safety. 6195e7823c9SIan Munsie * 6205e7823c9SIan Munsie * Notably we used to have some issues with the disable sequence on PSL 6215e7823c9SIan Munsie * cards, which is why we ended up using this heavy weight procedure in 6225e7823c9SIan Munsie * the first place, however a bug was discovered that had rendered the 6235e7823c9SIan Munsie * disable operation ineffective, so it is conceivable that was the 6245e7823c9SIan Munsie * sole explanation for those difficulties. Careful regression testing 6255e7823c9SIan Munsie * is recommended if anyone attempts to remove or reorder these 6265e7823c9SIan Munsie * operations. 6275e7823c9SIan Munsie * 6285e7823c9SIan Munsie * The XSL on the Mellanox CX4 behaves a little differently from the 6295e7823c9SIan Munsie * PSL based cards and will time out an AFU reset if the AFU is still 6305e7823c9SIan Munsie * enabled. That card is special in that we do have a means to identify 6315e7823c9SIan Munsie * it from this code, so in that case we skip the reset and just use a 6325e7823c9SIan Munsie * disable/purge to avoid the timeout and corresponding noise in the 6335e7823c9SIan Munsie * kernel log. 6345e7823c9SIan Munsie */ 6355e7823c9SIan Munsie if (afu->adapter->native->sl_ops->needs_reset_before_disable) 6365be587b1SFrederic Barrat cxl_ops->afu_reset(afu); 637f204e0b8SIan Munsie cxl_afu_disable(afu); 638f204e0b8SIan Munsie cxl_psl_purge(afu); 639f204e0b8SIan Munsie 640f204e0b8SIan Munsie return 0; 641f204e0b8SIan Munsie } 642f204e0b8SIan Munsie 643f204e0b8SIan Munsie static int activate_dedicated_process(struct cxl_afu *afu) 644f204e0b8SIan Munsie { 645f204e0b8SIan Munsie dev_info(&afu->dev, "Activating dedicated process mode\n"); 646f204e0b8SIan Munsie 647f204e0b8SIan Munsie cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_Process); 648f204e0b8SIan Munsie 649f204e0b8SIan Munsie cxl_p1n_write(afu, CXL_PSL_CtxTime_An, 0); /* disable */ 650f204e0b8SIan Munsie cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); /* disable */ 651f204e0b8SIan Munsie cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL); 652f204e0b8SIan Munsie cxl_p1n_write(afu, CXL_PSL_LPID_An, mfspr(SPRN_LPID)); 653f204e0b8SIan Munsie cxl_p1n_write(afu, CXL_HAURP_An, 0); /* disable */ 654f204e0b8SIan Munsie cxl_p1n_write(afu, CXL_PSL_SDR_An, mfspr(SPRN_SDR1)); 655f204e0b8SIan Munsie 656f204e0b8SIan Munsie cxl_p2n_write(afu, CXL_CSRP_An, 0); /* disable */ 657f204e0b8SIan Munsie cxl_p2n_write(afu, CXL_AURP0_An, 0); /* disable */ 658f204e0b8SIan Munsie cxl_p2n_write(afu, CXL_AURP1_An, 0); /* disable */ 659f204e0b8SIan Munsie 660f204e0b8SIan Munsie afu->current_mode = CXL_MODE_DEDICATED; 661f204e0b8SIan Munsie afu->num_procs = 1; 662f204e0b8SIan Munsie 663f204e0b8SIan Munsie return cxl_chardev_d_afu_add(afu); 664f204e0b8SIan Munsie } 665f204e0b8SIan Munsie 666292841b0SIan Munsie static void update_ivtes_dedicated(struct cxl_context *ctx) 667292841b0SIan Munsie { 668292841b0SIan Munsie struct cxl_afu *afu = ctx->afu; 669292841b0SIan Munsie 670292841b0SIan Munsie cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 671292841b0SIan Munsie (((u64)ctx->irqs.offset[0] & 0xffff) << 48) | 672292841b0SIan Munsie (((u64)ctx->irqs.offset[1] & 0xffff) << 32) | 673292841b0SIan Munsie (((u64)ctx->irqs.offset[2] & 0xffff) << 16) | 674292841b0SIan Munsie ((u64)ctx->irqs.offset[3] & 0xffff)); 675292841b0SIan Munsie cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, (u64) 676292841b0SIan Munsie (((u64)ctx->irqs.range[0] & 0xffff) << 48) | 677292841b0SIan Munsie (((u64)ctx->irqs.range[1] & 0xffff) << 32) | 678292841b0SIan Munsie (((u64)ctx->irqs.range[2] & 0xffff) << 16) | 679292841b0SIan Munsie ((u64)ctx->irqs.range[3] & 0xffff)); 680292841b0SIan Munsie } 681292841b0SIan Munsie 682f204e0b8SIan Munsie static int attach_dedicated(struct cxl_context *ctx, u64 wed, u64 amr) 683f204e0b8SIan Munsie { 684f204e0b8SIan Munsie struct cxl_afu *afu = ctx->afu; 6852f663527SMichael Neuling u64 pid; 686f204e0b8SIan Munsie int rc; 687f204e0b8SIan Munsie 6882f663527SMichael Neuling pid = (u64)current->pid << 32; 6892f663527SMichael Neuling if (ctx->kernel) 6902f663527SMichael Neuling pid = 0; 6912f663527SMichael Neuling cxl_p2n_write(afu, CXL_PSL_PID_TID_An, pid); 6922f663527SMichael Neuling 6932f663527SMichael Neuling cxl_p1n_write(afu, CXL_PSL_SR_An, calculate_sr(ctx)); 694f204e0b8SIan Munsie 695f204e0b8SIan Munsie if ((rc = cxl_write_sstp(afu, ctx->sstp0, ctx->sstp1))) 696f204e0b8SIan Munsie return rc; 697f204e0b8SIan Munsie 698f204e0b8SIan Munsie cxl_prefault(ctx, wed); 699f204e0b8SIan Munsie 700292841b0SIan Munsie update_ivtes_dedicated(ctx); 701f204e0b8SIan Munsie 702f204e0b8SIan Munsie cxl_p2n_write(afu, CXL_PSL_AMR_An, amr); 703f204e0b8SIan Munsie 704f204e0b8SIan Munsie /* master only context for dedicated */ 7051a1a94b8SMichael Neuling cxl_assign_psn_space(ctx); 706f204e0b8SIan Munsie 7075be587b1SFrederic Barrat if ((rc = cxl_ops->afu_reset(afu))) 708f204e0b8SIan Munsie return rc; 709f204e0b8SIan Munsie 710f204e0b8SIan Munsie cxl_p2n_write(afu, CXL_PSL_WED_An, wed); 711f204e0b8SIan Munsie 712f204e0b8SIan Munsie return afu_enable(afu); 713f204e0b8SIan Munsie } 714f204e0b8SIan Munsie 715f204e0b8SIan Munsie static int deactivate_dedicated_process(struct cxl_afu *afu) 716f204e0b8SIan Munsie { 717f204e0b8SIan Munsie dev_info(&afu->dev, "Deactivating dedicated process mode\n"); 718f204e0b8SIan Munsie 719f204e0b8SIan Munsie afu->current_mode = 0; 720f204e0b8SIan Munsie afu->num_procs = 0; 721f204e0b8SIan Munsie 722f204e0b8SIan Munsie cxl_chardev_afu_remove(afu); 723f204e0b8SIan Munsie 724f204e0b8SIan Munsie return 0; 725f204e0b8SIan Munsie } 726f204e0b8SIan Munsie 7272b04cf31SFrederic Barrat static int native_afu_deactivate_mode(struct cxl_afu *afu, int mode) 728f204e0b8SIan Munsie { 729f204e0b8SIan Munsie if (mode == CXL_MODE_DIRECTED) 730f204e0b8SIan Munsie return deactivate_afu_directed(afu); 731f204e0b8SIan Munsie if (mode == CXL_MODE_DEDICATED) 732f204e0b8SIan Munsie return deactivate_dedicated_process(afu); 733f204e0b8SIan Munsie return 0; 734f204e0b8SIan Munsie } 735f204e0b8SIan Munsie 7362b04cf31SFrederic Barrat static int native_afu_activate_mode(struct cxl_afu *afu, int mode) 737f204e0b8SIan Munsie { 738f204e0b8SIan Munsie if (!mode) 739f204e0b8SIan Munsie return 0; 740f204e0b8SIan Munsie if (!(mode & afu->modes_supported)) 741f204e0b8SIan Munsie return -EINVAL; 742f204e0b8SIan Munsie 7430d400f77SChristophe Lombard if (!cxl_ops->link_ok(afu->adapter, afu)) { 7440b3f9c75SDaniel Axtens WARN(1, "Device link is down, refusing to activate!\n"); 7450b3f9c75SDaniel Axtens return -EIO; 7460b3f9c75SDaniel Axtens } 7470b3f9c75SDaniel Axtens 748f204e0b8SIan Munsie if (mode == CXL_MODE_DIRECTED) 749f204e0b8SIan Munsie return activate_afu_directed(afu); 750f204e0b8SIan Munsie if (mode == CXL_MODE_DEDICATED) 751f204e0b8SIan Munsie return activate_dedicated_process(afu); 752f204e0b8SIan Munsie 753f204e0b8SIan Munsie return -EINVAL; 754f204e0b8SIan Munsie } 755f204e0b8SIan Munsie 7562b04cf31SFrederic Barrat static int native_attach_process(struct cxl_context *ctx, bool kernel, 7572b04cf31SFrederic Barrat u64 wed, u64 amr) 758f204e0b8SIan Munsie { 7590d400f77SChristophe Lombard if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) { 7600b3f9c75SDaniel Axtens WARN(1, "Device link is down, refusing to attach process!\n"); 7610b3f9c75SDaniel Axtens return -EIO; 7620b3f9c75SDaniel Axtens } 7630b3f9c75SDaniel Axtens 764f204e0b8SIan Munsie ctx->kernel = kernel; 765f204e0b8SIan Munsie if (ctx->afu->current_mode == CXL_MODE_DIRECTED) 766f204e0b8SIan Munsie return attach_afu_directed(ctx, wed, amr); 767f204e0b8SIan Munsie 768f204e0b8SIan Munsie if (ctx->afu->current_mode == CXL_MODE_DEDICATED) 769f204e0b8SIan Munsie return attach_dedicated(ctx, wed, amr); 770f204e0b8SIan Munsie 771f204e0b8SIan Munsie return -EINVAL; 772f204e0b8SIan Munsie } 773f204e0b8SIan Munsie 774f204e0b8SIan Munsie static inline int detach_process_native_dedicated(struct cxl_context *ctx) 775f204e0b8SIan Munsie { 7765e7823c9SIan Munsie /* 7775e7823c9SIan Munsie * The CAIA section 2.1.1 indicates that we need to do an AFU reset to 7785e7823c9SIan Munsie * stop the AFU in dedicated mode (we therefore do not make that 7795e7823c9SIan Munsie * optional like we do in the afu directed path). It does not indicate 7805e7823c9SIan Munsie * that we need to do an explicit disable (which should occur 7815e7823c9SIan Munsie * implicitly as part of the reset) or purge, but we do these as well 7825e7823c9SIan Munsie * to be on the safe side. 7835e7823c9SIan Munsie * 7845e7823c9SIan Munsie * Notably we used to have some issues with the disable sequence 7855e7823c9SIan Munsie * (before the sequence was spelled out in the architecture) which is 7865e7823c9SIan Munsie * why we were so heavy weight in the first place, however a bug was 7875e7823c9SIan Munsie * discovered that had rendered the disable operation ineffective, so 7885e7823c9SIan Munsie * it is conceivable that was the sole explanation for those 7895e7823c9SIan Munsie * difficulties. Point is, we should be careful and do some regression 7905e7823c9SIan Munsie * testing if we ever attempt to remove any part of this procedure. 7915e7823c9SIan Munsie */ 7925be587b1SFrederic Barrat cxl_ops->afu_reset(ctx->afu); 793f204e0b8SIan Munsie cxl_afu_disable(ctx->afu); 794f204e0b8SIan Munsie cxl_psl_purge(ctx->afu); 795f204e0b8SIan Munsie return 0; 796f204e0b8SIan Munsie } 797f204e0b8SIan Munsie 798292841b0SIan Munsie static void native_update_ivtes(struct cxl_context *ctx) 799292841b0SIan Munsie { 800292841b0SIan Munsie if (ctx->afu->current_mode == CXL_MODE_DIRECTED) 801292841b0SIan Munsie return update_ivtes_directed(ctx); 802292841b0SIan Munsie if (ctx->afu->current_mode == CXL_MODE_DEDICATED) 803292841b0SIan Munsie return update_ivtes_dedicated(ctx); 804292841b0SIan Munsie WARN(1, "native_update_ivtes: Bad mode\n"); 805292841b0SIan Munsie } 806292841b0SIan Munsie 807f204e0b8SIan Munsie static inline int detach_process_native_afu_directed(struct cxl_context *ctx) 808f204e0b8SIan Munsie { 809f204e0b8SIan Munsie if (!ctx->pe_inserted) 810f204e0b8SIan Munsie return 0; 811f204e0b8SIan Munsie if (terminate_process_element(ctx)) 812f204e0b8SIan Munsie return -1; 813f204e0b8SIan Munsie if (remove_process_element(ctx)) 814f204e0b8SIan Munsie return -1; 815f204e0b8SIan Munsie 816f204e0b8SIan Munsie return 0; 817f204e0b8SIan Munsie } 818f204e0b8SIan Munsie 8192b04cf31SFrederic Barrat static int native_detach_process(struct cxl_context *ctx) 820f204e0b8SIan Munsie { 8219bcf28cdSIan Munsie trace_cxl_detach(ctx); 8229bcf28cdSIan Munsie 823f204e0b8SIan Munsie if (ctx->afu->current_mode == CXL_MODE_DEDICATED) 824f204e0b8SIan Munsie return detach_process_native_dedicated(ctx); 825f204e0b8SIan Munsie 826f204e0b8SIan Munsie return detach_process_native_afu_directed(ctx); 827f204e0b8SIan Munsie } 828f204e0b8SIan Munsie 8292b04cf31SFrederic Barrat static int native_get_irq_info(struct cxl_afu *afu, struct cxl_irq_info *info) 830f204e0b8SIan Munsie { 831f204e0b8SIan Munsie u64 pidtid; 832f204e0b8SIan Munsie 8330b3f9c75SDaniel Axtens /* If the adapter has gone away, we can't get any meaningful 8340b3f9c75SDaniel Axtens * information. 8350b3f9c75SDaniel Axtens */ 8360d400f77SChristophe Lombard if (!cxl_ops->link_ok(afu->adapter, afu)) 8370b3f9c75SDaniel Axtens return -EIO; 8380b3f9c75SDaniel Axtens 839bc78b05bSIan Munsie info->dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); 840bc78b05bSIan Munsie info->dar = cxl_p2n_read(afu, CXL_PSL_DAR_An); 841bc78b05bSIan Munsie info->dsr = cxl_p2n_read(afu, CXL_PSL_DSR_An); 842bc78b05bSIan Munsie pidtid = cxl_p2n_read(afu, CXL_PSL_PID_TID_An); 843f204e0b8SIan Munsie info->pid = pidtid >> 32; 844f204e0b8SIan Munsie info->tid = pidtid & 0xffffffff; 845bc78b05bSIan Munsie info->afu_err = cxl_p2n_read(afu, CXL_AFU_ERR_An); 846bc78b05bSIan Munsie info->errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); 847444c4ba4SChristophe Lombard info->proc_handle = 0; 848f204e0b8SIan Munsie 849f204e0b8SIan Munsie return 0; 850f204e0b8SIan Munsie } 851f204e0b8SIan Munsie 8526d382616SFrederic Barrat void cxl_native_psl_irq_dump_regs(struct cxl_context *ctx) 853d56d301bSFrederic Barrat { 854d56d301bSFrederic Barrat u64 fir1, fir2, fir_slice, serr, afu_debug; 855d56d301bSFrederic Barrat 856d56d301bSFrederic Barrat fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR1); 857d56d301bSFrederic Barrat fir2 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR2); 858d56d301bSFrederic Barrat fir_slice = cxl_p1n_read(ctx->afu, CXL_PSL_FIR_SLICE_An); 859d56d301bSFrederic Barrat afu_debug = cxl_p1n_read(ctx->afu, CXL_AFU_DEBUG_An); 860d56d301bSFrederic Barrat 861d56d301bSFrederic Barrat dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1); 862d56d301bSFrederic Barrat dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%016llx\n", fir2); 8636d382616SFrederic Barrat if (ctx->afu->adapter->native->sl_ops->register_serr_irq) { 8646d382616SFrederic Barrat serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An); 865d56d301bSFrederic Barrat dev_crit(&ctx->afu->dev, "PSL_SERR_An: 0x%016llx\n", serr); 8666d382616SFrederic Barrat } 867d56d301bSFrederic Barrat dev_crit(&ctx->afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice); 868d56d301bSFrederic Barrat dev_crit(&ctx->afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug); 8696d382616SFrederic Barrat } 870d56d301bSFrederic Barrat 8716d382616SFrederic Barrat static irqreturn_t native_handle_psl_slice_error(struct cxl_context *ctx, 8726d382616SFrederic Barrat u64 dsisr, u64 errstat) 8736d382616SFrederic Barrat { 8746d382616SFrederic Barrat 8756d382616SFrederic Barrat dev_crit(&ctx->afu->dev, "PSL ERROR STATUS: 0x%016llx\n", errstat); 8766d382616SFrederic Barrat 8776d382616SFrederic Barrat if (ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers) 8786d382616SFrederic Barrat ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers(ctx); 8796d382616SFrederic Barrat 8806d382616SFrederic Barrat if (ctx->afu->adapter->native->sl_ops->debugfs_stop_trace) { 881d56d301bSFrederic Barrat dev_crit(&ctx->afu->dev, "STOPPING CXL TRACE\n"); 8826d382616SFrederic Barrat ctx->afu->adapter->native->sl_ops->debugfs_stop_trace(ctx->afu->adapter); 8836d382616SFrederic Barrat } 884d56d301bSFrederic Barrat 8855be587b1SFrederic Barrat return cxl_ops->ack_irq(ctx, 0, errstat); 886d56d301bSFrederic Barrat } 887d56d301bSFrederic Barrat 888d56d301bSFrederic Barrat static irqreturn_t fail_psl_irq(struct cxl_afu *afu, struct cxl_irq_info *irq_info) 889d56d301bSFrederic Barrat { 890d56d301bSFrederic Barrat if (irq_info->dsisr & CXL_PSL_DSISR_TRANS) 891d56d301bSFrederic Barrat cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); 892d56d301bSFrederic Barrat else 893d56d301bSFrederic Barrat cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); 894d56d301bSFrederic Barrat 895d56d301bSFrederic Barrat return IRQ_HANDLED; 896d56d301bSFrederic Barrat } 897d56d301bSFrederic Barrat 8982b04cf31SFrederic Barrat static irqreturn_t native_irq_multiplexed(int irq, void *data) 899d56d301bSFrederic Barrat { 900d56d301bSFrederic Barrat struct cxl_afu *afu = data; 901d56d301bSFrederic Barrat struct cxl_context *ctx; 902d56d301bSFrederic Barrat struct cxl_irq_info irq_info; 903d56d301bSFrederic Barrat int ph = cxl_p2n_read(afu, CXL_PSL_PEHandle_An) & 0xffff; 904d56d301bSFrederic Barrat int ret; 905d56d301bSFrederic Barrat 9062b04cf31SFrederic Barrat if ((ret = native_get_irq_info(afu, &irq_info))) { 907d56d301bSFrederic Barrat WARN(1, "Unable to get CXL IRQ Info: %i\n", ret); 908d56d301bSFrederic Barrat return fail_psl_irq(afu, &irq_info); 909d56d301bSFrederic Barrat } 910d56d301bSFrederic Barrat 911d56d301bSFrederic Barrat rcu_read_lock(); 912d56d301bSFrederic Barrat ctx = idr_find(&afu->contexts_idr, ph); 913d56d301bSFrederic Barrat if (ctx) { 914d56d301bSFrederic Barrat ret = cxl_irq(irq, ctx, &irq_info); 915d56d301bSFrederic Barrat rcu_read_unlock(); 916d56d301bSFrederic Barrat return ret; 917d56d301bSFrederic Barrat } 918d56d301bSFrederic Barrat rcu_read_unlock(); 919d56d301bSFrederic Barrat 920d56d301bSFrederic Barrat WARN(1, "Unable to demultiplex CXL PSL IRQ for PE %i DSISR %016llx DAR" 921d56d301bSFrederic Barrat " %016llx\n(Possible AFU HW issue - was a term/remove acked" 922d56d301bSFrederic Barrat " with outstanding transactions?)\n", ph, irq_info.dsisr, 923d56d301bSFrederic Barrat irq_info.dar); 924d56d301bSFrederic Barrat return fail_psl_irq(afu, &irq_info); 925d56d301bSFrederic Barrat } 926d56d301bSFrederic Barrat 9272bc79ffcSMichael Neuling void native_irq_wait(struct cxl_context *ctx) 9282bc79ffcSMichael Neuling { 9292bc79ffcSMichael Neuling u64 dsisr; 9302bc79ffcSMichael Neuling int timeout = 1000; 9312bc79ffcSMichael Neuling int ph; 9322bc79ffcSMichael Neuling 9332bc79ffcSMichael Neuling /* 9342bc79ffcSMichael Neuling * Wait until no further interrupts are presented by the PSL 9352bc79ffcSMichael Neuling * for this context. 9362bc79ffcSMichael Neuling */ 9372bc79ffcSMichael Neuling while (timeout--) { 9382bc79ffcSMichael Neuling ph = cxl_p2n_read(ctx->afu, CXL_PSL_PEHandle_An) & 0xffff; 9392bc79ffcSMichael Neuling if (ph != ctx->pe) 9402bc79ffcSMichael Neuling return; 9412bc79ffcSMichael Neuling dsisr = cxl_p2n_read(ctx->afu, CXL_PSL_DSISR_An); 9422bc79ffcSMichael Neuling if ((dsisr & CXL_PSL_DSISR_PENDING) == 0) 9432bc79ffcSMichael Neuling return; 9442bc79ffcSMichael Neuling /* 9452bc79ffcSMichael Neuling * We are waiting for the workqueue to process our 9462bc79ffcSMichael Neuling * irq, so need to let that run here. 9472bc79ffcSMichael Neuling */ 9482bc79ffcSMichael Neuling msleep(1); 9492bc79ffcSMichael Neuling } 9502bc79ffcSMichael Neuling 9512bc79ffcSMichael Neuling dev_warn(&ctx->afu->dev, "WARNING: waiting on DSI for PE %i" 9522bc79ffcSMichael Neuling " DSISR %016llx!\n", ph, dsisr); 9532bc79ffcSMichael Neuling return; 9542bc79ffcSMichael Neuling } 9552bc79ffcSMichael Neuling 9562b04cf31SFrederic Barrat static irqreturn_t native_slice_irq_err(int irq, void *data) 957d56d301bSFrederic Barrat { 958d56d301bSFrederic Barrat struct cxl_afu *afu = data; 959d56d301bSFrederic Barrat u64 fir_slice, errstat, serr, afu_debug; 960d56d301bSFrederic Barrat 9616d382616SFrederic Barrat /* 9626d382616SFrederic Barrat * slice err interrupt is only used with full PSL (no XSL) 9636d382616SFrederic Barrat */ 964d56d301bSFrederic Barrat WARN(irq, "CXL SLICE ERROR interrupt %i\n", irq); 965d56d301bSFrederic Barrat 966d56d301bSFrederic Barrat serr = cxl_p1n_read(afu, CXL_PSL_SERR_An); 967d56d301bSFrederic Barrat fir_slice = cxl_p1n_read(afu, CXL_PSL_FIR_SLICE_An); 968d56d301bSFrederic Barrat errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); 969d56d301bSFrederic Barrat afu_debug = cxl_p1n_read(afu, CXL_AFU_DEBUG_An); 970d56d301bSFrederic Barrat dev_crit(&afu->dev, "PSL_SERR_An: 0x%016llx\n", serr); 971d56d301bSFrederic Barrat dev_crit(&afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice); 972d56d301bSFrederic Barrat dev_crit(&afu->dev, "CXL_PSL_ErrStat_An: 0x%016llx\n", errstat); 973d56d301bSFrederic Barrat dev_crit(&afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug); 974d56d301bSFrederic Barrat 975d56d301bSFrederic Barrat cxl_p1n_write(afu, CXL_PSL_SERR_An, serr); 976d56d301bSFrederic Barrat 977d56d301bSFrederic Barrat return IRQ_HANDLED; 978d56d301bSFrederic Barrat } 979d56d301bSFrederic Barrat 9806d382616SFrederic Barrat void cxl_native_err_irq_dump_regs(struct cxl *adapter) 9816d382616SFrederic Barrat { 9826d382616SFrederic Barrat u64 fir1, fir2; 9836d382616SFrederic Barrat 9846d382616SFrederic Barrat fir1 = cxl_p1_read(adapter, CXL_PSL_FIR1); 9856d382616SFrederic Barrat fir2 = cxl_p1_read(adapter, CXL_PSL_FIR2); 9866d382616SFrederic Barrat 9876d382616SFrederic Barrat dev_crit(&adapter->dev, "PSL_FIR1: 0x%016llx\nPSL_FIR2: 0x%016llx\n", fir1, fir2); 9886d382616SFrederic Barrat } 9896d382616SFrederic Barrat 9902b04cf31SFrederic Barrat static irqreturn_t native_irq_err(int irq, void *data) 991d56d301bSFrederic Barrat { 992d56d301bSFrederic Barrat struct cxl *adapter = data; 9936d382616SFrederic Barrat u64 err_ivte; 994d56d301bSFrederic Barrat 995d56d301bSFrederic Barrat WARN(1, "CXL ERROR interrupt %i\n", irq); 996d56d301bSFrederic Barrat 997d56d301bSFrederic Barrat err_ivte = cxl_p1_read(adapter, CXL_PSL_ErrIVTE); 998d56d301bSFrederic Barrat dev_crit(&adapter->dev, "PSL_ErrIVTE: 0x%016llx\n", err_ivte); 999d56d301bSFrederic Barrat 10006d382616SFrederic Barrat if (adapter->native->sl_ops->debugfs_stop_trace) { 1001d56d301bSFrederic Barrat dev_crit(&adapter->dev, "STOPPING CXL TRACE\n"); 10026d382616SFrederic Barrat adapter->native->sl_ops->debugfs_stop_trace(adapter); 10036d382616SFrederic Barrat } 1004d56d301bSFrederic Barrat 10056d382616SFrederic Barrat if (adapter->native->sl_ops->err_irq_dump_registers) 10066d382616SFrederic Barrat adapter->native->sl_ops->err_irq_dump_registers(adapter); 1007d56d301bSFrederic Barrat 1008d56d301bSFrederic Barrat return IRQ_HANDLED; 1009d56d301bSFrederic Barrat } 1010d56d301bSFrederic Barrat 10112b04cf31SFrederic Barrat int cxl_native_register_psl_err_irq(struct cxl *adapter) 1012d56d301bSFrederic Barrat { 1013d56d301bSFrederic Barrat int rc; 1014d56d301bSFrederic Barrat 1015d56d301bSFrederic Barrat adapter->irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err", 1016d56d301bSFrederic Barrat dev_name(&adapter->dev)); 1017d56d301bSFrederic Barrat if (!adapter->irq_name) 1018d56d301bSFrederic Barrat return -ENOMEM; 1019d56d301bSFrederic Barrat 10202b04cf31SFrederic Barrat if ((rc = cxl_register_one_irq(adapter, native_irq_err, adapter, 1021cbffa3a5SChristophe Lombard &adapter->native->err_hwirq, 1022cbffa3a5SChristophe Lombard &adapter->native->err_virq, 1023d56d301bSFrederic Barrat adapter->irq_name))) { 1024d56d301bSFrederic Barrat kfree(adapter->irq_name); 1025d56d301bSFrederic Barrat adapter->irq_name = NULL; 1026d56d301bSFrederic Barrat return rc; 1027d56d301bSFrederic Barrat } 1028d56d301bSFrederic Barrat 1029cbffa3a5SChristophe Lombard cxl_p1_write(adapter, CXL_PSL_ErrIVTE, adapter->native->err_hwirq & 0xffff); 1030d56d301bSFrederic Barrat 1031d56d301bSFrederic Barrat return 0; 1032d56d301bSFrederic Barrat } 1033d56d301bSFrederic Barrat 10342b04cf31SFrederic Barrat void cxl_native_release_psl_err_irq(struct cxl *adapter) 1035d56d301bSFrederic Barrat { 1036cbffa3a5SChristophe Lombard if (adapter->native->err_virq != irq_find_mapping(NULL, adapter->native->err_hwirq)) 1037d56d301bSFrederic Barrat return; 1038d56d301bSFrederic Barrat 1039d56d301bSFrederic Barrat cxl_p1_write(adapter, CXL_PSL_ErrIVTE, 0x0000000000000000); 1040cbffa3a5SChristophe Lombard cxl_unmap_irq(adapter->native->err_virq, adapter); 1041cbffa3a5SChristophe Lombard cxl_ops->release_one_irq(adapter, adapter->native->err_hwirq); 1042d56d301bSFrederic Barrat kfree(adapter->irq_name); 1043d56d301bSFrederic Barrat } 1044d56d301bSFrederic Barrat 10452b04cf31SFrederic Barrat int cxl_native_register_serr_irq(struct cxl_afu *afu) 1046d56d301bSFrederic Barrat { 1047d56d301bSFrederic Barrat u64 serr; 1048d56d301bSFrederic Barrat int rc; 1049d56d301bSFrederic Barrat 1050d56d301bSFrederic Barrat afu->err_irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err", 1051d56d301bSFrederic Barrat dev_name(&afu->dev)); 1052d56d301bSFrederic Barrat if (!afu->err_irq_name) 1053d56d301bSFrederic Barrat return -ENOMEM; 1054d56d301bSFrederic Barrat 10552b04cf31SFrederic Barrat if ((rc = cxl_register_one_irq(afu->adapter, native_slice_irq_err, afu, 1056d56d301bSFrederic Barrat &afu->serr_hwirq, 1057d56d301bSFrederic Barrat &afu->serr_virq, afu->err_irq_name))) { 1058d56d301bSFrederic Barrat kfree(afu->err_irq_name); 1059d56d301bSFrederic Barrat afu->err_irq_name = NULL; 1060d56d301bSFrederic Barrat return rc; 1061d56d301bSFrederic Barrat } 1062d56d301bSFrederic Barrat 1063d56d301bSFrederic Barrat serr = cxl_p1n_read(afu, CXL_PSL_SERR_An); 1064d56d301bSFrederic Barrat serr = (serr & 0x00ffffffffff0000ULL) | (afu->serr_hwirq & 0xffff); 1065d56d301bSFrederic Barrat cxl_p1n_write(afu, CXL_PSL_SERR_An, serr); 1066d56d301bSFrederic Barrat 1067d56d301bSFrederic Barrat return 0; 1068d56d301bSFrederic Barrat } 1069d56d301bSFrederic Barrat 10702b04cf31SFrederic Barrat void cxl_native_release_serr_irq(struct cxl_afu *afu) 1071d56d301bSFrederic Barrat { 1072d56d301bSFrederic Barrat if (afu->serr_virq != irq_find_mapping(NULL, afu->serr_hwirq)) 1073d56d301bSFrederic Barrat return; 1074d56d301bSFrederic Barrat 1075d56d301bSFrederic Barrat cxl_p1n_write(afu, CXL_PSL_SERR_An, 0x0000000000000000); 1076d56d301bSFrederic Barrat cxl_unmap_irq(afu->serr_virq, afu); 10775be587b1SFrederic Barrat cxl_ops->release_one_irq(afu->adapter, afu->serr_hwirq); 1078d56d301bSFrederic Barrat kfree(afu->err_irq_name); 1079d56d301bSFrederic Barrat } 1080d56d301bSFrederic Barrat 10812b04cf31SFrederic Barrat int cxl_native_register_psl_irq(struct cxl_afu *afu) 1082d56d301bSFrederic Barrat { 1083d56d301bSFrederic Barrat int rc; 1084d56d301bSFrederic Barrat 1085d56d301bSFrederic Barrat afu->psl_irq_name = kasprintf(GFP_KERNEL, "cxl-%s", 1086d56d301bSFrederic Barrat dev_name(&afu->dev)); 1087d56d301bSFrederic Barrat if (!afu->psl_irq_name) 1088d56d301bSFrederic Barrat return -ENOMEM; 1089d56d301bSFrederic Barrat 1090cbffa3a5SChristophe Lombard if ((rc = cxl_register_one_irq(afu->adapter, native_irq_multiplexed, 1091cbffa3a5SChristophe Lombard afu, &afu->native->psl_hwirq, &afu->native->psl_virq, 1092d56d301bSFrederic Barrat afu->psl_irq_name))) { 1093d56d301bSFrederic Barrat kfree(afu->psl_irq_name); 1094d56d301bSFrederic Barrat afu->psl_irq_name = NULL; 1095d56d301bSFrederic Barrat } 1096d56d301bSFrederic Barrat return rc; 1097d56d301bSFrederic Barrat } 1098d56d301bSFrederic Barrat 10992b04cf31SFrederic Barrat void cxl_native_release_psl_irq(struct cxl_afu *afu) 1100d56d301bSFrederic Barrat { 1101cbffa3a5SChristophe Lombard if (afu->native->psl_virq != irq_find_mapping(NULL, afu->native->psl_hwirq)) 1102d56d301bSFrederic Barrat return; 1103d56d301bSFrederic Barrat 1104cbffa3a5SChristophe Lombard cxl_unmap_irq(afu->native->psl_virq, afu); 1105cbffa3a5SChristophe Lombard cxl_ops->release_one_irq(afu->adapter, afu->native->psl_hwirq); 1106d56d301bSFrederic Barrat kfree(afu->psl_irq_name); 1107d56d301bSFrederic Barrat } 1108d56d301bSFrederic Barrat 1109f204e0b8SIan Munsie static void recover_psl_err(struct cxl_afu *afu, u64 errstat) 1110f204e0b8SIan Munsie { 1111f204e0b8SIan Munsie u64 dsisr; 1112f204e0b8SIan Munsie 1113de369538SRasmus Villemoes pr_devel("RECOVERING FROM PSL ERROR... (0x%016llx)\n", errstat); 1114f204e0b8SIan Munsie 1115f204e0b8SIan Munsie /* Clear PSL_DSISR[PE] */ 1116f204e0b8SIan Munsie dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); 1117f204e0b8SIan Munsie cxl_p2n_write(afu, CXL_PSL_DSISR_An, dsisr & ~CXL_PSL_DSISR_An_PE); 1118f204e0b8SIan Munsie 1119f204e0b8SIan Munsie /* Write 1s to clear error status bits */ 1120f204e0b8SIan Munsie cxl_p2n_write(afu, CXL_PSL_ErrStat_An, errstat); 1121f204e0b8SIan Munsie } 1122f204e0b8SIan Munsie 11232b04cf31SFrederic Barrat static int native_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask) 1124f204e0b8SIan Munsie { 11259bcf28cdSIan Munsie trace_cxl_psl_irq_ack(ctx, tfc); 1126f204e0b8SIan Munsie if (tfc) 1127f204e0b8SIan Munsie cxl_p2n_write(ctx->afu, CXL_PSL_TFC_An, tfc); 1128f204e0b8SIan Munsie if (psl_reset_mask) 1129f204e0b8SIan Munsie recover_psl_err(ctx->afu, psl_reset_mask); 1130f204e0b8SIan Munsie 1131f204e0b8SIan Munsie return 0; 1132f204e0b8SIan Munsie } 1133f204e0b8SIan Munsie 1134f204e0b8SIan Munsie int cxl_check_error(struct cxl_afu *afu) 1135f204e0b8SIan Munsie { 1136f204e0b8SIan Munsie return (cxl_p1n_read(afu, CXL_PSL_SCNTL_An) == ~0ULL); 1137f204e0b8SIan Munsie } 1138d56d301bSFrederic Barrat 11394752876cSChristophe Lombard static bool native_support_attributes(const char *attr_name, 11404752876cSChristophe Lombard enum cxl_attrs type) 11414752876cSChristophe Lombard { 11424752876cSChristophe Lombard return true; 11434752876cSChristophe Lombard } 11444752876cSChristophe Lombard 11452b04cf31SFrederic Barrat static int native_afu_cr_read64(struct cxl_afu *afu, int cr, u64 off, u64 *out) 1146d56d301bSFrederic Barrat { 11470d400f77SChristophe Lombard if (unlikely(!cxl_ops->link_ok(afu->adapter, afu))) 11485be587b1SFrederic Barrat return -EIO; 11495be587b1SFrederic Barrat if (unlikely(off >= afu->crs_len)) 11505be587b1SFrederic Barrat return -ERANGE; 1151cbffa3a5SChristophe Lombard *out = in_le64(afu->native->afu_desc_mmio + afu->crs_offset + 11525be587b1SFrederic Barrat (cr * afu->crs_len) + off); 11535be587b1SFrederic Barrat return 0; 1154d56d301bSFrederic Barrat } 1155d56d301bSFrederic Barrat 11562b04cf31SFrederic Barrat static int native_afu_cr_read32(struct cxl_afu *afu, int cr, u64 off, u32 *out) 1157d56d301bSFrederic Barrat { 11580d400f77SChristophe Lombard if (unlikely(!cxl_ops->link_ok(afu->adapter, afu))) 11595be587b1SFrederic Barrat return -EIO; 11605be587b1SFrederic Barrat if (unlikely(off >= afu->crs_len)) 11615be587b1SFrederic Barrat return -ERANGE; 1162cbffa3a5SChristophe Lombard *out = in_le32(afu->native->afu_desc_mmio + afu->crs_offset + 11635be587b1SFrederic Barrat (cr * afu->crs_len) + off); 11645be587b1SFrederic Barrat return 0; 1165d56d301bSFrederic Barrat } 1166d56d301bSFrederic Barrat 11672b04cf31SFrederic Barrat static int native_afu_cr_read16(struct cxl_afu *afu, int cr, u64 off, u16 *out) 1168d56d301bSFrederic Barrat { 1169d56d301bSFrederic Barrat u64 aligned_off = off & ~0x3L; 1170d56d301bSFrederic Barrat u32 val; 11715be587b1SFrederic Barrat int rc; 1172d56d301bSFrederic Barrat 11732b04cf31SFrederic Barrat rc = native_afu_cr_read32(afu, cr, aligned_off, &val); 11745be587b1SFrederic Barrat if (!rc) 11755be587b1SFrederic Barrat *out = (val >> ((off & 0x3) * 8)) & 0xffff; 11765be587b1SFrederic Barrat return rc; 1177d56d301bSFrederic Barrat } 1178d56d301bSFrederic Barrat 11792b04cf31SFrederic Barrat static int native_afu_cr_read8(struct cxl_afu *afu, int cr, u64 off, u8 *out) 1180d56d301bSFrederic Barrat { 1181d56d301bSFrederic Barrat u64 aligned_off = off & ~0x3L; 1182d56d301bSFrederic Barrat u32 val; 11835be587b1SFrederic Barrat int rc; 1184d56d301bSFrederic Barrat 11852b04cf31SFrederic Barrat rc = native_afu_cr_read32(afu, cr, aligned_off, &val); 11865be587b1SFrederic Barrat if (!rc) 11875be587b1SFrederic Barrat *out = (val >> ((off & 0x3) * 8)) & 0xff; 11885be587b1SFrederic Barrat return rc; 1189d56d301bSFrederic Barrat } 11905be587b1SFrederic Barrat 1191d601ea91SFrederic Barrat static int native_afu_cr_write32(struct cxl_afu *afu, int cr, u64 off, u32 in) 1192d601ea91SFrederic Barrat { 11930d400f77SChristophe Lombard if (unlikely(!cxl_ops->link_ok(afu->adapter, afu))) 1194d601ea91SFrederic Barrat return -EIO; 1195d601ea91SFrederic Barrat if (unlikely(off >= afu->crs_len)) 1196d601ea91SFrederic Barrat return -ERANGE; 1197d601ea91SFrederic Barrat out_le32(afu->native->afu_desc_mmio + afu->crs_offset + 1198d601ea91SFrederic Barrat (cr * afu->crs_len) + off, in); 1199d601ea91SFrederic Barrat return 0; 1200d601ea91SFrederic Barrat } 1201d601ea91SFrederic Barrat 1202d601ea91SFrederic Barrat static int native_afu_cr_write16(struct cxl_afu *afu, int cr, u64 off, u16 in) 1203d601ea91SFrederic Barrat { 1204d601ea91SFrederic Barrat u64 aligned_off = off & ~0x3L; 1205d601ea91SFrederic Barrat u32 val32, mask, shift; 1206d601ea91SFrederic Barrat int rc; 1207d601ea91SFrederic Barrat 1208d601ea91SFrederic Barrat rc = native_afu_cr_read32(afu, cr, aligned_off, &val32); 1209d601ea91SFrederic Barrat if (rc) 1210d601ea91SFrederic Barrat return rc; 1211d601ea91SFrederic Barrat shift = (off & 0x3) * 8; 1212d601ea91SFrederic Barrat WARN_ON(shift == 24); 1213d601ea91SFrederic Barrat mask = 0xffff << shift; 1214d601ea91SFrederic Barrat val32 = (val32 & ~mask) | (in << shift); 1215d601ea91SFrederic Barrat 1216d601ea91SFrederic Barrat rc = native_afu_cr_write32(afu, cr, aligned_off, val32); 1217d601ea91SFrederic Barrat return rc; 1218d601ea91SFrederic Barrat } 1219d601ea91SFrederic Barrat 1220d601ea91SFrederic Barrat static int native_afu_cr_write8(struct cxl_afu *afu, int cr, u64 off, u8 in) 1221d601ea91SFrederic Barrat { 1222d601ea91SFrederic Barrat u64 aligned_off = off & ~0x3L; 1223d601ea91SFrederic Barrat u32 val32, mask, shift; 1224d601ea91SFrederic Barrat int rc; 1225d601ea91SFrederic Barrat 1226d601ea91SFrederic Barrat rc = native_afu_cr_read32(afu, cr, aligned_off, &val32); 1227d601ea91SFrederic Barrat if (rc) 1228d601ea91SFrederic Barrat return rc; 1229d601ea91SFrederic Barrat shift = (off & 0x3) * 8; 1230d601ea91SFrederic Barrat mask = 0xff << shift; 1231d601ea91SFrederic Barrat val32 = (val32 & ~mask) | (in << shift); 1232d601ea91SFrederic Barrat 1233d601ea91SFrederic Barrat rc = native_afu_cr_write32(afu, cr, aligned_off, val32); 1234d601ea91SFrederic Barrat return rc; 1235d601ea91SFrederic Barrat } 1236d601ea91SFrederic Barrat 12375be587b1SFrederic Barrat const struct cxl_backend_ops cxl_native_ops = { 12385be587b1SFrederic Barrat .module = THIS_MODULE, 12392b04cf31SFrederic Barrat .adapter_reset = cxl_pci_reset, 12402b04cf31SFrederic Barrat .alloc_one_irq = cxl_pci_alloc_one_irq, 12412b04cf31SFrederic Barrat .release_one_irq = cxl_pci_release_one_irq, 12422b04cf31SFrederic Barrat .alloc_irq_ranges = cxl_pci_alloc_irq_ranges, 12432b04cf31SFrederic Barrat .release_irq_ranges = cxl_pci_release_irq_ranges, 12442b04cf31SFrederic Barrat .setup_irq = cxl_pci_setup_irq, 12452b04cf31SFrederic Barrat .handle_psl_slice_error = native_handle_psl_slice_error, 12465be587b1SFrederic Barrat .psl_interrupt = NULL, 12472b04cf31SFrederic Barrat .ack_irq = native_ack_irq, 12482bc79ffcSMichael Neuling .irq_wait = native_irq_wait, 12492b04cf31SFrederic Barrat .attach_process = native_attach_process, 12502b04cf31SFrederic Barrat .detach_process = native_detach_process, 1251292841b0SIan Munsie .update_ivtes = native_update_ivtes, 12524752876cSChristophe Lombard .support_attributes = native_support_attributes, 12535be587b1SFrederic Barrat .link_ok = cxl_adapter_link_ok, 12542b04cf31SFrederic Barrat .release_afu = cxl_pci_release_afu, 12552b04cf31SFrederic Barrat .afu_read_err_buffer = cxl_pci_afu_read_err_buffer, 12562b04cf31SFrederic Barrat .afu_check_and_enable = native_afu_check_and_enable, 12572b04cf31SFrederic Barrat .afu_activate_mode = native_afu_activate_mode, 12582b04cf31SFrederic Barrat .afu_deactivate_mode = native_afu_deactivate_mode, 12592b04cf31SFrederic Barrat .afu_reset = native_afu_reset, 12602b04cf31SFrederic Barrat .afu_cr_read8 = native_afu_cr_read8, 12612b04cf31SFrederic Barrat .afu_cr_read16 = native_afu_cr_read16, 12622b04cf31SFrederic Barrat .afu_cr_read32 = native_afu_cr_read32, 12632b04cf31SFrederic Barrat .afu_cr_read64 = native_afu_cr_read64, 1264d601ea91SFrederic Barrat .afu_cr_write8 = native_afu_cr_write8, 1265d601ea91SFrederic Barrat .afu_cr_write16 = native_afu_cr_write16, 1266d601ea91SFrederic Barrat .afu_cr_write32 = native_afu_cr_write32, 1267d601ea91SFrederic Barrat .read_adapter_vpd = cxl_pci_read_adapter_vpd, 12685be587b1SFrederic Barrat }; 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