1 /* 2 * Copyright 2014 IBM Corp. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 */ 9 10 #include <linux/workqueue.h> 11 #include <linux/sched.h> 12 #include <linux/pid.h> 13 #include <linux/mm.h> 14 #include <linux/moduleparam.h> 15 16 #undef MODULE_PARAM_PREFIX 17 #define MODULE_PARAM_PREFIX "cxl" "." 18 #include <asm/current.h> 19 #include <asm/copro.h> 20 #include <asm/mmu.h> 21 22 #include "cxl.h" 23 24 static bool sste_matches(struct cxl_sste *sste, struct copro_slb *slb) 25 { 26 return ((sste->vsid_data == cpu_to_be64(slb->vsid)) && 27 (sste->esid_data == cpu_to_be64(slb->esid))); 28 } 29 30 /* 31 * This finds a free SSTE for the given SLB, or returns NULL if it's already in 32 * the segment table. 33 */ 34 static struct cxl_sste* find_free_sste(struct cxl_context *ctx, 35 struct copro_slb *slb) 36 { 37 struct cxl_sste *primary, *sste, *ret = NULL; 38 unsigned int mask = (ctx->sst_size >> 7) - 1; /* SSTP0[SegTableSize] */ 39 unsigned int entry; 40 unsigned int hash; 41 42 if (slb->vsid & SLB_VSID_B_1T) 43 hash = (slb->esid >> SID_SHIFT_1T) & mask; 44 else /* 256M */ 45 hash = (slb->esid >> SID_SHIFT) & mask; 46 47 primary = ctx->sstp + (hash << 3); 48 49 for (entry = 0, sste = primary; entry < 8; entry++, sste++) { 50 if (!ret && !(be64_to_cpu(sste->esid_data) & SLB_ESID_V)) 51 ret = sste; 52 if (sste_matches(sste, slb)) 53 return NULL; 54 } 55 if (ret) 56 return ret; 57 58 /* Nothing free, select an entry to cast out */ 59 ret = primary + ctx->sst_lru; 60 ctx->sst_lru = (ctx->sst_lru + 1) & 0x7; 61 62 return ret; 63 } 64 65 static void cxl_load_segment(struct cxl_context *ctx, struct copro_slb *slb) 66 { 67 /* mask is the group index, we search primary and secondary here. */ 68 struct cxl_sste *sste; 69 unsigned long flags; 70 71 spin_lock_irqsave(&ctx->sste_lock, flags); 72 sste = find_free_sste(ctx, slb); 73 if (!sste) 74 goto out_unlock; 75 76 pr_devel("CXL Populating SST[%li]: %#llx %#llx\n", 77 sste - ctx->sstp, slb->vsid, slb->esid); 78 79 sste->vsid_data = cpu_to_be64(slb->vsid); 80 sste->esid_data = cpu_to_be64(slb->esid); 81 out_unlock: 82 spin_unlock_irqrestore(&ctx->sste_lock, flags); 83 } 84 85 static int cxl_fault_segment(struct cxl_context *ctx, struct mm_struct *mm, 86 u64 ea) 87 { 88 struct copro_slb slb = {0,0}; 89 int rc; 90 91 if (!(rc = copro_calculate_slb(mm, ea, &slb))) { 92 cxl_load_segment(ctx, &slb); 93 } 94 95 return rc; 96 } 97 98 static void cxl_ack_ae(struct cxl_context *ctx) 99 { 100 unsigned long flags; 101 102 cxl_ack_irq(ctx, CXL_PSL_TFC_An_AE, 0); 103 104 spin_lock_irqsave(&ctx->lock, flags); 105 ctx->pending_fault = true; 106 ctx->fault_addr = ctx->dar; 107 ctx->fault_dsisr = ctx->dsisr; 108 spin_unlock_irqrestore(&ctx->lock, flags); 109 110 wake_up_all(&ctx->wq); 111 } 112 113 static int cxl_handle_segment_miss(struct cxl_context *ctx, 114 struct mm_struct *mm, u64 ea) 115 { 116 int rc; 117 118 pr_devel("CXL interrupt: Segment fault pe: %i ea: %#llx\n", ctx->pe, ea); 119 120 if ((rc = cxl_fault_segment(ctx, mm, ea))) 121 cxl_ack_ae(ctx); 122 else { 123 124 mb(); /* Order seg table write to TFC MMIO write */ 125 cxl_ack_irq(ctx, CXL_PSL_TFC_An_R, 0); 126 } 127 128 return IRQ_HANDLED; 129 } 130 131 static void cxl_handle_page_fault(struct cxl_context *ctx, 132 struct mm_struct *mm, u64 dsisr, u64 dar) 133 { 134 unsigned flt = 0; 135 int result; 136 unsigned long access, flags, inv_flags = 0; 137 138 if ((result = copro_handle_mm_fault(mm, dar, dsisr, &flt))) { 139 pr_devel("copro_handle_mm_fault failed: %#x\n", result); 140 return cxl_ack_ae(ctx); 141 } 142 143 /* 144 * update_mmu_cache() will not have loaded the hash since current->trap 145 * is not a 0x400 or 0x300, so just call hash_page_mm() here. 146 */ 147 access = _PAGE_PRESENT; 148 if (dsisr & CXL_PSL_DSISR_An_S) 149 access |= _PAGE_RW; 150 if ((!ctx->kernel) || ~(dar & (1ULL << 63))) 151 access |= _PAGE_USER; 152 153 if (dsisr & DSISR_NOHPTE) 154 inv_flags |= HPTE_NOHPTE_UPDATE; 155 156 local_irq_save(flags); 157 hash_page_mm(mm, dar, access, 0x300, inv_flags); 158 local_irq_restore(flags); 159 160 pr_devel("Page fault successfully handled for pe: %i!\n", ctx->pe); 161 cxl_ack_irq(ctx, CXL_PSL_TFC_An_R, 0); 162 } 163 164 void cxl_handle_fault(struct work_struct *fault_work) 165 { 166 struct cxl_context *ctx = 167 container_of(fault_work, struct cxl_context, fault_work); 168 u64 dsisr = ctx->dsisr; 169 u64 dar = ctx->dar; 170 struct task_struct *task; 171 struct mm_struct *mm; 172 173 if (cxl_p2n_read(ctx->afu, CXL_PSL_DSISR_An) != dsisr || 174 cxl_p2n_read(ctx->afu, CXL_PSL_DAR_An) != dar || 175 cxl_p2n_read(ctx->afu, CXL_PSL_PEHandle_An) != ctx->pe) { 176 /* Most likely explanation is harmless - a dedicated process 177 * has detached and these were cleared by the PSL purge, but 178 * warn about it just in case */ 179 dev_notice(&ctx->afu->dev, "cxl_handle_fault: Translation fault regs changed\n"); 180 return; 181 } 182 183 pr_devel("CXL BOTTOM HALF handling fault for afu pe: %i. " 184 "DSISR: %#llx DAR: %#llx\n", ctx->pe, dsisr, dar); 185 186 if (!(task = get_pid_task(ctx->pid, PIDTYPE_PID))) { 187 pr_devel("cxl_handle_fault unable to get task %i\n", 188 pid_nr(ctx->pid)); 189 cxl_ack_ae(ctx); 190 return; 191 } 192 if (!(mm = get_task_mm(task))) { 193 pr_devel("cxl_handle_fault unable to get mm %i\n", 194 pid_nr(ctx->pid)); 195 cxl_ack_ae(ctx); 196 goto out; 197 } 198 199 if (dsisr & CXL_PSL_DSISR_An_DS) 200 cxl_handle_segment_miss(ctx, mm, dar); 201 else if (dsisr & CXL_PSL_DSISR_An_DM) 202 cxl_handle_page_fault(ctx, mm, dsisr, dar); 203 else 204 WARN(1, "cxl_handle_fault has nothing to handle\n"); 205 206 mmput(mm); 207 out: 208 put_task_struct(task); 209 } 210 211 static void cxl_prefault_one(struct cxl_context *ctx, u64 ea) 212 { 213 int rc; 214 struct task_struct *task; 215 struct mm_struct *mm; 216 217 if (!(task = get_pid_task(ctx->pid, PIDTYPE_PID))) { 218 pr_devel("cxl_prefault_one unable to get task %i\n", 219 pid_nr(ctx->pid)); 220 return; 221 } 222 if (!(mm = get_task_mm(task))) { 223 pr_devel("cxl_prefault_one unable to get mm %i\n", 224 pid_nr(ctx->pid)); 225 put_task_struct(task); 226 return; 227 } 228 229 rc = cxl_fault_segment(ctx, mm, ea); 230 231 mmput(mm); 232 put_task_struct(task); 233 } 234 235 static u64 next_segment(u64 ea, u64 vsid) 236 { 237 if (vsid & SLB_VSID_B_1T) 238 ea |= (1ULL << 40) - 1; 239 else 240 ea |= (1ULL << 28) - 1; 241 242 return ea + 1; 243 } 244 245 static void cxl_prefault_vma(struct cxl_context *ctx) 246 { 247 u64 ea, last_esid = 0; 248 struct copro_slb slb; 249 struct vm_area_struct *vma; 250 int rc; 251 struct task_struct *task; 252 struct mm_struct *mm; 253 254 if (!(task = get_pid_task(ctx->pid, PIDTYPE_PID))) { 255 pr_devel("cxl_prefault_vma unable to get task %i\n", 256 pid_nr(ctx->pid)); 257 return; 258 } 259 if (!(mm = get_task_mm(task))) { 260 pr_devel("cxl_prefault_vm unable to get mm %i\n", 261 pid_nr(ctx->pid)); 262 goto out1; 263 } 264 265 down_read(&mm->mmap_sem); 266 for (vma = mm->mmap; vma; vma = vma->vm_next) { 267 for (ea = vma->vm_start; ea < vma->vm_end; 268 ea = next_segment(ea, slb.vsid)) { 269 rc = copro_calculate_slb(mm, ea, &slb); 270 if (rc) 271 continue; 272 273 if (last_esid == slb.esid) 274 continue; 275 276 cxl_load_segment(ctx, &slb); 277 last_esid = slb.esid; 278 } 279 } 280 up_read(&mm->mmap_sem); 281 282 mmput(mm); 283 out1: 284 put_task_struct(task); 285 } 286 287 void cxl_prefault(struct cxl_context *ctx, u64 wed) 288 { 289 switch (ctx->afu->prefault_mode) { 290 case CXL_PREFAULT_WED: 291 cxl_prefault_one(ctx, wed); 292 break; 293 case CXL_PREFAULT_ALL: 294 cxl_prefault_vma(ctx); 295 break; 296 default: 297 break; 298 } 299 } 300