1 /* 2 * Copyright 2014 IBM Corp. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 */ 9 10 #ifndef _CXL_H_ 11 #define _CXL_H_ 12 13 #include <linux/interrupt.h> 14 #include <linux/semaphore.h> 15 #include <linux/device.h> 16 #include <linux/types.h> 17 #include <linux/cdev.h> 18 #include <linux/pid.h> 19 #include <linux/io.h> 20 #include <linux/pci.h> 21 #include <asm/cputable.h> 22 #include <asm/mmu.h> 23 #include <asm/reg.h> 24 #include <misc/cxl.h> 25 26 #include <uapi/misc/cxl.h> 27 28 extern uint cxl_verbose; 29 30 #define CXL_TIMEOUT 5 31 32 /* 33 * Bump version each time a user API change is made, whether it is 34 * backwards compatible ot not. 35 */ 36 #define CXL_API_VERSION 1 37 #define CXL_API_VERSION_COMPATIBLE 1 38 39 /* 40 * Opaque types to avoid accidentally passing registers for the wrong MMIO 41 * 42 * At the end of the day, I'm not married to using typedef here, but it might 43 * (and has!) help avoid bugs like mixing up CXL_PSL_CtxTime and 44 * CXL_PSL_CtxTime_An, or calling cxl_p1n_write instead of cxl_p1_write. 45 * 46 * I'm quite happy if these are changed back to #defines before upstreaming, it 47 * should be little more than a regexp search+replace operation in this file. 48 */ 49 typedef struct { 50 const int x; 51 } cxl_p1_reg_t; 52 typedef struct { 53 const int x; 54 } cxl_p1n_reg_t; 55 typedef struct { 56 const int x; 57 } cxl_p2n_reg_t; 58 #define cxl_reg_off(reg) \ 59 (reg.x) 60 61 /* Memory maps. Ref CXL Appendix A */ 62 63 /* PSL Privilege 1 Memory Map */ 64 /* Configuration and Control area */ 65 static const cxl_p1_reg_t CXL_PSL_CtxTime = {0x0000}; 66 static const cxl_p1_reg_t CXL_PSL_ErrIVTE = {0x0008}; 67 static const cxl_p1_reg_t CXL_PSL_KEY1 = {0x0010}; 68 static const cxl_p1_reg_t CXL_PSL_KEY2 = {0x0018}; 69 static const cxl_p1_reg_t CXL_PSL_Control = {0x0020}; 70 /* Downloading */ 71 static const cxl_p1_reg_t CXL_PSL_DLCNTL = {0x0060}; 72 static const cxl_p1_reg_t CXL_PSL_DLADDR = {0x0068}; 73 74 /* PSL Lookaside Buffer Management Area */ 75 static const cxl_p1_reg_t CXL_PSL_LBISEL = {0x0080}; 76 static const cxl_p1_reg_t CXL_PSL_SLBIE = {0x0088}; 77 static const cxl_p1_reg_t CXL_PSL_SLBIA = {0x0090}; 78 static const cxl_p1_reg_t CXL_PSL_TLBIE = {0x00A0}; 79 static const cxl_p1_reg_t CXL_PSL_TLBIA = {0x00A8}; 80 static const cxl_p1_reg_t CXL_PSL_AFUSEL = {0x00B0}; 81 82 /* 0x00C0:7EFF Implementation dependent area */ 83 static const cxl_p1_reg_t CXL_PSL_FIR1 = {0x0100}; 84 static const cxl_p1_reg_t CXL_PSL_FIR2 = {0x0108}; 85 static const cxl_p1_reg_t CXL_PSL_VERSION = {0x0118}; 86 static const cxl_p1_reg_t CXL_PSL_RESLCKTO = {0x0128}; 87 static const cxl_p1_reg_t CXL_PSL_FIR_CNTL = {0x0148}; 88 static const cxl_p1_reg_t CXL_PSL_DSNDCTL = {0x0150}; 89 static const cxl_p1_reg_t CXL_PSL_SNWRALLOC = {0x0158}; 90 static const cxl_p1_reg_t CXL_PSL_TRACE = {0x0170}; 91 /* 0x7F00:7FFF Reserved PCIe MSI-X Pending Bit Array area */ 92 /* 0x8000:FFFF Reserved PCIe MSI-X Table Area */ 93 94 /* PSL Slice Privilege 1 Memory Map */ 95 /* Configuration Area */ 96 static const cxl_p1n_reg_t CXL_PSL_SR_An = {0x00}; 97 static const cxl_p1n_reg_t CXL_PSL_LPID_An = {0x08}; 98 static const cxl_p1n_reg_t CXL_PSL_AMBAR_An = {0x10}; 99 static const cxl_p1n_reg_t CXL_PSL_SPOffset_An = {0x18}; 100 static const cxl_p1n_reg_t CXL_PSL_ID_An = {0x20}; 101 static const cxl_p1n_reg_t CXL_PSL_SERR_An = {0x28}; 102 /* Memory Management and Lookaside Buffer Management */ 103 static const cxl_p1n_reg_t CXL_PSL_SDR_An = {0x30}; 104 static const cxl_p1n_reg_t CXL_PSL_AMOR_An = {0x38}; 105 /* Pointer Area */ 106 static const cxl_p1n_reg_t CXL_HAURP_An = {0x80}; 107 static const cxl_p1n_reg_t CXL_PSL_SPAP_An = {0x88}; 108 static const cxl_p1n_reg_t CXL_PSL_LLCMD_An = {0x90}; 109 /* Control Area */ 110 static const cxl_p1n_reg_t CXL_PSL_SCNTL_An = {0xA0}; 111 static const cxl_p1n_reg_t CXL_PSL_CtxTime_An = {0xA8}; 112 static const cxl_p1n_reg_t CXL_PSL_IVTE_Offset_An = {0xB0}; 113 static const cxl_p1n_reg_t CXL_PSL_IVTE_Limit_An = {0xB8}; 114 /* 0xC0:FF Implementation Dependent Area */ 115 static const cxl_p1n_reg_t CXL_PSL_FIR_SLICE_An = {0xC0}; 116 static const cxl_p1n_reg_t CXL_AFU_DEBUG_An = {0xC8}; 117 static const cxl_p1n_reg_t CXL_PSL_APCALLOC_A = {0xD0}; 118 static const cxl_p1n_reg_t CXL_PSL_COALLOC_A = {0xD8}; 119 static const cxl_p1n_reg_t CXL_PSL_RXCTL_A = {0xE0}; 120 static const cxl_p1n_reg_t CXL_PSL_SLICE_TRACE = {0xE8}; 121 122 /* PSL Slice Privilege 2 Memory Map */ 123 /* Configuration and Control Area */ 124 static const cxl_p2n_reg_t CXL_PSL_PID_TID_An = {0x000}; 125 static const cxl_p2n_reg_t CXL_CSRP_An = {0x008}; 126 static const cxl_p2n_reg_t CXL_AURP0_An = {0x010}; 127 static const cxl_p2n_reg_t CXL_AURP1_An = {0x018}; 128 static const cxl_p2n_reg_t CXL_SSTP0_An = {0x020}; 129 static const cxl_p2n_reg_t CXL_SSTP1_An = {0x028}; 130 static const cxl_p2n_reg_t CXL_PSL_AMR_An = {0x030}; 131 /* Segment Lookaside Buffer Management */ 132 static const cxl_p2n_reg_t CXL_SLBIE_An = {0x040}; 133 static const cxl_p2n_reg_t CXL_SLBIA_An = {0x048}; 134 static const cxl_p2n_reg_t CXL_SLBI_Select_An = {0x050}; 135 /* Interrupt Registers */ 136 static const cxl_p2n_reg_t CXL_PSL_DSISR_An = {0x060}; 137 static const cxl_p2n_reg_t CXL_PSL_DAR_An = {0x068}; 138 static const cxl_p2n_reg_t CXL_PSL_DSR_An = {0x070}; 139 static const cxl_p2n_reg_t CXL_PSL_TFC_An = {0x078}; 140 static const cxl_p2n_reg_t CXL_PSL_PEHandle_An = {0x080}; 141 static const cxl_p2n_reg_t CXL_PSL_ErrStat_An = {0x088}; 142 /* AFU Registers */ 143 static const cxl_p2n_reg_t CXL_AFU_Cntl_An = {0x090}; 144 static const cxl_p2n_reg_t CXL_AFU_ERR_An = {0x098}; 145 /* Work Element Descriptor */ 146 static const cxl_p2n_reg_t CXL_PSL_WED_An = {0x0A0}; 147 /* 0x0C0:FFF Implementation Dependent Area */ 148 149 #define CXL_PSL_SPAP_Addr 0x0ffffffffffff000ULL 150 #define CXL_PSL_SPAP_Size 0x0000000000000ff0ULL 151 #define CXL_PSL_SPAP_Size_Shift 4 152 #define CXL_PSL_SPAP_V 0x0000000000000001ULL 153 154 /****** CXL_PSL_DLCNTL *****************************************************/ 155 #define CXL_PSL_DLCNTL_D (0x1ull << (63-28)) 156 #define CXL_PSL_DLCNTL_C (0x1ull << (63-29)) 157 #define CXL_PSL_DLCNTL_E (0x1ull << (63-30)) 158 #define CXL_PSL_DLCNTL_S (0x1ull << (63-31)) 159 #define CXL_PSL_DLCNTL_CE (CXL_PSL_DLCNTL_C | CXL_PSL_DLCNTL_E) 160 #define CXL_PSL_DLCNTL_DCES (CXL_PSL_DLCNTL_D | CXL_PSL_DLCNTL_CE | CXL_PSL_DLCNTL_S) 161 162 /****** CXL_PSL_SR_An ******************************************************/ 163 #define CXL_PSL_SR_An_SF MSR_SF /* 64bit */ 164 #define CXL_PSL_SR_An_TA (1ull << (63-1)) /* Tags active, GA1: 0 */ 165 #define CXL_PSL_SR_An_HV MSR_HV /* Hypervisor, GA1: 0 */ 166 #define CXL_PSL_SR_An_PR MSR_PR /* Problem state, GA1: 1 */ 167 #define CXL_PSL_SR_An_ISL (1ull << (63-53)) /* Ignore Segment Large Page */ 168 #define CXL_PSL_SR_An_TC (1ull << (63-54)) /* Page Table secondary hash */ 169 #define CXL_PSL_SR_An_US (1ull << (63-56)) /* User state, GA1: X */ 170 #define CXL_PSL_SR_An_SC (1ull << (63-58)) /* Segment Table secondary hash */ 171 #define CXL_PSL_SR_An_R MSR_DR /* Relocate, GA1: 1 */ 172 #define CXL_PSL_SR_An_MP (1ull << (63-62)) /* Master Process */ 173 #define CXL_PSL_SR_An_LE (1ull << (63-63)) /* Little Endian */ 174 175 /****** CXL_PSL_LLCMD_An ****************************************************/ 176 #define CXL_LLCMD_TERMINATE 0x0001000000000000ULL 177 #define CXL_LLCMD_REMOVE 0x0002000000000000ULL 178 #define CXL_LLCMD_SUSPEND 0x0003000000000000ULL 179 #define CXL_LLCMD_RESUME 0x0004000000000000ULL 180 #define CXL_LLCMD_ADD 0x0005000000000000ULL 181 #define CXL_LLCMD_UPDATE 0x0006000000000000ULL 182 #define CXL_LLCMD_HANDLE_MASK 0x000000000000ffffULL 183 184 /****** CXL_PSL_ID_An ****************************************************/ 185 #define CXL_PSL_ID_An_F (1ull << (63-31)) 186 #define CXL_PSL_ID_An_L (1ull << (63-30)) 187 188 /****** CXL_PSL_SCNTL_An ****************************************************/ 189 #define CXL_PSL_SCNTL_An_CR (0x1ull << (63-15)) 190 /* Programming Modes: */ 191 #define CXL_PSL_SCNTL_An_PM_MASK (0xffffull << (63-31)) 192 #define CXL_PSL_SCNTL_An_PM_Shared (0x0000ull << (63-31)) 193 #define CXL_PSL_SCNTL_An_PM_OS (0x0001ull << (63-31)) 194 #define CXL_PSL_SCNTL_An_PM_Process (0x0002ull << (63-31)) 195 #define CXL_PSL_SCNTL_An_PM_AFU (0x0004ull << (63-31)) 196 #define CXL_PSL_SCNTL_An_PM_AFU_PBT (0x0104ull << (63-31)) 197 /* Purge Status (ro) */ 198 #define CXL_PSL_SCNTL_An_Ps_MASK (0x3ull << (63-39)) 199 #define CXL_PSL_SCNTL_An_Ps_Pending (0x1ull << (63-39)) 200 #define CXL_PSL_SCNTL_An_Ps_Complete (0x3ull << (63-39)) 201 /* Purge */ 202 #define CXL_PSL_SCNTL_An_Pc (0x1ull << (63-48)) 203 /* Suspend Status (ro) */ 204 #define CXL_PSL_SCNTL_An_Ss_MASK (0x3ull << (63-55)) 205 #define CXL_PSL_SCNTL_An_Ss_Pending (0x1ull << (63-55)) 206 #define CXL_PSL_SCNTL_An_Ss_Complete (0x3ull << (63-55)) 207 /* Suspend Control */ 208 #define CXL_PSL_SCNTL_An_Sc (0x1ull << (63-63)) 209 210 /* AFU Slice Enable Status (ro) */ 211 #define CXL_AFU_Cntl_An_ES_MASK (0x7ull << (63-2)) 212 #define CXL_AFU_Cntl_An_ES_Disabled (0x0ull << (63-2)) 213 #define CXL_AFU_Cntl_An_ES_Enabled (0x4ull << (63-2)) 214 /* AFU Slice Enable */ 215 #define CXL_AFU_Cntl_An_E (0x1ull << (63-3)) 216 /* AFU Slice Reset status (ro) */ 217 #define CXL_AFU_Cntl_An_RS_MASK (0x3ull << (63-5)) 218 #define CXL_AFU_Cntl_An_RS_Pending (0x1ull << (63-5)) 219 #define CXL_AFU_Cntl_An_RS_Complete (0x2ull << (63-5)) 220 /* AFU Slice Reset */ 221 #define CXL_AFU_Cntl_An_RA (0x1ull << (63-7)) 222 223 /****** CXL_SSTP0/1_An ******************************************************/ 224 /* These top bits are for the segment that CONTAINS the segment table */ 225 #define CXL_SSTP0_An_B_SHIFT SLB_VSID_SSIZE_SHIFT 226 #define CXL_SSTP0_An_KS (1ull << (63-2)) 227 #define CXL_SSTP0_An_KP (1ull << (63-3)) 228 #define CXL_SSTP0_An_N (1ull << (63-4)) 229 #define CXL_SSTP0_An_L (1ull << (63-5)) 230 #define CXL_SSTP0_An_C (1ull << (63-6)) 231 #define CXL_SSTP0_An_TA (1ull << (63-7)) 232 #define CXL_SSTP0_An_LP_SHIFT (63-9) /* 2 Bits */ 233 /* And finally, the virtual address & size of the segment table: */ 234 #define CXL_SSTP0_An_SegTableSize_SHIFT (63-31) /* 12 Bits */ 235 #define CXL_SSTP0_An_SegTableSize_MASK \ 236 (((1ull << 12) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT) 237 #define CXL_SSTP0_An_STVA_U_MASK ((1ull << (63-49))-1) 238 #define CXL_SSTP1_An_STVA_L_MASK (~((1ull << (63-55))-1)) 239 #define CXL_SSTP1_An_V (1ull << (63-63)) 240 241 /****** CXL_PSL_SLBIE_[An] **************************************************/ 242 /* write: */ 243 #define CXL_SLBIE_C PPC_BIT(36) /* Class */ 244 #define CXL_SLBIE_SS PPC_BITMASK(37, 38) /* Segment Size */ 245 #define CXL_SLBIE_SS_SHIFT PPC_BITLSHIFT(38) 246 #define CXL_SLBIE_TA PPC_BIT(38) /* Tags Active */ 247 /* read: */ 248 #define CXL_SLBIE_MAX PPC_BITMASK(24, 31) 249 #define CXL_SLBIE_PENDING PPC_BITMASK(56, 63) 250 251 /****** Common to all CXL_TLBIA/SLBIA_[An] **********************************/ 252 #define CXL_TLB_SLB_P (1ull) /* Pending (read) */ 253 254 /****** Common to all CXL_TLB/SLB_IA/IE_[An] registers **********************/ 255 #define CXL_TLB_SLB_IQ_ALL (0ull) /* Inv qualifier */ 256 #define CXL_TLB_SLB_IQ_LPID (1ull) /* Inv qualifier */ 257 #define CXL_TLB_SLB_IQ_LPIDPID (3ull) /* Inv qualifier */ 258 259 /****** CXL_PSL_AFUSEL ******************************************************/ 260 #define CXL_PSL_AFUSEL_A (1ull << (63-55)) /* Adapter wide invalidates affect all AFUs */ 261 262 /****** CXL_PSL_DSISR_An ****************************************************/ 263 #define CXL_PSL_DSISR_An_DS (1ull << (63-0)) /* Segment not found */ 264 #define CXL_PSL_DSISR_An_DM (1ull << (63-1)) /* PTE not found (See also: M) or protection fault */ 265 #define CXL_PSL_DSISR_An_ST (1ull << (63-2)) /* Segment Table PTE not found */ 266 #define CXL_PSL_DSISR_An_UR (1ull << (63-3)) /* AURP PTE not found */ 267 #define CXL_PSL_DSISR_TRANS (CXL_PSL_DSISR_An_DS | CXL_PSL_DSISR_An_DM | CXL_PSL_DSISR_An_ST | CXL_PSL_DSISR_An_UR) 268 #define CXL_PSL_DSISR_An_PE (1ull << (63-4)) /* PSL Error (implementation specific) */ 269 #define CXL_PSL_DSISR_An_AE (1ull << (63-5)) /* AFU Error */ 270 #define CXL_PSL_DSISR_An_OC (1ull << (63-6)) /* OS Context Warning */ 271 /* NOTE: Bits 32:63 are undefined if DSISR[DS] = 1 */ 272 #define CXL_PSL_DSISR_An_M DSISR_NOHPTE /* PTE not found */ 273 #define CXL_PSL_DSISR_An_P DSISR_PROTFAULT /* Storage protection violation */ 274 #define CXL_PSL_DSISR_An_A (1ull << (63-37)) /* AFU lock access to write through or cache inhibited storage */ 275 #define CXL_PSL_DSISR_An_S DSISR_ISSTORE /* Access was afu_wr or afu_zero */ 276 #define CXL_PSL_DSISR_An_K DSISR_KEYFAULT /* Access not permitted by virtual page class key protection */ 277 278 /****** CXL_PSL_TFC_An ******************************************************/ 279 #define CXL_PSL_TFC_An_A (1ull << (63-28)) /* Acknowledge non-translation fault */ 280 #define CXL_PSL_TFC_An_C (1ull << (63-29)) /* Continue (abort transaction) */ 281 #define CXL_PSL_TFC_An_AE (1ull << (63-30)) /* Restart PSL with address error */ 282 #define CXL_PSL_TFC_An_R (1ull << (63-31)) /* Restart PSL transaction */ 283 284 /* cxl_process_element->software_status */ 285 #define CXL_PE_SOFTWARE_STATE_V (1ul << (31 - 0)) /* Valid */ 286 #define CXL_PE_SOFTWARE_STATE_C (1ul << (31 - 29)) /* Complete */ 287 #define CXL_PE_SOFTWARE_STATE_S (1ul << (31 - 30)) /* Suspend */ 288 #define CXL_PE_SOFTWARE_STATE_T (1ul << (31 - 31)) /* Terminate */ 289 290 /* SPA->sw_command_status */ 291 #define CXL_SPA_SW_CMD_MASK 0xffff000000000000ULL 292 #define CXL_SPA_SW_CMD_TERMINATE 0x0001000000000000ULL 293 #define CXL_SPA_SW_CMD_REMOVE 0x0002000000000000ULL 294 #define CXL_SPA_SW_CMD_SUSPEND 0x0003000000000000ULL 295 #define CXL_SPA_SW_CMD_RESUME 0x0004000000000000ULL 296 #define CXL_SPA_SW_CMD_ADD 0x0005000000000000ULL 297 #define CXL_SPA_SW_CMD_UPDATE 0x0006000000000000ULL 298 #define CXL_SPA_SW_STATE_MASK 0x0000ffff00000000ULL 299 #define CXL_SPA_SW_STATE_TERMINATED 0x0000000100000000ULL 300 #define CXL_SPA_SW_STATE_REMOVED 0x0000000200000000ULL 301 #define CXL_SPA_SW_STATE_SUSPENDED 0x0000000300000000ULL 302 #define CXL_SPA_SW_STATE_RESUMED 0x0000000400000000ULL 303 #define CXL_SPA_SW_STATE_ADDED 0x0000000500000000ULL 304 #define CXL_SPA_SW_STATE_UPDATED 0x0000000600000000ULL 305 #define CXL_SPA_SW_PSL_ID_MASK 0x00000000ffff0000ULL 306 #define CXL_SPA_SW_LINK_MASK 0x000000000000ffffULL 307 308 #define CXL_MAX_SLICES 4 309 #define MAX_AFU_MMIO_REGS 3 310 311 #define CXL_MODE_DEDICATED 0x1 312 #define CXL_MODE_DIRECTED 0x2 313 #define CXL_MODE_TIME_SLICED 0x4 314 #define CXL_SUPPORTED_MODES (CXL_MODE_DEDICATED | CXL_MODE_DIRECTED) 315 316 enum cxl_context_status { 317 CLOSED, 318 OPENED, 319 STARTED 320 }; 321 322 enum prefault_modes { 323 CXL_PREFAULT_NONE, 324 CXL_PREFAULT_WED, 325 CXL_PREFAULT_ALL, 326 }; 327 328 struct cxl_sste { 329 __be64 esid_data; 330 __be64 vsid_data; 331 }; 332 333 #define to_cxl_adapter(d) container_of(d, struct cxl, dev) 334 #define to_cxl_afu(d) container_of(d, struct cxl_afu, dev) 335 336 struct cxl_afu { 337 irq_hw_number_t psl_hwirq; 338 irq_hw_number_t serr_hwirq; 339 unsigned int serr_virq; 340 void __iomem *p1n_mmio; 341 void __iomem *p2n_mmio; 342 phys_addr_t psn_phys; 343 u64 pp_offset; 344 u64 pp_size; 345 void __iomem *afu_desc_mmio; 346 struct cxl *adapter; 347 struct device dev; 348 struct cdev afu_cdev_s, afu_cdev_m, afu_cdev_d; 349 struct device *chardev_s, *chardev_m, *chardev_d; 350 struct idr contexts_idr; 351 struct dentry *debugfs; 352 spinlock_t contexts_lock; 353 struct mutex spa_mutex; 354 spinlock_t afu_cntl_lock; 355 356 /* 357 * Only the first part of the SPA is used for the process element 358 * linked list. The only other part that software needs to worry about 359 * is sw_command_status, which we store a separate pointer to. 360 * Everything else in the SPA is only used by hardware 361 */ 362 struct cxl_process_element *spa; 363 __be64 *sw_command_status; 364 unsigned int spa_size; 365 int spa_order; 366 int spa_max_procs; 367 unsigned int psl_virq; 368 369 int pp_irqs; 370 int irqs_max; 371 int num_procs; 372 int max_procs_virtualised; 373 int slice; 374 int modes_supported; 375 int current_mode; 376 enum prefault_modes prefault_mode; 377 bool psa; 378 bool pp_psa; 379 bool enabled; 380 }; 381 382 /* 383 * This is a cxl context. If the PSL is in dedicated mode, there will be one 384 * of these per AFU. If in AFU directed there can be lots of these. 385 */ 386 struct cxl_context { 387 struct cxl_afu *afu; 388 389 /* Problem state MMIO */ 390 phys_addr_t psn_phys; 391 u64 psn_size; 392 393 spinlock_t sste_lock; /* Protects segment table entries */ 394 struct cxl_sste *sstp; 395 u64 sstp0, sstp1; 396 unsigned int sst_size, sst_lru; 397 398 wait_queue_head_t wq; 399 struct pid *pid; 400 spinlock_t lock; /* Protects pending_irq_mask, pending_fault and fault_addr */ 401 /* Only used in PR mode */ 402 u64 process_token; 403 404 unsigned long *irq_bitmap; /* Accessed from IRQ context */ 405 struct cxl_irq_ranges irqs; 406 u64 fault_addr; 407 u64 fault_dsisr; 408 u64 afu_err; 409 410 /* 411 * This status and it's lock pretects start and detach context 412 * from racing. It also prevents detach from racing with 413 * itself 414 */ 415 enum cxl_context_status status; 416 struct mutex status_mutex; 417 418 419 /* XXX: Is it possible to need multiple work items at once? */ 420 struct work_struct fault_work; 421 u64 dsisr; 422 u64 dar; 423 424 struct cxl_process_element *elem; 425 426 int pe; /* process element handle */ 427 u32 irq_count; 428 bool pe_inserted; 429 bool master; 430 bool kernel; 431 bool pending_irq; 432 bool pending_fault; 433 bool pending_afu_err; 434 }; 435 436 struct cxl { 437 void __iomem *p1_mmio; 438 void __iomem *p2_mmio; 439 irq_hw_number_t err_hwirq; 440 unsigned int err_virq; 441 spinlock_t afu_list_lock; 442 struct cxl_afu *afu[CXL_MAX_SLICES]; 443 struct device dev; 444 struct dentry *trace; 445 struct dentry *psl_err_chk; 446 struct dentry *debugfs; 447 struct bin_attribute cxl_attr; 448 int adapter_num; 449 int user_irqs; 450 u64 afu_desc_off; 451 u64 afu_desc_size; 452 u64 ps_off; 453 u64 ps_size; 454 u16 psl_rev; 455 u16 base_image; 456 u8 vsec_status; 457 u8 caia_major; 458 u8 caia_minor; 459 u8 slices; 460 bool user_image_loaded; 461 bool perst_loads_image; 462 bool perst_select_user; 463 }; 464 465 int cxl_alloc_one_irq(struct cxl *adapter); 466 void cxl_release_one_irq(struct cxl *adapter, int hwirq); 467 int cxl_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num); 468 void cxl_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter); 469 int cxl_setup_irq(struct cxl *adapter, unsigned int hwirq, unsigned int virq); 470 471 /* common == phyp + powernv */ 472 struct cxl_process_element_common { 473 __be32 tid; 474 __be32 pid; 475 __be64 csrp; 476 __be64 aurp0; 477 __be64 aurp1; 478 __be64 sstp0; 479 __be64 sstp1; 480 __be64 amr; 481 u8 reserved3[4]; 482 __be64 wed; 483 } __packed; 484 485 /* just powernv */ 486 struct cxl_process_element { 487 __be64 sr; 488 __be64 SPOffset; 489 __be64 sdr; 490 __be64 haurp; 491 __be32 ctxtime; 492 __be16 ivte_offsets[4]; 493 __be16 ivte_ranges[4]; 494 __be32 lpid; 495 struct cxl_process_element_common common; 496 __be32 software_state; 497 } __packed; 498 499 static inline void __iomem *_cxl_p1_addr(struct cxl *cxl, cxl_p1_reg_t reg) 500 { 501 WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE)); 502 return cxl->p1_mmio + cxl_reg_off(reg); 503 } 504 505 #define cxl_p1_write(cxl, reg, val) \ 506 out_be64(_cxl_p1_addr(cxl, reg), val) 507 #define cxl_p1_read(cxl, reg) \ 508 in_be64(_cxl_p1_addr(cxl, reg)) 509 510 static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg) 511 { 512 WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE)); 513 return afu->p1n_mmio + cxl_reg_off(reg); 514 } 515 516 #define cxl_p1n_write(afu, reg, val) \ 517 out_be64(_cxl_p1n_addr(afu, reg), val) 518 #define cxl_p1n_read(afu, reg) \ 519 in_be64(_cxl_p1n_addr(afu, reg)) 520 521 static inline void __iomem *_cxl_p2n_addr(struct cxl_afu *afu, cxl_p2n_reg_t reg) 522 { 523 return afu->p2n_mmio + cxl_reg_off(reg); 524 } 525 526 #define cxl_p2n_write(afu, reg, val) \ 527 out_be64(_cxl_p2n_addr(afu, reg), val) 528 #define cxl_p2n_read(afu, reg) \ 529 in_be64(_cxl_p2n_addr(afu, reg)) 530 531 struct cxl_calls { 532 void (*cxl_slbia)(struct mm_struct *mm); 533 struct module *owner; 534 }; 535 int register_cxl_calls(struct cxl_calls *calls); 536 void unregister_cxl_calls(struct cxl_calls *calls); 537 538 int cxl_alloc_adapter_nr(struct cxl *adapter); 539 void cxl_remove_adapter_nr(struct cxl *adapter); 540 541 int cxl_file_init(void); 542 void cxl_file_exit(void); 543 int cxl_register_adapter(struct cxl *adapter); 544 int cxl_register_afu(struct cxl_afu *afu); 545 int cxl_chardev_d_afu_add(struct cxl_afu *afu); 546 int cxl_chardev_m_afu_add(struct cxl_afu *afu); 547 int cxl_chardev_s_afu_add(struct cxl_afu *afu); 548 void cxl_chardev_afu_remove(struct cxl_afu *afu); 549 550 void cxl_context_detach_all(struct cxl_afu *afu); 551 void cxl_context_free(struct cxl_context *ctx); 552 void cxl_context_detach(struct cxl_context *ctx); 553 554 int cxl_sysfs_adapter_add(struct cxl *adapter); 555 void cxl_sysfs_adapter_remove(struct cxl *adapter); 556 int cxl_sysfs_afu_add(struct cxl_afu *afu); 557 void cxl_sysfs_afu_remove(struct cxl_afu *afu); 558 int cxl_sysfs_afu_m_add(struct cxl_afu *afu); 559 void cxl_sysfs_afu_m_remove(struct cxl_afu *afu); 560 561 int cxl_afu_activate_mode(struct cxl_afu *afu, int mode); 562 int _cxl_afu_deactivate_mode(struct cxl_afu *afu, int mode); 563 int cxl_afu_deactivate_mode(struct cxl_afu *afu); 564 int cxl_afu_select_best_mode(struct cxl_afu *afu); 565 566 unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq, 567 irq_handler_t handler, void *cookie); 568 void cxl_unmap_irq(unsigned int virq, void *cookie); 569 int cxl_register_psl_irq(struct cxl_afu *afu); 570 void cxl_release_psl_irq(struct cxl_afu *afu); 571 int cxl_register_psl_err_irq(struct cxl *adapter); 572 void cxl_release_psl_err_irq(struct cxl *adapter); 573 int cxl_register_serr_irq(struct cxl_afu *afu); 574 void cxl_release_serr_irq(struct cxl_afu *afu); 575 int afu_register_irqs(struct cxl_context *ctx, u32 count); 576 void afu_release_irqs(struct cxl_context *ctx); 577 irqreturn_t cxl_slice_irq_err(int irq, void *data); 578 579 int cxl_debugfs_init(void); 580 void cxl_debugfs_exit(void); 581 int cxl_debugfs_adapter_add(struct cxl *adapter); 582 void cxl_debugfs_adapter_remove(struct cxl *adapter); 583 int cxl_debugfs_afu_add(struct cxl_afu *afu); 584 void cxl_debugfs_afu_remove(struct cxl_afu *afu); 585 586 void cxl_handle_fault(struct work_struct *work); 587 void cxl_prefault(struct cxl_context *ctx, u64 wed); 588 589 struct cxl *get_cxl_adapter(int num); 590 int cxl_alloc_sst(struct cxl_context *ctx); 591 592 void init_cxl_native(void); 593 594 struct cxl_context *cxl_context_alloc(void); 595 int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master); 596 void cxl_context_free(struct cxl_context *ctx); 597 int cxl_context_iomap(struct cxl_context *ctx, struct vm_area_struct *vma); 598 599 /* This matches the layout of the H_COLLECT_CA_INT_INFO retbuf */ 600 struct cxl_irq_info { 601 u64 dsisr; 602 u64 dar; 603 u64 dsr; 604 u32 pid; 605 u32 tid; 606 u64 afu_err; 607 u64 errstat; 608 u64 padding[3]; /* to match the expected retbuf size for plpar_hcall9 */ 609 }; 610 611 int cxl_attach_process(struct cxl_context *ctx, bool kernel, u64 wed, 612 u64 amr); 613 int cxl_detach_process(struct cxl_context *ctx); 614 615 int cxl_get_irq(struct cxl_context *ctx, struct cxl_irq_info *info); 616 int cxl_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask); 617 618 int cxl_check_error(struct cxl_afu *afu); 619 int cxl_afu_slbia(struct cxl_afu *afu); 620 int cxl_tlb_slb_invalidate(struct cxl *adapter); 621 int cxl_afu_disable(struct cxl_afu *afu); 622 int cxl_afu_reset(struct cxl_afu *afu); 623 int cxl_psl_purge(struct cxl_afu *afu); 624 625 void cxl_stop_trace(struct cxl *cxl); 626 627 extern struct pci_driver cxl_pci_driver; 628 629 #endif 630