1 /* 2 * Copyright 2014 IBM Corp. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 */ 9 10 #ifndef _CXL_H_ 11 #define _CXL_H_ 12 13 #include <linux/interrupt.h> 14 #include <linux/semaphore.h> 15 #include <linux/device.h> 16 #include <linux/types.h> 17 #include <linux/cdev.h> 18 #include <linux/pid.h> 19 #include <linux/io.h> 20 #include <linux/pci.h> 21 #include <linux/fs.h> 22 #include <asm/cputable.h> 23 #include <asm/mmu.h> 24 #include <asm/reg.h> 25 #include <misc/cxl-base.h> 26 27 #include <uapi/misc/cxl.h> 28 29 extern uint cxl_verbose; 30 31 #define CXL_TIMEOUT 5 32 33 /* 34 * Bump version each time a user API change is made, whether it is 35 * backwards compatible ot not. 36 */ 37 #define CXL_API_VERSION 1 38 #define CXL_API_VERSION_COMPATIBLE 1 39 40 /* 41 * Opaque types to avoid accidentally passing registers for the wrong MMIO 42 * 43 * At the end of the day, I'm not married to using typedef here, but it might 44 * (and has!) help avoid bugs like mixing up CXL_PSL_CtxTime and 45 * CXL_PSL_CtxTime_An, or calling cxl_p1n_write instead of cxl_p1_write. 46 * 47 * I'm quite happy if these are changed back to #defines before upstreaming, it 48 * should be little more than a regexp search+replace operation in this file. 49 */ 50 typedef struct { 51 const int x; 52 } cxl_p1_reg_t; 53 typedef struct { 54 const int x; 55 } cxl_p1n_reg_t; 56 typedef struct { 57 const int x; 58 } cxl_p2n_reg_t; 59 #define cxl_reg_off(reg) \ 60 (reg.x) 61 62 /* Memory maps. Ref CXL Appendix A */ 63 64 /* PSL Privilege 1 Memory Map */ 65 /* Configuration and Control area */ 66 static const cxl_p1_reg_t CXL_PSL_CtxTime = {0x0000}; 67 static const cxl_p1_reg_t CXL_PSL_ErrIVTE = {0x0008}; 68 static const cxl_p1_reg_t CXL_PSL_KEY1 = {0x0010}; 69 static const cxl_p1_reg_t CXL_PSL_KEY2 = {0x0018}; 70 static const cxl_p1_reg_t CXL_PSL_Control = {0x0020}; 71 /* Downloading */ 72 static const cxl_p1_reg_t CXL_PSL_DLCNTL = {0x0060}; 73 static const cxl_p1_reg_t CXL_PSL_DLADDR = {0x0068}; 74 75 /* PSL Lookaside Buffer Management Area */ 76 static const cxl_p1_reg_t CXL_PSL_LBISEL = {0x0080}; 77 static const cxl_p1_reg_t CXL_PSL_SLBIE = {0x0088}; 78 static const cxl_p1_reg_t CXL_PSL_SLBIA = {0x0090}; 79 static const cxl_p1_reg_t CXL_PSL_TLBIE = {0x00A0}; 80 static const cxl_p1_reg_t CXL_PSL_TLBIA = {0x00A8}; 81 static const cxl_p1_reg_t CXL_PSL_AFUSEL = {0x00B0}; 82 83 /* 0x00C0:7EFF Implementation dependent area */ 84 static const cxl_p1_reg_t CXL_PSL_FIR1 = {0x0100}; 85 static const cxl_p1_reg_t CXL_PSL_FIR2 = {0x0108}; 86 static const cxl_p1_reg_t CXL_PSL_VERSION = {0x0118}; 87 static const cxl_p1_reg_t CXL_PSL_RESLCKTO = {0x0128}; 88 static const cxl_p1_reg_t CXL_PSL_FIR_CNTL = {0x0148}; 89 static const cxl_p1_reg_t CXL_PSL_DSNDCTL = {0x0150}; 90 static const cxl_p1_reg_t CXL_PSL_SNWRALLOC = {0x0158}; 91 static const cxl_p1_reg_t CXL_PSL_TRACE = {0x0170}; 92 /* 0x7F00:7FFF Reserved PCIe MSI-X Pending Bit Array area */ 93 /* 0x8000:FFFF Reserved PCIe MSI-X Table Area */ 94 95 /* PSL Slice Privilege 1 Memory Map */ 96 /* Configuration Area */ 97 static const cxl_p1n_reg_t CXL_PSL_SR_An = {0x00}; 98 static const cxl_p1n_reg_t CXL_PSL_LPID_An = {0x08}; 99 static const cxl_p1n_reg_t CXL_PSL_AMBAR_An = {0x10}; 100 static const cxl_p1n_reg_t CXL_PSL_SPOffset_An = {0x18}; 101 static const cxl_p1n_reg_t CXL_PSL_ID_An = {0x20}; 102 static const cxl_p1n_reg_t CXL_PSL_SERR_An = {0x28}; 103 /* Memory Management and Lookaside Buffer Management */ 104 static const cxl_p1n_reg_t CXL_PSL_SDR_An = {0x30}; 105 static const cxl_p1n_reg_t CXL_PSL_AMOR_An = {0x38}; 106 /* Pointer Area */ 107 static const cxl_p1n_reg_t CXL_HAURP_An = {0x80}; 108 static const cxl_p1n_reg_t CXL_PSL_SPAP_An = {0x88}; 109 static const cxl_p1n_reg_t CXL_PSL_LLCMD_An = {0x90}; 110 /* Control Area */ 111 static const cxl_p1n_reg_t CXL_PSL_SCNTL_An = {0xA0}; 112 static const cxl_p1n_reg_t CXL_PSL_CtxTime_An = {0xA8}; 113 static const cxl_p1n_reg_t CXL_PSL_IVTE_Offset_An = {0xB0}; 114 static const cxl_p1n_reg_t CXL_PSL_IVTE_Limit_An = {0xB8}; 115 /* 0xC0:FF Implementation Dependent Area */ 116 static const cxl_p1n_reg_t CXL_PSL_FIR_SLICE_An = {0xC0}; 117 static const cxl_p1n_reg_t CXL_AFU_DEBUG_An = {0xC8}; 118 static const cxl_p1n_reg_t CXL_PSL_APCALLOC_A = {0xD0}; 119 static const cxl_p1n_reg_t CXL_PSL_COALLOC_A = {0xD8}; 120 static const cxl_p1n_reg_t CXL_PSL_RXCTL_A = {0xE0}; 121 static const cxl_p1n_reg_t CXL_PSL_SLICE_TRACE = {0xE8}; 122 123 /* PSL Slice Privilege 2 Memory Map */ 124 /* Configuration and Control Area */ 125 static const cxl_p2n_reg_t CXL_PSL_PID_TID_An = {0x000}; 126 static const cxl_p2n_reg_t CXL_CSRP_An = {0x008}; 127 static const cxl_p2n_reg_t CXL_AURP0_An = {0x010}; 128 static const cxl_p2n_reg_t CXL_AURP1_An = {0x018}; 129 static const cxl_p2n_reg_t CXL_SSTP0_An = {0x020}; 130 static const cxl_p2n_reg_t CXL_SSTP1_An = {0x028}; 131 static const cxl_p2n_reg_t CXL_PSL_AMR_An = {0x030}; 132 /* Segment Lookaside Buffer Management */ 133 static const cxl_p2n_reg_t CXL_SLBIE_An = {0x040}; 134 static const cxl_p2n_reg_t CXL_SLBIA_An = {0x048}; 135 static const cxl_p2n_reg_t CXL_SLBI_Select_An = {0x050}; 136 /* Interrupt Registers */ 137 static const cxl_p2n_reg_t CXL_PSL_DSISR_An = {0x060}; 138 static const cxl_p2n_reg_t CXL_PSL_DAR_An = {0x068}; 139 static const cxl_p2n_reg_t CXL_PSL_DSR_An = {0x070}; 140 static const cxl_p2n_reg_t CXL_PSL_TFC_An = {0x078}; 141 static const cxl_p2n_reg_t CXL_PSL_PEHandle_An = {0x080}; 142 static const cxl_p2n_reg_t CXL_PSL_ErrStat_An = {0x088}; 143 /* AFU Registers */ 144 static const cxl_p2n_reg_t CXL_AFU_Cntl_An = {0x090}; 145 static const cxl_p2n_reg_t CXL_AFU_ERR_An = {0x098}; 146 /* Work Element Descriptor */ 147 static const cxl_p2n_reg_t CXL_PSL_WED_An = {0x0A0}; 148 /* 0x0C0:FFF Implementation Dependent Area */ 149 150 #define CXL_PSL_SPAP_Addr 0x0ffffffffffff000ULL 151 #define CXL_PSL_SPAP_Size 0x0000000000000ff0ULL 152 #define CXL_PSL_SPAP_Size_Shift 4 153 #define CXL_PSL_SPAP_V 0x0000000000000001ULL 154 155 /****** CXL_PSL_DLCNTL *****************************************************/ 156 #define CXL_PSL_DLCNTL_D (0x1ull << (63-28)) 157 #define CXL_PSL_DLCNTL_C (0x1ull << (63-29)) 158 #define CXL_PSL_DLCNTL_E (0x1ull << (63-30)) 159 #define CXL_PSL_DLCNTL_S (0x1ull << (63-31)) 160 #define CXL_PSL_DLCNTL_CE (CXL_PSL_DLCNTL_C | CXL_PSL_DLCNTL_E) 161 #define CXL_PSL_DLCNTL_DCES (CXL_PSL_DLCNTL_D | CXL_PSL_DLCNTL_CE | CXL_PSL_DLCNTL_S) 162 163 /****** CXL_PSL_SR_An ******************************************************/ 164 #define CXL_PSL_SR_An_SF MSR_SF /* 64bit */ 165 #define CXL_PSL_SR_An_TA (1ull << (63-1)) /* Tags active, GA1: 0 */ 166 #define CXL_PSL_SR_An_HV MSR_HV /* Hypervisor, GA1: 0 */ 167 #define CXL_PSL_SR_An_PR MSR_PR /* Problem state, GA1: 1 */ 168 #define CXL_PSL_SR_An_ISL (1ull << (63-53)) /* Ignore Segment Large Page */ 169 #define CXL_PSL_SR_An_TC (1ull << (63-54)) /* Page Table secondary hash */ 170 #define CXL_PSL_SR_An_US (1ull << (63-56)) /* User state, GA1: X */ 171 #define CXL_PSL_SR_An_SC (1ull << (63-58)) /* Segment Table secondary hash */ 172 #define CXL_PSL_SR_An_R MSR_DR /* Relocate, GA1: 1 */ 173 #define CXL_PSL_SR_An_MP (1ull << (63-62)) /* Master Process */ 174 #define CXL_PSL_SR_An_LE (1ull << (63-63)) /* Little Endian */ 175 176 /****** CXL_PSL_LLCMD_An ****************************************************/ 177 #define CXL_LLCMD_TERMINATE 0x0001000000000000ULL 178 #define CXL_LLCMD_REMOVE 0x0002000000000000ULL 179 #define CXL_LLCMD_SUSPEND 0x0003000000000000ULL 180 #define CXL_LLCMD_RESUME 0x0004000000000000ULL 181 #define CXL_LLCMD_ADD 0x0005000000000000ULL 182 #define CXL_LLCMD_UPDATE 0x0006000000000000ULL 183 #define CXL_LLCMD_HANDLE_MASK 0x000000000000ffffULL 184 185 /****** CXL_PSL_ID_An ****************************************************/ 186 #define CXL_PSL_ID_An_F (1ull << (63-31)) 187 #define CXL_PSL_ID_An_L (1ull << (63-30)) 188 189 /****** CXL_PSL_SCNTL_An ****************************************************/ 190 #define CXL_PSL_SCNTL_An_CR (0x1ull << (63-15)) 191 /* Programming Modes: */ 192 #define CXL_PSL_SCNTL_An_PM_MASK (0xffffull << (63-31)) 193 #define CXL_PSL_SCNTL_An_PM_Shared (0x0000ull << (63-31)) 194 #define CXL_PSL_SCNTL_An_PM_OS (0x0001ull << (63-31)) 195 #define CXL_PSL_SCNTL_An_PM_Process (0x0002ull << (63-31)) 196 #define CXL_PSL_SCNTL_An_PM_AFU (0x0004ull << (63-31)) 197 #define CXL_PSL_SCNTL_An_PM_AFU_PBT (0x0104ull << (63-31)) 198 /* Purge Status (ro) */ 199 #define CXL_PSL_SCNTL_An_Ps_MASK (0x3ull << (63-39)) 200 #define CXL_PSL_SCNTL_An_Ps_Pending (0x1ull << (63-39)) 201 #define CXL_PSL_SCNTL_An_Ps_Complete (0x3ull << (63-39)) 202 /* Purge */ 203 #define CXL_PSL_SCNTL_An_Pc (0x1ull << (63-48)) 204 /* Suspend Status (ro) */ 205 #define CXL_PSL_SCNTL_An_Ss_MASK (0x3ull << (63-55)) 206 #define CXL_PSL_SCNTL_An_Ss_Pending (0x1ull << (63-55)) 207 #define CXL_PSL_SCNTL_An_Ss_Complete (0x3ull << (63-55)) 208 /* Suspend Control */ 209 #define CXL_PSL_SCNTL_An_Sc (0x1ull << (63-63)) 210 211 /* AFU Slice Enable Status (ro) */ 212 #define CXL_AFU_Cntl_An_ES_MASK (0x7ull << (63-2)) 213 #define CXL_AFU_Cntl_An_ES_Disabled (0x0ull << (63-2)) 214 #define CXL_AFU_Cntl_An_ES_Enabled (0x4ull << (63-2)) 215 /* AFU Slice Enable */ 216 #define CXL_AFU_Cntl_An_E (0x1ull << (63-3)) 217 /* AFU Slice Reset status (ro) */ 218 #define CXL_AFU_Cntl_An_RS_MASK (0x3ull << (63-5)) 219 #define CXL_AFU_Cntl_An_RS_Pending (0x1ull << (63-5)) 220 #define CXL_AFU_Cntl_An_RS_Complete (0x2ull << (63-5)) 221 /* AFU Slice Reset */ 222 #define CXL_AFU_Cntl_An_RA (0x1ull << (63-7)) 223 224 /****** CXL_SSTP0/1_An ******************************************************/ 225 /* These top bits are for the segment that CONTAINS the segment table */ 226 #define CXL_SSTP0_An_B_SHIFT SLB_VSID_SSIZE_SHIFT 227 #define CXL_SSTP0_An_KS (1ull << (63-2)) 228 #define CXL_SSTP0_An_KP (1ull << (63-3)) 229 #define CXL_SSTP0_An_N (1ull << (63-4)) 230 #define CXL_SSTP0_An_L (1ull << (63-5)) 231 #define CXL_SSTP0_An_C (1ull << (63-6)) 232 #define CXL_SSTP0_An_TA (1ull << (63-7)) 233 #define CXL_SSTP0_An_LP_SHIFT (63-9) /* 2 Bits */ 234 /* And finally, the virtual address & size of the segment table: */ 235 #define CXL_SSTP0_An_SegTableSize_SHIFT (63-31) /* 12 Bits */ 236 #define CXL_SSTP0_An_SegTableSize_MASK \ 237 (((1ull << 12) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT) 238 #define CXL_SSTP0_An_STVA_U_MASK ((1ull << (63-49))-1) 239 #define CXL_SSTP1_An_STVA_L_MASK (~((1ull << (63-55))-1)) 240 #define CXL_SSTP1_An_V (1ull << (63-63)) 241 242 /****** CXL_PSL_SLBIE_[An] **************************************************/ 243 /* write: */ 244 #define CXL_SLBIE_C PPC_BIT(36) /* Class */ 245 #define CXL_SLBIE_SS PPC_BITMASK(37, 38) /* Segment Size */ 246 #define CXL_SLBIE_SS_SHIFT PPC_BITLSHIFT(38) 247 #define CXL_SLBIE_TA PPC_BIT(38) /* Tags Active */ 248 /* read: */ 249 #define CXL_SLBIE_MAX PPC_BITMASK(24, 31) 250 #define CXL_SLBIE_PENDING PPC_BITMASK(56, 63) 251 252 /****** Common to all CXL_TLBIA/SLBIA_[An] **********************************/ 253 #define CXL_TLB_SLB_P (1ull) /* Pending (read) */ 254 255 /****** Common to all CXL_TLB/SLB_IA/IE_[An] registers **********************/ 256 #define CXL_TLB_SLB_IQ_ALL (0ull) /* Inv qualifier */ 257 #define CXL_TLB_SLB_IQ_LPID (1ull) /* Inv qualifier */ 258 #define CXL_TLB_SLB_IQ_LPIDPID (3ull) /* Inv qualifier */ 259 260 /****** CXL_PSL_AFUSEL ******************************************************/ 261 #define CXL_PSL_AFUSEL_A (1ull << (63-55)) /* Adapter wide invalidates affect all AFUs */ 262 263 /****** CXL_PSL_DSISR_An ****************************************************/ 264 #define CXL_PSL_DSISR_An_DS (1ull << (63-0)) /* Segment not found */ 265 #define CXL_PSL_DSISR_An_DM (1ull << (63-1)) /* PTE not found (See also: M) or protection fault */ 266 #define CXL_PSL_DSISR_An_ST (1ull << (63-2)) /* Segment Table PTE not found */ 267 #define CXL_PSL_DSISR_An_UR (1ull << (63-3)) /* AURP PTE not found */ 268 #define CXL_PSL_DSISR_TRANS (CXL_PSL_DSISR_An_DS | CXL_PSL_DSISR_An_DM | CXL_PSL_DSISR_An_ST | CXL_PSL_DSISR_An_UR) 269 #define CXL_PSL_DSISR_An_PE (1ull << (63-4)) /* PSL Error (implementation specific) */ 270 #define CXL_PSL_DSISR_An_AE (1ull << (63-5)) /* AFU Error */ 271 #define CXL_PSL_DSISR_An_OC (1ull << (63-6)) /* OS Context Warning */ 272 /* NOTE: Bits 32:63 are undefined if DSISR[DS] = 1 */ 273 #define CXL_PSL_DSISR_An_M DSISR_NOHPTE /* PTE not found */ 274 #define CXL_PSL_DSISR_An_P DSISR_PROTFAULT /* Storage protection violation */ 275 #define CXL_PSL_DSISR_An_A (1ull << (63-37)) /* AFU lock access to write through or cache inhibited storage */ 276 #define CXL_PSL_DSISR_An_S DSISR_ISSTORE /* Access was afu_wr or afu_zero */ 277 #define CXL_PSL_DSISR_An_K DSISR_KEYFAULT /* Access not permitted by virtual page class key protection */ 278 279 /****** CXL_PSL_TFC_An ******************************************************/ 280 #define CXL_PSL_TFC_An_A (1ull << (63-28)) /* Acknowledge non-translation fault */ 281 #define CXL_PSL_TFC_An_C (1ull << (63-29)) /* Continue (abort transaction) */ 282 #define CXL_PSL_TFC_An_AE (1ull << (63-30)) /* Restart PSL with address error */ 283 #define CXL_PSL_TFC_An_R (1ull << (63-31)) /* Restart PSL transaction */ 284 285 /* cxl_process_element->software_status */ 286 #define CXL_PE_SOFTWARE_STATE_V (1ul << (31 - 0)) /* Valid */ 287 #define CXL_PE_SOFTWARE_STATE_C (1ul << (31 - 29)) /* Complete */ 288 #define CXL_PE_SOFTWARE_STATE_S (1ul << (31 - 30)) /* Suspend */ 289 #define CXL_PE_SOFTWARE_STATE_T (1ul << (31 - 31)) /* Terminate */ 290 291 /****** CXL_PSL_RXCTL_An (Implementation Specific) ************************** 292 * Controls AFU Hang Pulse, which sets the timeout for the AFU to respond to 293 * the PSL for any response (except MMIO). Timeouts will occur between 1x to 2x 294 * of the hang pulse frequency. 295 */ 296 #define CXL_PSL_RXCTL_AFUHP_4S 0x7000000000000000ULL 297 298 /* SPA->sw_command_status */ 299 #define CXL_SPA_SW_CMD_MASK 0xffff000000000000ULL 300 #define CXL_SPA_SW_CMD_TERMINATE 0x0001000000000000ULL 301 #define CXL_SPA_SW_CMD_REMOVE 0x0002000000000000ULL 302 #define CXL_SPA_SW_CMD_SUSPEND 0x0003000000000000ULL 303 #define CXL_SPA_SW_CMD_RESUME 0x0004000000000000ULL 304 #define CXL_SPA_SW_CMD_ADD 0x0005000000000000ULL 305 #define CXL_SPA_SW_CMD_UPDATE 0x0006000000000000ULL 306 #define CXL_SPA_SW_STATE_MASK 0x0000ffff00000000ULL 307 #define CXL_SPA_SW_STATE_TERMINATED 0x0000000100000000ULL 308 #define CXL_SPA_SW_STATE_REMOVED 0x0000000200000000ULL 309 #define CXL_SPA_SW_STATE_SUSPENDED 0x0000000300000000ULL 310 #define CXL_SPA_SW_STATE_RESUMED 0x0000000400000000ULL 311 #define CXL_SPA_SW_STATE_ADDED 0x0000000500000000ULL 312 #define CXL_SPA_SW_STATE_UPDATED 0x0000000600000000ULL 313 #define CXL_SPA_SW_PSL_ID_MASK 0x00000000ffff0000ULL 314 #define CXL_SPA_SW_LINK_MASK 0x000000000000ffffULL 315 316 #define CXL_MAX_SLICES 4 317 #define MAX_AFU_MMIO_REGS 3 318 319 #define CXL_MODE_TIME_SLICED 0x4 320 #define CXL_SUPPORTED_MODES (CXL_MODE_DEDICATED | CXL_MODE_DIRECTED) 321 322 enum cxl_context_status { 323 CLOSED, 324 OPENED, 325 STARTED 326 }; 327 328 enum prefault_modes { 329 CXL_PREFAULT_NONE, 330 CXL_PREFAULT_WED, 331 CXL_PREFAULT_ALL, 332 }; 333 334 struct cxl_sste { 335 __be64 esid_data; 336 __be64 vsid_data; 337 }; 338 339 #define to_cxl_adapter(d) container_of(d, struct cxl, dev) 340 #define to_cxl_afu(d) container_of(d, struct cxl_afu, dev) 341 342 struct cxl_afu { 343 irq_hw_number_t psl_hwirq; 344 irq_hw_number_t serr_hwirq; 345 char *err_irq_name; 346 char *psl_irq_name; 347 unsigned int serr_virq; 348 void __iomem *p1n_mmio; 349 void __iomem *p2n_mmio; 350 phys_addr_t psn_phys; 351 u64 pp_offset; 352 u64 pp_size; 353 void __iomem *afu_desc_mmio; 354 struct cxl *adapter; 355 struct device dev; 356 struct cdev afu_cdev_s, afu_cdev_m, afu_cdev_d; 357 struct device *chardev_s, *chardev_m, *chardev_d; 358 struct idr contexts_idr; 359 struct dentry *debugfs; 360 struct mutex contexts_lock; 361 struct mutex spa_mutex; 362 spinlock_t afu_cntl_lock; 363 364 /* AFU error buffer fields and bin attribute for sysfs */ 365 u64 eb_len, eb_offset; 366 struct bin_attribute attr_eb; 367 368 /* 369 * Only the first part of the SPA is used for the process element 370 * linked list. The only other part that software needs to worry about 371 * is sw_command_status, which we store a separate pointer to. 372 * Everything else in the SPA is only used by hardware 373 */ 374 struct cxl_process_element *spa; 375 __be64 *sw_command_status; 376 unsigned int spa_size; 377 int spa_order; 378 int spa_max_procs; 379 unsigned int psl_virq; 380 381 /* pointer to the vphb */ 382 struct pci_controller *phb; 383 384 int pp_irqs; 385 int irqs_max; 386 int num_procs; 387 int max_procs_virtualised; 388 int slice; 389 int modes_supported; 390 int current_mode; 391 int crs_num; 392 u64 crs_len; 393 u64 crs_offset; 394 struct list_head crs; 395 enum prefault_modes prefault_mode; 396 bool psa; 397 bool pp_psa; 398 bool enabled; 399 }; 400 401 402 struct cxl_irq_name { 403 struct list_head list; 404 char *name; 405 }; 406 407 /* 408 * This is a cxl context. If the PSL is in dedicated mode, there will be one 409 * of these per AFU. If in AFU directed there can be lots of these. 410 */ 411 struct cxl_context { 412 struct cxl_afu *afu; 413 414 /* Problem state MMIO */ 415 phys_addr_t psn_phys; 416 u64 psn_size; 417 418 /* Used to unmap any mmaps when force detaching */ 419 struct address_space *mapping; 420 struct mutex mapping_lock; 421 422 spinlock_t sste_lock; /* Protects segment table entries */ 423 struct cxl_sste *sstp; 424 u64 sstp0, sstp1; 425 unsigned int sst_size, sst_lru; 426 427 wait_queue_head_t wq; 428 struct pid *pid; 429 spinlock_t lock; /* Protects pending_irq_mask, pending_fault and fault_addr */ 430 /* Only used in PR mode */ 431 u64 process_token; 432 433 unsigned long *irq_bitmap; /* Accessed from IRQ context */ 434 struct cxl_irq_ranges irqs; 435 struct list_head irq_names; 436 u64 fault_addr; 437 u64 fault_dsisr; 438 u64 afu_err; 439 440 /* 441 * This status and it's lock pretects start and detach context 442 * from racing. It also prevents detach from racing with 443 * itself 444 */ 445 enum cxl_context_status status; 446 struct mutex status_mutex; 447 448 449 /* XXX: Is it possible to need multiple work items at once? */ 450 struct work_struct fault_work; 451 u64 dsisr; 452 u64 dar; 453 454 struct cxl_process_element *elem; 455 456 int pe; /* process element handle */ 457 u32 irq_count; 458 bool pe_inserted; 459 bool master; 460 bool kernel; 461 bool pending_irq; 462 bool pending_fault; 463 bool pending_afu_err; 464 465 struct rcu_head rcu; 466 }; 467 468 struct cxl { 469 void __iomem *p1_mmio; 470 void __iomem *p2_mmio; 471 irq_hw_number_t err_hwirq; 472 unsigned int err_virq; 473 spinlock_t afu_list_lock; 474 struct cxl_afu *afu[CXL_MAX_SLICES]; 475 struct device dev; 476 struct dentry *trace; 477 struct dentry *psl_err_chk; 478 struct dentry *debugfs; 479 char *irq_name; 480 struct bin_attribute cxl_attr; 481 int adapter_num; 482 int user_irqs; 483 u64 afu_desc_off; 484 u64 afu_desc_size; 485 u64 ps_off; 486 u64 ps_size; 487 u16 psl_rev; 488 u16 base_image; 489 u8 vsec_status; 490 u8 caia_major; 491 u8 caia_minor; 492 u8 slices; 493 bool user_image_loaded; 494 bool perst_loads_image; 495 bool perst_select_user; 496 }; 497 498 int cxl_alloc_one_irq(struct cxl *adapter); 499 void cxl_release_one_irq(struct cxl *adapter, int hwirq); 500 int cxl_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num); 501 void cxl_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter); 502 int cxl_setup_irq(struct cxl *adapter, unsigned int hwirq, unsigned int virq); 503 int cxl_update_image_control(struct cxl *adapter); 504 int cxl_reset(struct cxl *adapter); 505 506 /* common == phyp + powernv */ 507 struct cxl_process_element_common { 508 __be32 tid; 509 __be32 pid; 510 __be64 csrp; 511 __be64 aurp0; 512 __be64 aurp1; 513 __be64 sstp0; 514 __be64 sstp1; 515 __be64 amr; 516 u8 reserved3[4]; 517 __be64 wed; 518 } __packed; 519 520 /* just powernv */ 521 struct cxl_process_element { 522 __be64 sr; 523 __be64 SPOffset; 524 __be64 sdr; 525 __be64 haurp; 526 __be32 ctxtime; 527 __be16 ivte_offsets[4]; 528 __be16 ivte_ranges[4]; 529 __be32 lpid; 530 struct cxl_process_element_common common; 531 __be32 software_state; 532 } __packed; 533 534 static inline void __iomem *_cxl_p1_addr(struct cxl *cxl, cxl_p1_reg_t reg) 535 { 536 WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE)); 537 return cxl->p1_mmio + cxl_reg_off(reg); 538 } 539 540 #define cxl_p1_write(cxl, reg, val) \ 541 out_be64(_cxl_p1_addr(cxl, reg), val) 542 #define cxl_p1_read(cxl, reg) \ 543 in_be64(_cxl_p1_addr(cxl, reg)) 544 545 static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg) 546 { 547 WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE)); 548 return afu->p1n_mmio + cxl_reg_off(reg); 549 } 550 551 #define cxl_p1n_write(afu, reg, val) \ 552 out_be64(_cxl_p1n_addr(afu, reg), val) 553 #define cxl_p1n_read(afu, reg) \ 554 in_be64(_cxl_p1n_addr(afu, reg)) 555 556 static inline void __iomem *_cxl_p2n_addr(struct cxl_afu *afu, cxl_p2n_reg_t reg) 557 { 558 return afu->p2n_mmio + cxl_reg_off(reg); 559 } 560 561 #define cxl_p2n_write(afu, reg, val) \ 562 out_be64(_cxl_p2n_addr(afu, reg), val) 563 #define cxl_p2n_read(afu, reg) \ 564 in_be64(_cxl_p2n_addr(afu, reg)) 565 566 567 #define cxl_afu_cr_read64(afu, cr, off) \ 568 in_le64((afu)->afu_desc_mmio + (afu)->crs_offset + ((cr) * (afu)->crs_len) + (off)) 569 #define cxl_afu_cr_read32(afu, cr, off) \ 570 in_le32((afu)->afu_desc_mmio + (afu)->crs_offset + ((cr) * (afu)->crs_len) + (off)) 571 u16 cxl_afu_cr_read16(struct cxl_afu *afu, int cr, u64 off); 572 u8 cxl_afu_cr_read8(struct cxl_afu *afu, int cr, u64 off); 573 574 ssize_t cxl_afu_read_err_buffer(struct cxl_afu *afu, char *buf, 575 loff_t off, size_t count); 576 577 578 struct cxl_calls { 579 void (*cxl_slbia)(struct mm_struct *mm); 580 struct module *owner; 581 }; 582 int register_cxl_calls(struct cxl_calls *calls); 583 void unregister_cxl_calls(struct cxl_calls *calls); 584 585 int cxl_alloc_adapter_nr(struct cxl *adapter); 586 void cxl_remove_adapter_nr(struct cxl *adapter); 587 588 int cxl_file_init(void); 589 void cxl_file_exit(void); 590 int cxl_register_adapter(struct cxl *adapter); 591 int cxl_register_afu(struct cxl_afu *afu); 592 int cxl_chardev_d_afu_add(struct cxl_afu *afu); 593 int cxl_chardev_m_afu_add(struct cxl_afu *afu); 594 int cxl_chardev_s_afu_add(struct cxl_afu *afu); 595 void cxl_chardev_afu_remove(struct cxl_afu *afu); 596 597 void cxl_context_detach_all(struct cxl_afu *afu); 598 void cxl_context_free(struct cxl_context *ctx); 599 void cxl_context_detach(struct cxl_context *ctx); 600 601 int cxl_sysfs_adapter_add(struct cxl *adapter); 602 void cxl_sysfs_adapter_remove(struct cxl *adapter); 603 int cxl_sysfs_afu_add(struct cxl_afu *afu); 604 void cxl_sysfs_afu_remove(struct cxl_afu *afu); 605 int cxl_sysfs_afu_m_add(struct cxl_afu *afu); 606 void cxl_sysfs_afu_m_remove(struct cxl_afu *afu); 607 608 int cxl_afu_activate_mode(struct cxl_afu *afu, int mode); 609 int _cxl_afu_deactivate_mode(struct cxl_afu *afu, int mode); 610 int cxl_afu_deactivate_mode(struct cxl_afu *afu); 611 int cxl_afu_select_best_mode(struct cxl_afu *afu); 612 613 int cxl_register_psl_irq(struct cxl_afu *afu); 614 void cxl_release_psl_irq(struct cxl_afu *afu); 615 int cxl_register_psl_err_irq(struct cxl *adapter); 616 void cxl_release_psl_err_irq(struct cxl *adapter); 617 int cxl_register_serr_irq(struct cxl_afu *afu); 618 void cxl_release_serr_irq(struct cxl_afu *afu); 619 int afu_register_irqs(struct cxl_context *ctx, u32 count); 620 void afu_release_irqs(struct cxl_context *ctx, void *cookie); 621 irqreturn_t cxl_slice_irq_err(int irq, void *data); 622 623 int cxl_debugfs_init(void); 624 void cxl_debugfs_exit(void); 625 int cxl_debugfs_adapter_add(struct cxl *adapter); 626 void cxl_debugfs_adapter_remove(struct cxl *adapter); 627 int cxl_debugfs_afu_add(struct cxl_afu *afu); 628 void cxl_debugfs_afu_remove(struct cxl_afu *afu); 629 630 void cxl_handle_fault(struct work_struct *work); 631 void cxl_prefault(struct cxl_context *ctx, u64 wed); 632 633 struct cxl *get_cxl_adapter(int num); 634 int cxl_alloc_sst(struct cxl_context *ctx); 635 636 void init_cxl_native(void); 637 638 struct cxl_context *cxl_context_alloc(void); 639 int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master, 640 struct address_space *mapping); 641 void cxl_context_free(struct cxl_context *ctx); 642 int cxl_context_iomap(struct cxl_context *ctx, struct vm_area_struct *vma); 643 unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq, 644 irq_handler_t handler, void *cookie, const char *name); 645 void cxl_unmap_irq(unsigned int virq, void *cookie); 646 int __detach_context(struct cxl_context *ctx); 647 648 /* This matches the layout of the H_COLLECT_CA_INT_INFO retbuf */ 649 struct cxl_irq_info { 650 u64 dsisr; 651 u64 dar; 652 u64 dsr; 653 u32 pid; 654 u32 tid; 655 u64 afu_err; 656 u64 errstat; 657 u64 padding[3]; /* to match the expected retbuf size for plpar_hcall9 */ 658 }; 659 660 void cxl_assign_psn_space(struct cxl_context *ctx); 661 int cxl_attach_process(struct cxl_context *ctx, bool kernel, u64 wed, 662 u64 amr); 663 int cxl_detach_process(struct cxl_context *ctx); 664 665 int cxl_get_irq(struct cxl_afu *afu, struct cxl_irq_info *info); 666 int cxl_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask); 667 668 int cxl_check_error(struct cxl_afu *afu); 669 int cxl_afu_slbia(struct cxl_afu *afu); 670 int cxl_tlb_slb_invalidate(struct cxl *adapter); 671 int cxl_afu_disable(struct cxl_afu *afu); 672 int __cxl_afu_reset(struct cxl_afu *afu); 673 int cxl_afu_check_and_enable(struct cxl_afu *afu); 674 int cxl_psl_purge(struct cxl_afu *afu); 675 676 void cxl_stop_trace(struct cxl *cxl); 677 int cxl_pci_vphb_add(struct cxl_afu *afu); 678 void cxl_pci_vphb_remove(struct cxl_afu *afu); 679 680 extern struct pci_driver cxl_pci_driver; 681 int afu_allocate_irqs(struct cxl_context *ctx, u32 count); 682 683 int afu_open(struct inode *inode, struct file *file); 684 int afu_release(struct inode *inode, struct file *file); 685 long afu_ioctl(struct file *file, unsigned int cmd, unsigned long arg); 686 int afu_mmap(struct file *file, struct vm_area_struct *vm); 687 unsigned int afu_poll(struct file *file, struct poll_table_struct *poll); 688 ssize_t afu_read(struct file *file, char __user *buf, size_t count, loff_t *off); 689 extern const struct file_operations afu_fops; 690 691 #endif 692