1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Driver for Realtek PCI-Express card reader 3 * 4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 5 * 6 * Author: 7 * Wei WANG <wei_wang@realsil.com.cn> 8 */ 9 10 #include <linux/pci.h> 11 #include <linux/module.h> 12 #include <linux/slab.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/highmem.h> 15 #include <linux/interrupt.h> 16 #include <linux/delay.h> 17 #include <linux/idr.h> 18 #include <linux/platform_device.h> 19 #include <linux/mfd/core.h> 20 #include <linux/rtsx_pci.h> 21 #include <linux/mmc/card.h> 22 #include <asm/unaligned.h> 23 24 #include "rtsx_pcr.h" 25 #include "rts5261.h" 26 27 static bool msi_en = true; 28 module_param(msi_en, bool, S_IRUGO | S_IWUSR); 29 MODULE_PARM_DESC(msi_en, "Enable MSI"); 30 31 static DEFINE_IDR(rtsx_pci_idr); 32 static DEFINE_SPINLOCK(rtsx_pci_lock); 33 34 static struct mfd_cell rtsx_pcr_cells[] = { 35 [RTSX_SD_CARD] = { 36 .name = DRV_NAME_RTSX_PCI_SDMMC, 37 }, 38 }; 39 40 static const struct pci_device_id rtsx_pci_ids[] = { 41 { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 42 { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 43 { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 44 { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 45 { PCI_DEVICE(0x10EC, 0x522A), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 46 { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 47 { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 48 { PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 49 { PCI_DEVICE(0x10EC, 0x524A), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 50 { PCI_DEVICE(0x10EC, 0x525A), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 51 { PCI_DEVICE(0x10EC, 0x5260), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 52 { PCI_DEVICE(0x10EC, 0x5261), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 53 { 0, } 54 }; 55 56 MODULE_DEVICE_TABLE(pci, rtsx_pci_ids); 57 58 static inline void rtsx_pci_enable_aspm(struct rtsx_pcr *pcr) 59 { 60 rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL, 61 0xFC, pcr->aspm_en); 62 } 63 64 static inline void rtsx_pci_disable_aspm(struct rtsx_pcr *pcr) 65 { 66 rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL, 67 0xFC, 0); 68 } 69 70 static int rtsx_comm_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency) 71 { 72 rtsx_pci_write_register(pcr, MSGTXDATA0, 73 MASK_8_BIT_DEF, (u8) (latency & 0xFF)); 74 rtsx_pci_write_register(pcr, MSGTXDATA1, 75 MASK_8_BIT_DEF, (u8)((latency >> 8) & 0xFF)); 76 rtsx_pci_write_register(pcr, MSGTXDATA2, 77 MASK_8_BIT_DEF, (u8)((latency >> 16) & 0xFF)); 78 rtsx_pci_write_register(pcr, MSGTXDATA3, 79 MASK_8_BIT_DEF, (u8)((latency >> 24) & 0xFF)); 80 rtsx_pci_write_register(pcr, LTR_CTL, LTR_TX_EN_MASK | 81 LTR_LATENCY_MODE_MASK, LTR_TX_EN_1 | LTR_LATENCY_MODE_SW); 82 83 return 0; 84 } 85 86 int rtsx_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency) 87 { 88 if (pcr->ops->set_ltr_latency) 89 return pcr->ops->set_ltr_latency(pcr, latency); 90 else 91 return rtsx_comm_set_ltr_latency(pcr, latency); 92 } 93 94 static void rtsx_comm_set_aspm(struct rtsx_pcr *pcr, bool enable) 95 { 96 struct rtsx_cr_option *option = &pcr->option; 97 98 if (pcr->aspm_enabled == enable) 99 return; 100 101 if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) { 102 if (enable) 103 rtsx_pci_enable_aspm(pcr); 104 else 105 rtsx_pci_disable_aspm(pcr); 106 } else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) { 107 u8 mask = FORCE_ASPM_VAL_MASK; 108 u8 val = 0; 109 110 if (enable) 111 val = pcr->aspm_en; 112 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); 113 } 114 115 pcr->aspm_enabled = enable; 116 } 117 118 static void rtsx_disable_aspm(struct rtsx_pcr *pcr) 119 { 120 if (pcr->ops->set_aspm) 121 pcr->ops->set_aspm(pcr, false); 122 else 123 rtsx_comm_set_aspm(pcr, false); 124 } 125 126 int rtsx_set_l1off_sub(struct rtsx_pcr *pcr, u8 val) 127 { 128 rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, val); 129 130 return 0; 131 } 132 133 static void rtsx_set_l1off_sub_cfg_d0(struct rtsx_pcr *pcr, int active) 134 { 135 if (pcr->ops->set_l1off_cfg_sub_d0) 136 pcr->ops->set_l1off_cfg_sub_d0(pcr, active); 137 } 138 139 static void rtsx_comm_pm_full_on(struct rtsx_pcr *pcr) 140 { 141 struct rtsx_cr_option *option = &pcr->option; 142 143 rtsx_disable_aspm(pcr); 144 145 if (option->ltr_enabled) 146 rtsx_set_ltr_latency(pcr, option->ltr_active_latency); 147 148 if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_EN)) 149 rtsx_set_l1off_sub_cfg_d0(pcr, 1); 150 } 151 152 static void rtsx_pm_full_on(struct rtsx_pcr *pcr) 153 { 154 if (pcr->ops->full_on) 155 pcr->ops->full_on(pcr); 156 else 157 rtsx_comm_pm_full_on(pcr); 158 } 159 160 void rtsx_pci_start_run(struct rtsx_pcr *pcr) 161 { 162 /* If pci device removed, don't queue idle work any more */ 163 if (pcr->remove_pci) 164 return; 165 166 if (pcr->state != PDEV_STAT_RUN) { 167 pcr->state = PDEV_STAT_RUN; 168 if (pcr->ops->enable_auto_blink) 169 pcr->ops->enable_auto_blink(pcr); 170 rtsx_pm_full_on(pcr); 171 } 172 173 mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200)); 174 } 175 EXPORT_SYMBOL_GPL(rtsx_pci_start_run); 176 177 int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data) 178 { 179 int i; 180 u32 val = HAIMR_WRITE_START; 181 182 val |= (u32)(addr & 0x3FFF) << 16; 183 val |= (u32)mask << 8; 184 val |= (u32)data; 185 186 rtsx_pci_writel(pcr, RTSX_HAIMR, val); 187 188 for (i = 0; i < MAX_RW_REG_CNT; i++) { 189 val = rtsx_pci_readl(pcr, RTSX_HAIMR); 190 if ((val & HAIMR_TRANS_END) == 0) { 191 if (data != (u8)val) 192 return -EIO; 193 return 0; 194 } 195 } 196 197 return -ETIMEDOUT; 198 } 199 EXPORT_SYMBOL_GPL(rtsx_pci_write_register); 200 201 int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data) 202 { 203 u32 val = HAIMR_READ_START; 204 int i; 205 206 val |= (u32)(addr & 0x3FFF) << 16; 207 rtsx_pci_writel(pcr, RTSX_HAIMR, val); 208 209 for (i = 0; i < MAX_RW_REG_CNT; i++) { 210 val = rtsx_pci_readl(pcr, RTSX_HAIMR); 211 if ((val & HAIMR_TRANS_END) == 0) 212 break; 213 } 214 215 if (i >= MAX_RW_REG_CNT) 216 return -ETIMEDOUT; 217 218 if (data) 219 *data = (u8)(val & 0xFF); 220 221 return 0; 222 } 223 EXPORT_SYMBOL_GPL(rtsx_pci_read_register); 224 225 int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val) 226 { 227 int err, i, finished = 0; 228 u8 tmp; 229 230 rtsx_pci_init_cmd(pcr); 231 232 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val); 233 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8)); 234 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr); 235 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81); 236 237 err = rtsx_pci_send_cmd(pcr, 100); 238 if (err < 0) 239 return err; 240 241 for (i = 0; i < 100000; i++) { 242 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp); 243 if (err < 0) 244 return err; 245 246 if (!(tmp & 0x80)) { 247 finished = 1; 248 break; 249 } 250 } 251 252 if (!finished) 253 return -ETIMEDOUT; 254 255 return 0; 256 } 257 258 int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val) 259 { 260 if (pcr->ops->write_phy) 261 return pcr->ops->write_phy(pcr, addr, val); 262 263 return __rtsx_pci_write_phy_register(pcr, addr, val); 264 } 265 EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register); 266 267 int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val) 268 { 269 int err, i, finished = 0; 270 u16 data; 271 u8 *ptr, tmp; 272 273 rtsx_pci_init_cmd(pcr); 274 275 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr); 276 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80); 277 278 err = rtsx_pci_send_cmd(pcr, 100); 279 if (err < 0) 280 return err; 281 282 for (i = 0; i < 100000; i++) { 283 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp); 284 if (err < 0) 285 return err; 286 287 if (!(tmp & 0x80)) { 288 finished = 1; 289 break; 290 } 291 } 292 293 if (!finished) 294 return -ETIMEDOUT; 295 296 rtsx_pci_init_cmd(pcr); 297 298 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0); 299 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0); 300 301 err = rtsx_pci_send_cmd(pcr, 100); 302 if (err < 0) 303 return err; 304 305 ptr = rtsx_pci_get_cmd_data(pcr); 306 data = ((u16)ptr[1] << 8) | ptr[0]; 307 308 if (val) 309 *val = data; 310 311 return 0; 312 } 313 314 int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val) 315 { 316 if (pcr->ops->read_phy) 317 return pcr->ops->read_phy(pcr, addr, val); 318 319 return __rtsx_pci_read_phy_register(pcr, addr, val); 320 } 321 EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register); 322 323 void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr) 324 { 325 if (pcr->ops->stop_cmd) 326 return pcr->ops->stop_cmd(pcr); 327 328 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD); 329 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA); 330 331 rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80); 332 rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80); 333 } 334 EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd); 335 336 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr, 337 u8 cmd_type, u16 reg_addr, u8 mask, u8 data) 338 { 339 unsigned long flags; 340 u32 val = 0; 341 u32 *ptr = (u32 *)(pcr->host_cmds_ptr); 342 343 val |= (u32)(cmd_type & 0x03) << 30; 344 val |= (u32)(reg_addr & 0x3FFF) << 16; 345 val |= (u32)mask << 8; 346 val |= (u32)data; 347 348 spin_lock_irqsave(&pcr->lock, flags); 349 ptr += pcr->ci; 350 if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) { 351 put_unaligned_le32(val, ptr); 352 ptr++; 353 pcr->ci++; 354 } 355 spin_unlock_irqrestore(&pcr->lock, flags); 356 } 357 EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd); 358 359 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr) 360 { 361 u32 val = 1 << 31; 362 363 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr); 364 365 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF; 366 /* Hardware Auto Response */ 367 val |= 0x40000000; 368 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val); 369 } 370 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait); 371 372 int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout) 373 { 374 struct completion trans_done; 375 u32 val = 1 << 31; 376 long timeleft; 377 unsigned long flags; 378 int err = 0; 379 380 spin_lock_irqsave(&pcr->lock, flags); 381 382 /* set up data structures for the wakeup system */ 383 pcr->done = &trans_done; 384 pcr->trans_result = TRANS_NOT_READY; 385 init_completion(&trans_done); 386 387 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr); 388 389 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF; 390 /* Hardware Auto Response */ 391 val |= 0x40000000; 392 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val); 393 394 spin_unlock_irqrestore(&pcr->lock, flags); 395 396 /* Wait for TRANS_OK_INT */ 397 timeleft = wait_for_completion_interruptible_timeout( 398 &trans_done, msecs_to_jiffies(timeout)); 399 if (timeleft <= 0) { 400 pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__); 401 err = -ETIMEDOUT; 402 goto finish_send_cmd; 403 } 404 405 spin_lock_irqsave(&pcr->lock, flags); 406 if (pcr->trans_result == TRANS_RESULT_FAIL) 407 err = -EINVAL; 408 else if (pcr->trans_result == TRANS_RESULT_OK) 409 err = 0; 410 else if (pcr->trans_result == TRANS_NO_DEVICE) 411 err = -ENODEV; 412 spin_unlock_irqrestore(&pcr->lock, flags); 413 414 finish_send_cmd: 415 spin_lock_irqsave(&pcr->lock, flags); 416 pcr->done = NULL; 417 spin_unlock_irqrestore(&pcr->lock, flags); 418 419 if ((err < 0) && (err != -ENODEV)) 420 rtsx_pci_stop_cmd(pcr); 421 422 if (pcr->finish_me) 423 complete(pcr->finish_me); 424 425 return err; 426 } 427 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd); 428 429 static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr, 430 dma_addr_t addr, unsigned int len, int end) 431 { 432 u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi; 433 u64 val; 434 u8 option = RTSX_SG_VALID | RTSX_SG_TRANS_DATA; 435 436 pcr_dbg(pcr, "DMA addr: 0x%x, Len: 0x%x\n", (unsigned int)addr, len); 437 438 if (end) 439 option |= RTSX_SG_END; 440 441 if (PCI_PID(pcr) == PID_5261) { 442 if (len > 0xFFFF) 443 val = ((u64)addr << 32) | (((u64)len & 0xFFFF) << 16) 444 | (((u64)len >> 16) << 6) | option; 445 else 446 val = ((u64)addr << 32) | ((u64)len << 16) | option; 447 } else { 448 val = ((u64)addr << 32) | ((u64)len << 12) | option; 449 } 450 put_unaligned_le64(val, ptr); 451 pcr->sgi++; 452 } 453 454 int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist, 455 int num_sg, bool read, int timeout) 456 { 457 int err = 0, count; 458 459 pcr_dbg(pcr, "--> %s: num_sg = %d\n", __func__, num_sg); 460 count = rtsx_pci_dma_map_sg(pcr, sglist, num_sg, read); 461 if (count < 1) 462 return -EINVAL; 463 pcr_dbg(pcr, "DMA mapping count: %d\n", count); 464 465 err = rtsx_pci_dma_transfer(pcr, sglist, count, read, timeout); 466 467 rtsx_pci_dma_unmap_sg(pcr, sglist, num_sg, read); 468 469 return err; 470 } 471 EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data); 472 473 int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist, 474 int num_sg, bool read) 475 { 476 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 477 478 if (pcr->remove_pci) 479 return -EINVAL; 480 481 if ((sglist == NULL) || (num_sg <= 0)) 482 return -EINVAL; 483 484 return dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dir); 485 } 486 EXPORT_SYMBOL_GPL(rtsx_pci_dma_map_sg); 487 488 void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist, 489 int num_sg, bool read) 490 { 491 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 492 493 dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dir); 494 } 495 EXPORT_SYMBOL_GPL(rtsx_pci_dma_unmap_sg); 496 497 int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist, 498 int count, bool read, int timeout) 499 { 500 struct completion trans_done; 501 struct scatterlist *sg; 502 dma_addr_t addr; 503 long timeleft; 504 unsigned long flags; 505 unsigned int len; 506 int i, err = 0; 507 u32 val; 508 u8 dir = read ? DEVICE_TO_HOST : HOST_TO_DEVICE; 509 510 if (pcr->remove_pci) 511 return -ENODEV; 512 513 if ((sglist == NULL) || (count < 1)) 514 return -EINVAL; 515 516 val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE; 517 pcr->sgi = 0; 518 for_each_sg(sglist, sg, count, i) { 519 addr = sg_dma_address(sg); 520 len = sg_dma_len(sg); 521 rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1); 522 } 523 524 spin_lock_irqsave(&pcr->lock, flags); 525 526 pcr->done = &trans_done; 527 pcr->trans_result = TRANS_NOT_READY; 528 init_completion(&trans_done); 529 rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr); 530 rtsx_pci_writel(pcr, RTSX_HDBCTLR, val); 531 532 spin_unlock_irqrestore(&pcr->lock, flags); 533 534 timeleft = wait_for_completion_interruptible_timeout( 535 &trans_done, msecs_to_jiffies(timeout)); 536 if (timeleft <= 0) { 537 pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__); 538 err = -ETIMEDOUT; 539 goto out; 540 } 541 542 spin_lock_irqsave(&pcr->lock, flags); 543 if (pcr->trans_result == TRANS_RESULT_FAIL) { 544 err = -EILSEQ; 545 if (pcr->dma_error_count < RTS_MAX_TIMES_FREQ_REDUCTION) 546 pcr->dma_error_count++; 547 } 548 549 else if (pcr->trans_result == TRANS_NO_DEVICE) 550 err = -ENODEV; 551 spin_unlock_irqrestore(&pcr->lock, flags); 552 553 out: 554 spin_lock_irqsave(&pcr->lock, flags); 555 pcr->done = NULL; 556 spin_unlock_irqrestore(&pcr->lock, flags); 557 558 if ((err < 0) && (err != -ENODEV)) 559 rtsx_pci_stop_cmd(pcr); 560 561 if (pcr->finish_me) 562 complete(pcr->finish_me); 563 564 return err; 565 } 566 EXPORT_SYMBOL_GPL(rtsx_pci_dma_transfer); 567 568 int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len) 569 { 570 int err; 571 int i, j; 572 u16 reg; 573 u8 *ptr; 574 575 if (buf_len > 512) 576 buf_len = 512; 577 578 ptr = buf; 579 reg = PPBUF_BASE2; 580 for (i = 0; i < buf_len / 256; i++) { 581 rtsx_pci_init_cmd(pcr); 582 583 for (j = 0; j < 256; j++) 584 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0); 585 586 err = rtsx_pci_send_cmd(pcr, 250); 587 if (err < 0) 588 return err; 589 590 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256); 591 ptr += 256; 592 } 593 594 if (buf_len % 256) { 595 rtsx_pci_init_cmd(pcr); 596 597 for (j = 0; j < buf_len % 256; j++) 598 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0); 599 600 err = rtsx_pci_send_cmd(pcr, 250); 601 if (err < 0) 602 return err; 603 } 604 605 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256); 606 607 return 0; 608 } 609 EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf); 610 611 int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len) 612 { 613 int err; 614 int i, j; 615 u16 reg; 616 u8 *ptr; 617 618 if (buf_len > 512) 619 buf_len = 512; 620 621 ptr = buf; 622 reg = PPBUF_BASE2; 623 for (i = 0; i < buf_len / 256; i++) { 624 rtsx_pci_init_cmd(pcr); 625 626 for (j = 0; j < 256; j++) { 627 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 628 reg++, 0xFF, *ptr); 629 ptr++; 630 } 631 632 err = rtsx_pci_send_cmd(pcr, 250); 633 if (err < 0) 634 return err; 635 } 636 637 if (buf_len % 256) { 638 rtsx_pci_init_cmd(pcr); 639 640 for (j = 0; j < buf_len % 256; j++) { 641 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 642 reg++, 0xFF, *ptr); 643 ptr++; 644 } 645 646 err = rtsx_pci_send_cmd(pcr, 250); 647 if (err < 0) 648 return err; 649 } 650 651 return 0; 652 } 653 EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf); 654 655 static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl) 656 { 657 rtsx_pci_init_cmd(pcr); 658 659 while (*tbl & 0xFFFF0000) { 660 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 661 (u16)(*tbl >> 16), 0xFF, (u8)(*tbl)); 662 tbl++; 663 } 664 665 return rtsx_pci_send_cmd(pcr, 100); 666 } 667 668 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card) 669 { 670 const u32 *tbl; 671 672 if (card == RTSX_SD_CARD) 673 tbl = pcr->sd_pull_ctl_enable_tbl; 674 else if (card == RTSX_MS_CARD) 675 tbl = pcr->ms_pull_ctl_enable_tbl; 676 else 677 return -EINVAL; 678 679 return rtsx_pci_set_pull_ctl(pcr, tbl); 680 } 681 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable); 682 683 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card) 684 { 685 const u32 *tbl; 686 687 if (card == RTSX_SD_CARD) 688 tbl = pcr->sd_pull_ctl_disable_tbl; 689 else if (card == RTSX_MS_CARD) 690 tbl = pcr->ms_pull_ctl_disable_tbl; 691 else 692 return -EINVAL; 693 694 return rtsx_pci_set_pull_ctl(pcr, tbl); 695 } 696 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable); 697 698 static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr) 699 { 700 struct rtsx_hw_param *hw_param = &pcr->hw_param; 701 702 pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN 703 | hw_param->interrupt_en; 704 705 if (pcr->num_slots > 1) 706 pcr->bier |= MS_INT_EN; 707 708 /* Enable Bus Interrupt */ 709 rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier); 710 711 pcr_dbg(pcr, "RTSX_BIER: 0x%08x\n", pcr->bier); 712 } 713 714 static inline u8 double_ssc_depth(u8 depth) 715 { 716 return ((depth > 1) ? (depth - 1) : depth); 717 } 718 719 static u8 revise_ssc_depth(u8 ssc_depth, u8 div) 720 { 721 if (div > CLK_DIV_1) { 722 if (ssc_depth > (div - 1)) 723 ssc_depth -= (div - 1); 724 else 725 ssc_depth = SSC_DEPTH_4M; 726 } 727 728 return ssc_depth; 729 } 730 731 int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, 732 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk) 733 { 734 int err, clk; 735 u8 n, clk_divider, mcu_cnt, div; 736 static const u8 depth[] = { 737 [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M, 738 [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M, 739 [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M, 740 [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K, 741 [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K, 742 }; 743 744 if (PCI_PID(pcr) == PID_5261) 745 return rts5261_pci_switch_clock(pcr, card_clock, 746 ssc_depth, initial_mode, double_clk, vpclk); 747 748 if (initial_mode) { 749 /* We use 250k(around) here, in initial stage */ 750 clk_divider = SD_CLK_DIVIDE_128; 751 card_clock = 30000000; 752 } else { 753 clk_divider = SD_CLK_DIVIDE_0; 754 } 755 err = rtsx_pci_write_register(pcr, SD_CFG1, 756 SD_CLK_DIVIDE_MASK, clk_divider); 757 if (err < 0) 758 return err; 759 760 /* Reduce card clock by 20MHz each time a DMA transfer error occurs */ 761 if (card_clock == UHS_SDR104_MAX_DTR && 762 pcr->dma_error_count && 763 PCI_PID(pcr) == RTS5227_DEVICE_ID) 764 card_clock = UHS_SDR104_MAX_DTR - 765 (pcr->dma_error_count * 20000000); 766 767 card_clock /= 1000000; 768 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock); 769 770 clk = card_clock; 771 if (!initial_mode && double_clk) 772 clk = card_clock * 2; 773 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n", 774 clk, pcr->cur_clock); 775 776 if (clk == pcr->cur_clock) 777 return 0; 778 779 if (pcr->ops->conv_clk_and_div_n) 780 n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N); 781 else 782 n = (u8)(clk - 2); 783 if ((clk <= 2) || (n > MAX_DIV_N_PCR)) 784 return -EINVAL; 785 786 mcu_cnt = (u8)(125/clk + 3); 787 if (mcu_cnt > 15) 788 mcu_cnt = 15; 789 790 /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */ 791 div = CLK_DIV_1; 792 while ((n < MIN_DIV_N_PCR) && (div < CLK_DIV_8)) { 793 if (pcr->ops->conv_clk_and_div_n) { 794 int dbl_clk = pcr->ops->conv_clk_and_div_n(n, 795 DIV_N_TO_CLK) * 2; 796 n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk, 797 CLK_TO_DIV_N); 798 } else { 799 n = (n + 2) * 2 - 2; 800 } 801 div++; 802 } 803 pcr_dbg(pcr, "n = %d, div = %d\n", n, div); 804 805 ssc_depth = depth[ssc_depth]; 806 if (double_clk) 807 ssc_depth = double_ssc_depth(ssc_depth); 808 809 ssc_depth = revise_ssc_depth(ssc_depth, div); 810 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth); 811 812 rtsx_pci_init_cmd(pcr); 813 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 814 CLK_LOW_FREQ, CLK_LOW_FREQ); 815 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 816 0xFF, (div << 4) | mcu_cnt); 817 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); 818 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 819 SSC_DEPTH_MASK, ssc_depth); 820 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n); 821 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB); 822 if (vpclk) { 823 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, 824 PHASE_NOT_RESET, 0); 825 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, 826 PHASE_NOT_RESET, PHASE_NOT_RESET); 827 } 828 829 err = rtsx_pci_send_cmd(pcr, 2000); 830 if (err < 0) 831 return err; 832 833 /* Wait SSC clock stable */ 834 udelay(SSC_CLOCK_STABLE_WAIT); 835 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); 836 if (err < 0) 837 return err; 838 839 pcr->cur_clock = clk; 840 return 0; 841 } 842 EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock); 843 844 int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card) 845 { 846 if (pcr->ops->card_power_on) 847 return pcr->ops->card_power_on(pcr, card); 848 849 return 0; 850 } 851 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on); 852 853 int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card) 854 { 855 if (pcr->ops->card_power_off) 856 return pcr->ops->card_power_off(pcr, card); 857 858 return 0; 859 } 860 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off); 861 862 int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card) 863 { 864 static const unsigned int cd_mask[] = { 865 [RTSX_SD_CARD] = SD_EXIST, 866 [RTSX_MS_CARD] = MS_EXIST 867 }; 868 869 if (!(pcr->flags & PCR_MS_PMOS)) { 870 /* When using single PMOS, accessing card is not permitted 871 * if the existing card is not the designated one. 872 */ 873 if (pcr->card_exist & (~cd_mask[card])) 874 return -EIO; 875 } 876 877 return 0; 878 } 879 EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check); 880 881 int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) 882 { 883 if (pcr->ops->switch_output_voltage) 884 return pcr->ops->switch_output_voltage(pcr, voltage); 885 886 return 0; 887 } 888 EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage); 889 890 unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr) 891 { 892 unsigned int val; 893 894 val = rtsx_pci_readl(pcr, RTSX_BIPR); 895 if (pcr->ops->cd_deglitch) 896 val = pcr->ops->cd_deglitch(pcr); 897 898 return val; 899 } 900 EXPORT_SYMBOL_GPL(rtsx_pci_card_exist); 901 902 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr) 903 { 904 struct completion finish; 905 906 pcr->finish_me = &finish; 907 init_completion(&finish); 908 909 if (pcr->done) 910 complete(pcr->done); 911 912 if (!pcr->remove_pci) 913 rtsx_pci_stop_cmd(pcr); 914 915 wait_for_completion_interruptible_timeout(&finish, 916 msecs_to_jiffies(2)); 917 pcr->finish_me = NULL; 918 } 919 EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer); 920 921 static void rtsx_pci_card_detect(struct work_struct *work) 922 { 923 struct delayed_work *dwork; 924 struct rtsx_pcr *pcr; 925 unsigned long flags; 926 unsigned int card_detect = 0, card_inserted, card_removed; 927 u32 irq_status; 928 929 dwork = to_delayed_work(work); 930 pcr = container_of(dwork, struct rtsx_pcr, carddet_work); 931 932 pcr_dbg(pcr, "--> %s\n", __func__); 933 934 mutex_lock(&pcr->pcr_mutex); 935 spin_lock_irqsave(&pcr->lock, flags); 936 937 irq_status = rtsx_pci_readl(pcr, RTSX_BIPR); 938 pcr_dbg(pcr, "irq_status: 0x%08x\n", irq_status); 939 940 irq_status &= CARD_EXIST; 941 card_inserted = pcr->card_inserted & irq_status; 942 card_removed = pcr->card_removed; 943 pcr->card_inserted = 0; 944 pcr->card_removed = 0; 945 946 spin_unlock_irqrestore(&pcr->lock, flags); 947 948 if (card_inserted || card_removed) { 949 pcr_dbg(pcr, "card_inserted: 0x%x, card_removed: 0x%x\n", 950 card_inserted, card_removed); 951 952 if (pcr->ops->cd_deglitch) 953 card_inserted = pcr->ops->cd_deglitch(pcr); 954 955 card_detect = card_inserted | card_removed; 956 957 pcr->card_exist |= card_inserted; 958 pcr->card_exist &= ~card_removed; 959 } 960 961 mutex_unlock(&pcr->pcr_mutex); 962 963 if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event) 964 pcr->slots[RTSX_SD_CARD].card_event( 965 pcr->slots[RTSX_SD_CARD].p_dev); 966 if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event) 967 pcr->slots[RTSX_MS_CARD].card_event( 968 pcr->slots[RTSX_MS_CARD].p_dev); 969 } 970 971 static void rtsx_pci_process_ocp(struct rtsx_pcr *pcr) 972 { 973 if (pcr->ops->process_ocp) { 974 pcr->ops->process_ocp(pcr); 975 } else { 976 if (!pcr->option.ocp_en) 977 return; 978 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat); 979 if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) { 980 rtsx_pci_card_power_off(pcr, RTSX_SD_CARD); 981 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0); 982 rtsx_pci_clear_ocpstat(pcr); 983 pcr->ocp_stat = 0; 984 } 985 } 986 } 987 988 static int rtsx_pci_process_ocp_interrupt(struct rtsx_pcr *pcr) 989 { 990 if (pcr->option.ocp_en) 991 rtsx_pci_process_ocp(pcr); 992 993 return 0; 994 } 995 996 static irqreturn_t rtsx_pci_isr(int irq, void *dev_id) 997 { 998 struct rtsx_pcr *pcr = dev_id; 999 u32 int_reg; 1000 1001 if (!pcr) 1002 return IRQ_NONE; 1003 1004 spin_lock(&pcr->lock); 1005 1006 int_reg = rtsx_pci_readl(pcr, RTSX_BIPR); 1007 /* Clear interrupt flag */ 1008 rtsx_pci_writel(pcr, RTSX_BIPR, int_reg); 1009 if ((int_reg & pcr->bier) == 0) { 1010 spin_unlock(&pcr->lock); 1011 return IRQ_NONE; 1012 } 1013 if (int_reg == 0xFFFFFFFF) { 1014 spin_unlock(&pcr->lock); 1015 return IRQ_HANDLED; 1016 } 1017 1018 int_reg &= (pcr->bier | 0x7FFFFF); 1019 1020 if (int_reg & SD_OC_INT) 1021 rtsx_pci_process_ocp_interrupt(pcr); 1022 1023 if (int_reg & SD_INT) { 1024 if (int_reg & SD_EXIST) { 1025 pcr->card_inserted |= SD_EXIST; 1026 } else { 1027 pcr->card_removed |= SD_EXIST; 1028 pcr->card_inserted &= ~SD_EXIST; 1029 } 1030 pcr->dma_error_count = 0; 1031 } 1032 1033 if (int_reg & MS_INT) { 1034 if (int_reg & MS_EXIST) { 1035 pcr->card_inserted |= MS_EXIST; 1036 } else { 1037 pcr->card_removed |= MS_EXIST; 1038 pcr->card_inserted &= ~MS_EXIST; 1039 } 1040 } 1041 1042 if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) { 1043 if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) { 1044 pcr->trans_result = TRANS_RESULT_FAIL; 1045 if (pcr->done) 1046 complete(pcr->done); 1047 } else if (int_reg & TRANS_OK_INT) { 1048 pcr->trans_result = TRANS_RESULT_OK; 1049 if (pcr->done) 1050 complete(pcr->done); 1051 } 1052 } 1053 1054 if ((pcr->card_inserted || pcr->card_removed) && !(int_reg & SD_OC_INT)) 1055 schedule_delayed_work(&pcr->carddet_work, 1056 msecs_to_jiffies(200)); 1057 1058 spin_unlock(&pcr->lock); 1059 return IRQ_HANDLED; 1060 } 1061 1062 static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr) 1063 { 1064 pcr_dbg(pcr, "%s: pcr->msi_en = %d, pci->irq = %d\n", 1065 __func__, pcr->msi_en, pcr->pci->irq); 1066 1067 if (request_irq(pcr->pci->irq, rtsx_pci_isr, 1068 pcr->msi_en ? 0 : IRQF_SHARED, 1069 DRV_NAME_RTSX_PCI, pcr)) { 1070 dev_err(&(pcr->pci->dev), 1071 "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n", 1072 pcr->pci->irq); 1073 return -1; 1074 } 1075 1076 pcr->irq = pcr->pci->irq; 1077 pci_intx(pcr->pci, !pcr->msi_en); 1078 1079 return 0; 1080 } 1081 1082 static void rtsx_enable_aspm(struct rtsx_pcr *pcr) 1083 { 1084 if (pcr->ops->set_aspm) 1085 pcr->ops->set_aspm(pcr, true); 1086 else 1087 rtsx_comm_set_aspm(pcr, true); 1088 } 1089 1090 static void rtsx_comm_pm_power_saving(struct rtsx_pcr *pcr) 1091 { 1092 struct rtsx_cr_option *option = &pcr->option; 1093 1094 if (option->ltr_enabled) { 1095 u32 latency = option->ltr_l1off_latency; 1096 1097 if (rtsx_check_dev_flag(pcr, L1_SNOOZE_TEST_EN)) 1098 mdelay(option->l1_snooze_delay); 1099 1100 rtsx_set_ltr_latency(pcr, latency); 1101 } 1102 1103 if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_EN)) 1104 rtsx_set_l1off_sub_cfg_d0(pcr, 0); 1105 1106 rtsx_enable_aspm(pcr); 1107 } 1108 1109 static void rtsx_pm_power_saving(struct rtsx_pcr *pcr) 1110 { 1111 if (pcr->ops->power_saving) 1112 pcr->ops->power_saving(pcr); 1113 else 1114 rtsx_comm_pm_power_saving(pcr); 1115 } 1116 1117 static void rtsx_pci_idle_work(struct work_struct *work) 1118 { 1119 struct delayed_work *dwork = to_delayed_work(work); 1120 struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work); 1121 1122 pcr_dbg(pcr, "--> %s\n", __func__); 1123 1124 mutex_lock(&pcr->pcr_mutex); 1125 1126 pcr->state = PDEV_STAT_IDLE; 1127 1128 if (pcr->ops->disable_auto_blink) 1129 pcr->ops->disable_auto_blink(pcr); 1130 if (pcr->ops->turn_off_led) 1131 pcr->ops->turn_off_led(pcr); 1132 1133 rtsx_pm_power_saving(pcr); 1134 1135 mutex_unlock(&pcr->pcr_mutex); 1136 } 1137 1138 #ifdef CONFIG_PM 1139 static void rtsx_pci_power_off(struct rtsx_pcr *pcr, u8 pm_state) 1140 { 1141 if (pcr->ops->turn_off_led) 1142 pcr->ops->turn_off_led(pcr); 1143 1144 rtsx_pci_writel(pcr, RTSX_BIER, 0); 1145 pcr->bier = 0; 1146 1147 rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08); 1148 rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, pm_state); 1149 1150 if (pcr->ops->force_power_down) 1151 pcr->ops->force_power_down(pcr, pm_state); 1152 } 1153 #endif 1154 1155 void rtsx_pci_enable_ocp(struct rtsx_pcr *pcr) 1156 { 1157 u8 val = SD_OCP_INT_EN | SD_DETECT_EN; 1158 1159 if (pcr->ops->enable_ocp) { 1160 pcr->ops->enable_ocp(pcr); 1161 } else { 1162 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0); 1163 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val); 1164 } 1165 1166 } 1167 1168 void rtsx_pci_disable_ocp(struct rtsx_pcr *pcr) 1169 { 1170 u8 mask = SD_OCP_INT_EN | SD_DETECT_EN; 1171 1172 if (pcr->ops->disable_ocp) { 1173 pcr->ops->disable_ocp(pcr); 1174 } else { 1175 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); 1176 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 1177 OC_POWER_DOWN); 1178 } 1179 } 1180 1181 void rtsx_pci_init_ocp(struct rtsx_pcr *pcr) 1182 { 1183 if (pcr->ops->init_ocp) { 1184 pcr->ops->init_ocp(pcr); 1185 } else { 1186 struct rtsx_cr_option *option = &(pcr->option); 1187 1188 if (option->ocp_en) { 1189 u8 val = option->sd_800mA_ocp_thd; 1190 1191 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0); 1192 rtsx_pci_write_register(pcr, REG_OCPPARA1, 1193 SD_OCP_TIME_MASK, SD_OCP_TIME_800); 1194 rtsx_pci_write_register(pcr, REG_OCPPARA2, 1195 SD_OCP_THD_MASK, val); 1196 rtsx_pci_write_register(pcr, REG_OCPGLITCH, 1197 SD_OCP_GLITCH_MASK, pcr->hw_param.ocp_glitch); 1198 rtsx_pci_enable_ocp(pcr); 1199 } else { 1200 /* OC power down */ 1201 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 1202 OC_POWER_DOWN); 1203 } 1204 } 1205 } 1206 1207 int rtsx_pci_get_ocpstat(struct rtsx_pcr *pcr, u8 *val) 1208 { 1209 if (pcr->ops->get_ocpstat) 1210 return pcr->ops->get_ocpstat(pcr, val); 1211 else 1212 return rtsx_pci_read_register(pcr, REG_OCPSTAT, val); 1213 } 1214 1215 void rtsx_pci_clear_ocpstat(struct rtsx_pcr *pcr) 1216 { 1217 if (pcr->ops->clear_ocpstat) { 1218 pcr->ops->clear_ocpstat(pcr); 1219 } else { 1220 u8 mask = SD_OCP_INT_CLR | SD_OC_CLR; 1221 u8 val = SD_OCP_INT_CLR | SD_OC_CLR; 1222 1223 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val); 1224 udelay(100); 1225 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); 1226 } 1227 } 1228 1229 int rtsx_sd_power_off_card3v3(struct rtsx_pcr *pcr) 1230 { 1231 rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN | 1232 MS_CLK_EN | SD40_CLK_EN, 0); 1233 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0); 1234 rtsx_pci_card_power_off(pcr, RTSX_SD_CARD); 1235 1236 msleep(50); 1237 1238 rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD); 1239 1240 return 0; 1241 } 1242 1243 int rtsx_ms_power_off_card3v3(struct rtsx_pcr *pcr) 1244 { 1245 rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN | 1246 MS_CLK_EN | SD40_CLK_EN, 0); 1247 1248 rtsx_pci_card_pull_ctl_disable(pcr, RTSX_MS_CARD); 1249 1250 rtsx_pci_write_register(pcr, CARD_OE, MS_OUTPUT_EN, 0); 1251 rtsx_pci_card_power_off(pcr, RTSX_MS_CARD); 1252 1253 return 0; 1254 } 1255 1256 static int rtsx_pci_init_hw(struct rtsx_pcr *pcr) 1257 { 1258 int err; 1259 1260 pcr->pcie_cap = pci_find_capability(pcr->pci, PCI_CAP_ID_EXP); 1261 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr); 1262 1263 rtsx_pci_enable_bus_int(pcr); 1264 1265 /* Power on SSC */ 1266 if (PCI_PID(pcr) == PID_5261) { 1267 /* Gating real mcu clock */ 1268 err = rtsx_pci_write_register(pcr, RTS5261_FW_CFG1, 1269 RTS5261_MCU_CLOCK_GATING, 0); 1270 err = rtsx_pci_write_register(pcr, RTS5261_REG_FPDCTL, 1271 SSC_POWER_DOWN, 0); 1272 } else { 1273 err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0); 1274 } 1275 if (err < 0) 1276 return err; 1277 1278 /* Wait SSC power stable */ 1279 udelay(200); 1280 1281 rtsx_pci_disable_aspm(pcr); 1282 if (pcr->ops->optimize_phy) { 1283 err = pcr->ops->optimize_phy(pcr); 1284 if (err < 0) 1285 return err; 1286 } 1287 1288 rtsx_pci_init_cmd(pcr); 1289 1290 /* Set mcu_cnt to 7 to ensure data can be sampled properly */ 1291 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07); 1292 1293 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00); 1294 /* Disable card clock */ 1295 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0); 1296 /* Reset delink mode */ 1297 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0); 1298 /* Card driving select */ 1299 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL, 1300 0xFF, pcr->card_drive_sel); 1301 /* Enable SSC Clock */ 1302 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, 1303 0xFF, SSC_8X_EN | SSC_SEL_4M); 1304 if (PCI_PID(pcr) == PID_5261) 1305 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 1306 RTS5261_SSC_DEPTH_2M); 1307 else 1308 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12); 1309 1310 /* Disable cd_pwr_save */ 1311 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10); 1312 /* Clear Link Ready Interrupt */ 1313 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, 1314 LINK_RDY_INT, LINK_RDY_INT); 1315 /* Enlarge the estimation window of PERST# glitch 1316 * to reduce the chance of invalid card interrupt 1317 */ 1318 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80); 1319 /* Update RC oscillator to 400k 1320 * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1 1321 * 1: 2M 0: 400k 1322 */ 1323 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00); 1324 /* Set interrupt write clear 1325 * bit 1: U_elbi_if_rd_clr_en 1326 * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear 1327 * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear 1328 */ 1329 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0); 1330 1331 err = rtsx_pci_send_cmd(pcr, 100); 1332 if (err < 0) 1333 return err; 1334 1335 switch (PCI_PID(pcr)) { 1336 case PID_5250: 1337 case PID_524A: 1338 case PID_525A: 1339 case PID_5260: 1340 case PID_5261: 1341 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 1, 1); 1342 break; 1343 default: 1344 break; 1345 } 1346 1347 /*init ocp*/ 1348 rtsx_pci_init_ocp(pcr); 1349 1350 /* Enable clk_request_n to enable clock power management */ 1351 rtsx_pci_write_config_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL + 1, 1); 1352 /* Enter L1 when host tx idle */ 1353 rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B); 1354 1355 if (pcr->ops->extra_init_hw) { 1356 err = pcr->ops->extra_init_hw(pcr); 1357 if (err < 0) 1358 return err; 1359 } 1360 1361 /* No CD interrupt if probing driver with card inserted. 1362 * So we need to initialize pcr->card_exist here. 1363 */ 1364 if (pcr->ops->cd_deglitch) 1365 pcr->card_exist = pcr->ops->cd_deglitch(pcr); 1366 else 1367 pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST; 1368 1369 return 0; 1370 } 1371 1372 static int rtsx_pci_init_chip(struct rtsx_pcr *pcr) 1373 { 1374 int err; 1375 1376 spin_lock_init(&pcr->lock); 1377 mutex_init(&pcr->pcr_mutex); 1378 1379 switch (PCI_PID(pcr)) { 1380 default: 1381 case 0x5209: 1382 rts5209_init_params(pcr); 1383 break; 1384 1385 case 0x5229: 1386 rts5229_init_params(pcr); 1387 break; 1388 1389 case 0x5289: 1390 rtl8411_init_params(pcr); 1391 break; 1392 1393 case 0x5227: 1394 rts5227_init_params(pcr); 1395 break; 1396 1397 case 0x522A: 1398 rts522a_init_params(pcr); 1399 break; 1400 1401 case 0x5249: 1402 rts5249_init_params(pcr); 1403 break; 1404 1405 case 0x524A: 1406 rts524a_init_params(pcr); 1407 break; 1408 1409 case 0x525A: 1410 rts525a_init_params(pcr); 1411 break; 1412 1413 case 0x5287: 1414 rtl8411b_init_params(pcr); 1415 break; 1416 1417 case 0x5286: 1418 rtl8402_init_params(pcr); 1419 break; 1420 1421 case 0x5260: 1422 rts5260_init_params(pcr); 1423 break; 1424 1425 case 0x5261: 1426 rts5261_init_params(pcr); 1427 break; 1428 } 1429 1430 pcr_dbg(pcr, "PID: 0x%04x, IC version: 0x%02x\n", 1431 PCI_PID(pcr), pcr->ic_version); 1432 1433 pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot), 1434 GFP_KERNEL); 1435 if (!pcr->slots) 1436 return -ENOMEM; 1437 1438 if (pcr->ops->fetch_vendor_settings) 1439 pcr->ops->fetch_vendor_settings(pcr); 1440 1441 pcr_dbg(pcr, "pcr->aspm_en = 0x%x\n", pcr->aspm_en); 1442 pcr_dbg(pcr, "pcr->sd30_drive_sel_1v8 = 0x%x\n", 1443 pcr->sd30_drive_sel_1v8); 1444 pcr_dbg(pcr, "pcr->sd30_drive_sel_3v3 = 0x%x\n", 1445 pcr->sd30_drive_sel_3v3); 1446 pcr_dbg(pcr, "pcr->card_drive_sel = 0x%x\n", 1447 pcr->card_drive_sel); 1448 pcr_dbg(pcr, "pcr->flags = 0x%x\n", pcr->flags); 1449 1450 pcr->state = PDEV_STAT_IDLE; 1451 err = rtsx_pci_init_hw(pcr); 1452 if (err < 0) { 1453 kfree(pcr->slots); 1454 return err; 1455 } 1456 1457 return 0; 1458 } 1459 1460 static int rtsx_pci_probe(struct pci_dev *pcidev, 1461 const struct pci_device_id *id) 1462 { 1463 struct rtsx_pcr *pcr; 1464 struct pcr_handle *handle; 1465 u32 base, len; 1466 int ret, i, bar = 0; 1467 1468 dev_dbg(&(pcidev->dev), 1469 ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n", 1470 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device, 1471 (int)pcidev->revision); 1472 1473 ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32)); 1474 if (ret < 0) 1475 return ret; 1476 1477 ret = pci_enable_device(pcidev); 1478 if (ret) 1479 return ret; 1480 1481 ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI); 1482 if (ret) 1483 goto disable; 1484 1485 pcr = kzalloc(sizeof(*pcr), GFP_KERNEL); 1486 if (!pcr) { 1487 ret = -ENOMEM; 1488 goto release_pci; 1489 } 1490 1491 handle = kzalloc(sizeof(*handle), GFP_KERNEL); 1492 if (!handle) { 1493 ret = -ENOMEM; 1494 goto free_pcr; 1495 } 1496 handle->pcr = pcr; 1497 1498 idr_preload(GFP_KERNEL); 1499 spin_lock(&rtsx_pci_lock); 1500 ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT); 1501 if (ret >= 0) 1502 pcr->id = ret; 1503 spin_unlock(&rtsx_pci_lock); 1504 idr_preload_end(); 1505 if (ret < 0) 1506 goto free_handle; 1507 1508 pcr->pci = pcidev; 1509 dev_set_drvdata(&pcidev->dev, handle); 1510 1511 if (CHK_PCI_PID(pcr, 0x525A)) 1512 bar = 1; 1513 len = pci_resource_len(pcidev, bar); 1514 base = pci_resource_start(pcidev, bar); 1515 pcr->remap_addr = ioremap(base, len); 1516 if (!pcr->remap_addr) { 1517 ret = -ENOMEM; 1518 goto free_handle; 1519 } 1520 1521 pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev), 1522 RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr), 1523 GFP_KERNEL); 1524 if (pcr->rtsx_resv_buf == NULL) { 1525 ret = -ENXIO; 1526 goto unmap; 1527 } 1528 pcr->host_cmds_ptr = pcr->rtsx_resv_buf; 1529 pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr; 1530 pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN; 1531 pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN; 1532 1533 pcr->card_inserted = 0; 1534 pcr->card_removed = 0; 1535 INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect); 1536 INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work); 1537 1538 pcr->msi_en = msi_en; 1539 if (pcr->msi_en) { 1540 ret = pci_enable_msi(pcidev); 1541 if (ret) 1542 pcr->msi_en = false; 1543 } 1544 1545 ret = rtsx_pci_acquire_irq(pcr); 1546 if (ret < 0) 1547 goto disable_msi; 1548 1549 pci_set_master(pcidev); 1550 synchronize_irq(pcr->irq); 1551 1552 ret = rtsx_pci_init_chip(pcr); 1553 if (ret < 0) 1554 goto disable_irq; 1555 1556 for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) { 1557 rtsx_pcr_cells[i].platform_data = handle; 1558 rtsx_pcr_cells[i].pdata_size = sizeof(*handle); 1559 } 1560 ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells, 1561 ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL); 1562 if (ret < 0) 1563 goto disable_irq; 1564 1565 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200)); 1566 1567 return 0; 1568 1569 disable_irq: 1570 free_irq(pcr->irq, (void *)pcr); 1571 disable_msi: 1572 if (pcr->msi_en) 1573 pci_disable_msi(pcr->pci); 1574 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN, 1575 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr); 1576 unmap: 1577 iounmap(pcr->remap_addr); 1578 free_handle: 1579 kfree(handle); 1580 free_pcr: 1581 kfree(pcr); 1582 release_pci: 1583 pci_release_regions(pcidev); 1584 disable: 1585 pci_disable_device(pcidev); 1586 1587 return ret; 1588 } 1589 1590 static void rtsx_pci_remove(struct pci_dev *pcidev) 1591 { 1592 struct pcr_handle *handle = pci_get_drvdata(pcidev); 1593 struct rtsx_pcr *pcr = handle->pcr; 1594 1595 pcr->remove_pci = true; 1596 1597 /* Disable interrupts at the pcr level */ 1598 spin_lock_irq(&pcr->lock); 1599 rtsx_pci_writel(pcr, RTSX_BIER, 0); 1600 pcr->bier = 0; 1601 spin_unlock_irq(&pcr->lock); 1602 1603 cancel_delayed_work_sync(&pcr->carddet_work); 1604 cancel_delayed_work_sync(&pcr->idle_work); 1605 1606 mfd_remove_devices(&pcidev->dev); 1607 1608 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN, 1609 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr); 1610 free_irq(pcr->irq, (void *)pcr); 1611 if (pcr->msi_en) 1612 pci_disable_msi(pcr->pci); 1613 iounmap(pcr->remap_addr); 1614 1615 pci_release_regions(pcidev); 1616 pci_disable_device(pcidev); 1617 1618 spin_lock(&rtsx_pci_lock); 1619 idr_remove(&rtsx_pci_idr, pcr->id); 1620 spin_unlock(&rtsx_pci_lock); 1621 1622 kfree(pcr->slots); 1623 kfree(pcr); 1624 kfree(handle); 1625 1626 dev_dbg(&(pcidev->dev), 1627 ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n", 1628 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device); 1629 } 1630 1631 #ifdef CONFIG_PM 1632 1633 static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state) 1634 { 1635 struct pcr_handle *handle; 1636 struct rtsx_pcr *pcr; 1637 1638 dev_dbg(&(pcidev->dev), "--> %s\n", __func__); 1639 1640 handle = pci_get_drvdata(pcidev); 1641 pcr = handle->pcr; 1642 1643 cancel_delayed_work(&pcr->carddet_work); 1644 cancel_delayed_work(&pcr->idle_work); 1645 1646 mutex_lock(&pcr->pcr_mutex); 1647 1648 rtsx_pci_power_off(pcr, HOST_ENTER_S3); 1649 1650 pci_save_state(pcidev); 1651 pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0); 1652 pci_disable_device(pcidev); 1653 pci_set_power_state(pcidev, pci_choose_state(pcidev, state)); 1654 1655 mutex_unlock(&pcr->pcr_mutex); 1656 return 0; 1657 } 1658 1659 static int rtsx_pci_resume(struct pci_dev *pcidev) 1660 { 1661 struct pcr_handle *handle; 1662 struct rtsx_pcr *pcr; 1663 int ret = 0; 1664 1665 dev_dbg(&(pcidev->dev), "--> %s\n", __func__); 1666 1667 handle = pci_get_drvdata(pcidev); 1668 pcr = handle->pcr; 1669 1670 mutex_lock(&pcr->pcr_mutex); 1671 1672 pci_set_power_state(pcidev, PCI_D0); 1673 pci_restore_state(pcidev); 1674 ret = pci_enable_device(pcidev); 1675 if (ret) 1676 goto out; 1677 pci_set_master(pcidev); 1678 1679 ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00); 1680 if (ret) 1681 goto out; 1682 1683 ret = rtsx_pci_init_hw(pcr); 1684 if (ret) 1685 goto out; 1686 1687 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200)); 1688 1689 out: 1690 mutex_unlock(&pcr->pcr_mutex); 1691 return ret; 1692 } 1693 1694 static void rtsx_pci_shutdown(struct pci_dev *pcidev) 1695 { 1696 struct pcr_handle *handle; 1697 struct rtsx_pcr *pcr; 1698 1699 dev_dbg(&(pcidev->dev), "--> %s\n", __func__); 1700 1701 handle = pci_get_drvdata(pcidev); 1702 pcr = handle->pcr; 1703 rtsx_pci_power_off(pcr, HOST_ENTER_S1); 1704 1705 pci_disable_device(pcidev); 1706 free_irq(pcr->irq, (void *)pcr); 1707 if (pcr->msi_en) 1708 pci_disable_msi(pcr->pci); 1709 } 1710 1711 #else /* CONFIG_PM */ 1712 1713 #define rtsx_pci_suspend NULL 1714 #define rtsx_pci_resume NULL 1715 #define rtsx_pci_shutdown NULL 1716 1717 #endif /* CONFIG_PM */ 1718 1719 static struct pci_driver rtsx_pci_driver = { 1720 .name = DRV_NAME_RTSX_PCI, 1721 .id_table = rtsx_pci_ids, 1722 .probe = rtsx_pci_probe, 1723 .remove = rtsx_pci_remove, 1724 .suspend = rtsx_pci_suspend, 1725 .resume = rtsx_pci_resume, 1726 .shutdown = rtsx_pci_shutdown, 1727 }; 1728 module_pci_driver(rtsx_pci_driver); 1729 1730 MODULE_LICENSE("GPL"); 1731 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>"); 1732 MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver"); 1733