1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Driver for Realtek PCI-Express card reader 3 * 4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 5 * 6 * Author: 7 * Wei WANG <wei_wang@realsil.com.cn> 8 */ 9 10 #include <linux/pci.h> 11 #include <linux/module.h> 12 #include <linux/slab.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/highmem.h> 15 #include <linux/interrupt.h> 16 #include <linux/delay.h> 17 #include <linux/idr.h> 18 #include <linux/platform_device.h> 19 #include <linux/mfd/core.h> 20 #include <linux/rtsx_pci.h> 21 #include <linux/mmc/card.h> 22 #include <asm/unaligned.h> 23 #include <linux/pm.h> 24 #include <linux/pm_runtime.h> 25 26 #include "rtsx_pcr.h" 27 #include "rts5261.h" 28 #include "rts5228.h" 29 30 static bool msi_en = true; 31 module_param(msi_en, bool, S_IRUGO | S_IWUSR); 32 MODULE_PARM_DESC(msi_en, "Enable MSI"); 33 34 static DEFINE_IDR(rtsx_pci_idr); 35 static DEFINE_SPINLOCK(rtsx_pci_lock); 36 37 static struct mfd_cell rtsx_pcr_cells[] = { 38 [RTSX_SD_CARD] = { 39 .name = DRV_NAME_RTSX_PCI_SDMMC, 40 }, 41 }; 42 43 static const struct pci_device_id rtsx_pci_ids[] = { 44 { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 45 { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 46 { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 47 { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 48 { PCI_DEVICE(0x10EC, 0x522A), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 49 { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 50 { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 51 { PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 52 { PCI_DEVICE(0x10EC, 0x524A), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 53 { PCI_DEVICE(0x10EC, 0x525A), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 54 { PCI_DEVICE(0x10EC, 0x5260), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 55 { PCI_DEVICE(0x10EC, 0x5261), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 56 { PCI_DEVICE(0x10EC, 0x5228), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 57 { 0, } 58 }; 59 60 MODULE_DEVICE_TABLE(pci, rtsx_pci_ids); 61 62 static inline void rtsx_pci_disable_aspm(struct rtsx_pcr *pcr) 63 { 64 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, 65 PCI_EXP_LNKCTL_ASPMC, 0); 66 } 67 68 static int rtsx_comm_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency) 69 { 70 rtsx_pci_write_register(pcr, MSGTXDATA0, 71 MASK_8_BIT_DEF, (u8) (latency & 0xFF)); 72 rtsx_pci_write_register(pcr, MSGTXDATA1, 73 MASK_8_BIT_DEF, (u8)((latency >> 8) & 0xFF)); 74 rtsx_pci_write_register(pcr, MSGTXDATA2, 75 MASK_8_BIT_DEF, (u8)((latency >> 16) & 0xFF)); 76 rtsx_pci_write_register(pcr, MSGTXDATA3, 77 MASK_8_BIT_DEF, (u8)((latency >> 24) & 0xFF)); 78 rtsx_pci_write_register(pcr, LTR_CTL, LTR_TX_EN_MASK | 79 LTR_LATENCY_MODE_MASK, LTR_TX_EN_1 | LTR_LATENCY_MODE_SW); 80 81 return 0; 82 } 83 84 int rtsx_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency) 85 { 86 return rtsx_comm_set_ltr_latency(pcr, latency); 87 } 88 89 static void rtsx_comm_set_aspm(struct rtsx_pcr *pcr, bool enable) 90 { 91 if (pcr->aspm_enabled == enable) 92 return; 93 94 if (pcr->aspm_en & 0x02) 95 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, FORCE_ASPM_CTL0 | 96 FORCE_ASPM_CTL1, enable ? 0 : FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1); 97 else 98 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, FORCE_ASPM_CTL0 | 99 FORCE_ASPM_CTL1, FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1); 100 101 if (!enable && (pcr->aspm_en & 0x02)) 102 mdelay(10); 103 104 pcr->aspm_enabled = enable; 105 } 106 107 static void rtsx_disable_aspm(struct rtsx_pcr *pcr) 108 { 109 if (pcr->ops->set_aspm) 110 pcr->ops->set_aspm(pcr, false); 111 else 112 rtsx_comm_set_aspm(pcr, false); 113 } 114 115 int rtsx_set_l1off_sub(struct rtsx_pcr *pcr, u8 val) 116 { 117 rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, val); 118 119 return 0; 120 } 121 122 static void rtsx_set_l1off_sub_cfg_d0(struct rtsx_pcr *pcr, int active) 123 { 124 if (pcr->ops->set_l1off_cfg_sub_d0) 125 pcr->ops->set_l1off_cfg_sub_d0(pcr, active); 126 } 127 128 static void rtsx_comm_pm_full_on(struct rtsx_pcr *pcr) 129 { 130 struct rtsx_cr_option *option = &pcr->option; 131 132 rtsx_disable_aspm(pcr); 133 134 /* Fixes DMA transfer timout issue after disabling ASPM on RTS5260 */ 135 msleep(1); 136 137 if (option->ltr_enabled) 138 rtsx_set_ltr_latency(pcr, option->ltr_active_latency); 139 140 if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_EN)) 141 rtsx_set_l1off_sub_cfg_d0(pcr, 1); 142 } 143 144 static void rtsx_pm_full_on(struct rtsx_pcr *pcr) 145 { 146 rtsx_comm_pm_full_on(pcr); 147 } 148 149 void rtsx_pci_start_run(struct rtsx_pcr *pcr) 150 { 151 /* If pci device removed, don't queue idle work any more */ 152 if (pcr->remove_pci) 153 return; 154 155 if (pcr->rtd3_en) 156 if (pcr->is_runtime_suspended) { 157 pm_runtime_get(&(pcr->pci->dev)); 158 pcr->is_runtime_suspended = false; 159 } 160 161 if (pcr->state != PDEV_STAT_RUN) { 162 pcr->state = PDEV_STAT_RUN; 163 if (pcr->ops->enable_auto_blink) 164 pcr->ops->enable_auto_blink(pcr); 165 rtsx_pm_full_on(pcr); 166 } 167 168 mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200)); 169 } 170 EXPORT_SYMBOL_GPL(rtsx_pci_start_run); 171 172 int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data) 173 { 174 int i; 175 u32 val = HAIMR_WRITE_START; 176 177 val |= (u32)(addr & 0x3FFF) << 16; 178 val |= (u32)mask << 8; 179 val |= (u32)data; 180 181 rtsx_pci_writel(pcr, RTSX_HAIMR, val); 182 183 for (i = 0; i < MAX_RW_REG_CNT; i++) { 184 val = rtsx_pci_readl(pcr, RTSX_HAIMR); 185 if ((val & HAIMR_TRANS_END) == 0) { 186 if (data != (u8)val) 187 return -EIO; 188 return 0; 189 } 190 } 191 192 return -ETIMEDOUT; 193 } 194 EXPORT_SYMBOL_GPL(rtsx_pci_write_register); 195 196 int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data) 197 { 198 u32 val = HAIMR_READ_START; 199 int i; 200 201 val |= (u32)(addr & 0x3FFF) << 16; 202 rtsx_pci_writel(pcr, RTSX_HAIMR, val); 203 204 for (i = 0; i < MAX_RW_REG_CNT; i++) { 205 val = rtsx_pci_readl(pcr, RTSX_HAIMR); 206 if ((val & HAIMR_TRANS_END) == 0) 207 break; 208 } 209 210 if (i >= MAX_RW_REG_CNT) 211 return -ETIMEDOUT; 212 213 if (data) 214 *data = (u8)(val & 0xFF); 215 216 return 0; 217 } 218 EXPORT_SYMBOL_GPL(rtsx_pci_read_register); 219 220 int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val) 221 { 222 int err, i, finished = 0; 223 u8 tmp; 224 225 rtsx_pci_write_register(pcr, PHYDATA0, 0xFF, (u8)val); 226 rtsx_pci_write_register(pcr, PHYDATA1, 0xFF, (u8)(val >> 8)); 227 rtsx_pci_write_register(pcr, PHYADDR, 0xFF, addr); 228 rtsx_pci_write_register(pcr, PHYRWCTL, 0xFF, 0x81); 229 230 for (i = 0; i < 100000; i++) { 231 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp); 232 if (err < 0) 233 return err; 234 235 if (!(tmp & 0x80)) { 236 finished = 1; 237 break; 238 } 239 } 240 241 if (!finished) 242 return -ETIMEDOUT; 243 244 return 0; 245 } 246 247 int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val) 248 { 249 if (pcr->ops->write_phy) 250 return pcr->ops->write_phy(pcr, addr, val); 251 252 return __rtsx_pci_write_phy_register(pcr, addr, val); 253 } 254 EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register); 255 256 int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val) 257 { 258 int err, i, finished = 0; 259 u16 data; 260 u8 tmp, val1, val2; 261 262 rtsx_pci_write_register(pcr, PHYADDR, 0xFF, addr); 263 rtsx_pci_write_register(pcr, PHYRWCTL, 0xFF, 0x80); 264 265 for (i = 0; i < 100000; i++) { 266 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp); 267 if (err < 0) 268 return err; 269 270 if (!(tmp & 0x80)) { 271 finished = 1; 272 break; 273 } 274 } 275 276 if (!finished) 277 return -ETIMEDOUT; 278 279 rtsx_pci_read_register(pcr, PHYDATA0, &val1); 280 rtsx_pci_read_register(pcr, PHYDATA1, &val2); 281 data = val1 | (val2 << 8); 282 283 if (val) 284 *val = data; 285 286 return 0; 287 } 288 289 int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val) 290 { 291 if (pcr->ops->read_phy) 292 return pcr->ops->read_phy(pcr, addr, val); 293 294 return __rtsx_pci_read_phy_register(pcr, addr, val); 295 } 296 EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register); 297 298 void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr) 299 { 300 if (pcr->ops->stop_cmd) 301 return pcr->ops->stop_cmd(pcr); 302 303 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD); 304 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA); 305 306 rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80); 307 rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80); 308 } 309 EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd); 310 311 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr, 312 u8 cmd_type, u16 reg_addr, u8 mask, u8 data) 313 { 314 unsigned long flags; 315 u32 val = 0; 316 u32 *ptr = (u32 *)(pcr->host_cmds_ptr); 317 318 val |= (u32)(cmd_type & 0x03) << 30; 319 val |= (u32)(reg_addr & 0x3FFF) << 16; 320 val |= (u32)mask << 8; 321 val |= (u32)data; 322 323 spin_lock_irqsave(&pcr->lock, flags); 324 ptr += pcr->ci; 325 if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) { 326 put_unaligned_le32(val, ptr); 327 ptr++; 328 pcr->ci++; 329 } 330 spin_unlock_irqrestore(&pcr->lock, flags); 331 } 332 EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd); 333 334 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr) 335 { 336 u32 val = 1 << 31; 337 338 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr); 339 340 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF; 341 /* Hardware Auto Response */ 342 val |= 0x40000000; 343 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val); 344 } 345 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait); 346 347 int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout) 348 { 349 struct completion trans_done; 350 u32 val = 1 << 31; 351 long timeleft; 352 unsigned long flags; 353 int err = 0; 354 355 spin_lock_irqsave(&pcr->lock, flags); 356 357 /* set up data structures for the wakeup system */ 358 pcr->done = &trans_done; 359 pcr->trans_result = TRANS_NOT_READY; 360 init_completion(&trans_done); 361 362 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr); 363 364 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF; 365 /* Hardware Auto Response */ 366 val |= 0x40000000; 367 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val); 368 369 spin_unlock_irqrestore(&pcr->lock, flags); 370 371 /* Wait for TRANS_OK_INT */ 372 timeleft = wait_for_completion_interruptible_timeout( 373 &trans_done, msecs_to_jiffies(timeout)); 374 if (timeleft <= 0) { 375 pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__); 376 err = -ETIMEDOUT; 377 goto finish_send_cmd; 378 } 379 380 spin_lock_irqsave(&pcr->lock, flags); 381 if (pcr->trans_result == TRANS_RESULT_FAIL) 382 err = -EINVAL; 383 else if (pcr->trans_result == TRANS_RESULT_OK) 384 err = 0; 385 else if (pcr->trans_result == TRANS_NO_DEVICE) 386 err = -ENODEV; 387 spin_unlock_irqrestore(&pcr->lock, flags); 388 389 finish_send_cmd: 390 spin_lock_irqsave(&pcr->lock, flags); 391 pcr->done = NULL; 392 spin_unlock_irqrestore(&pcr->lock, flags); 393 394 if ((err < 0) && (err != -ENODEV)) 395 rtsx_pci_stop_cmd(pcr); 396 397 if (pcr->finish_me) 398 complete(pcr->finish_me); 399 400 return err; 401 } 402 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd); 403 404 static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr, 405 dma_addr_t addr, unsigned int len, int end) 406 { 407 u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi; 408 u64 val; 409 u8 option = RTSX_SG_VALID | RTSX_SG_TRANS_DATA; 410 411 pcr_dbg(pcr, "DMA addr: 0x%x, Len: 0x%x\n", (unsigned int)addr, len); 412 413 if (end) 414 option |= RTSX_SG_END; 415 416 if ((PCI_PID(pcr) == PID_5261) || (PCI_PID(pcr) == PID_5228)) { 417 if (len > 0xFFFF) 418 val = ((u64)addr << 32) | (((u64)len & 0xFFFF) << 16) 419 | (((u64)len >> 16) << 6) | option; 420 else 421 val = ((u64)addr << 32) | ((u64)len << 16) | option; 422 } else { 423 val = ((u64)addr << 32) | ((u64)len << 12) | option; 424 } 425 put_unaligned_le64(val, ptr); 426 pcr->sgi++; 427 } 428 429 int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist, 430 int num_sg, bool read, int timeout) 431 { 432 int err = 0, count; 433 434 pcr_dbg(pcr, "--> %s: num_sg = %d\n", __func__, num_sg); 435 count = rtsx_pci_dma_map_sg(pcr, sglist, num_sg, read); 436 if (count < 1) 437 return -EINVAL; 438 pcr_dbg(pcr, "DMA mapping count: %d\n", count); 439 440 err = rtsx_pci_dma_transfer(pcr, sglist, count, read, timeout); 441 442 rtsx_pci_dma_unmap_sg(pcr, sglist, num_sg, read); 443 444 return err; 445 } 446 EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data); 447 448 int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist, 449 int num_sg, bool read) 450 { 451 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 452 453 if (pcr->remove_pci) 454 return -EINVAL; 455 456 if ((sglist == NULL) || (num_sg <= 0)) 457 return -EINVAL; 458 459 return dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dir); 460 } 461 EXPORT_SYMBOL_GPL(rtsx_pci_dma_map_sg); 462 463 void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist, 464 int num_sg, bool read) 465 { 466 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 467 468 dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dir); 469 } 470 EXPORT_SYMBOL_GPL(rtsx_pci_dma_unmap_sg); 471 472 int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist, 473 int count, bool read, int timeout) 474 { 475 struct completion trans_done; 476 struct scatterlist *sg; 477 dma_addr_t addr; 478 long timeleft; 479 unsigned long flags; 480 unsigned int len; 481 int i, err = 0; 482 u32 val; 483 u8 dir = read ? DEVICE_TO_HOST : HOST_TO_DEVICE; 484 485 if (pcr->remove_pci) 486 return -ENODEV; 487 488 if ((sglist == NULL) || (count < 1)) 489 return -EINVAL; 490 491 val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE; 492 pcr->sgi = 0; 493 for_each_sg(sglist, sg, count, i) { 494 addr = sg_dma_address(sg); 495 len = sg_dma_len(sg); 496 rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1); 497 } 498 499 spin_lock_irqsave(&pcr->lock, flags); 500 501 pcr->done = &trans_done; 502 pcr->trans_result = TRANS_NOT_READY; 503 init_completion(&trans_done); 504 rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr); 505 rtsx_pci_writel(pcr, RTSX_HDBCTLR, val); 506 507 spin_unlock_irqrestore(&pcr->lock, flags); 508 509 timeleft = wait_for_completion_interruptible_timeout( 510 &trans_done, msecs_to_jiffies(timeout)); 511 if (timeleft <= 0) { 512 pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__); 513 err = -ETIMEDOUT; 514 goto out; 515 } 516 517 spin_lock_irqsave(&pcr->lock, flags); 518 if (pcr->trans_result == TRANS_RESULT_FAIL) { 519 err = -EILSEQ; 520 if (pcr->dma_error_count < RTS_MAX_TIMES_FREQ_REDUCTION) 521 pcr->dma_error_count++; 522 } 523 524 else if (pcr->trans_result == TRANS_NO_DEVICE) 525 err = -ENODEV; 526 spin_unlock_irqrestore(&pcr->lock, flags); 527 528 out: 529 spin_lock_irqsave(&pcr->lock, flags); 530 pcr->done = NULL; 531 spin_unlock_irqrestore(&pcr->lock, flags); 532 533 if ((err < 0) && (err != -ENODEV)) 534 rtsx_pci_stop_cmd(pcr); 535 536 if (pcr->finish_me) 537 complete(pcr->finish_me); 538 539 return err; 540 } 541 EXPORT_SYMBOL_GPL(rtsx_pci_dma_transfer); 542 543 int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len) 544 { 545 int err; 546 int i, j; 547 u16 reg; 548 u8 *ptr; 549 550 if (buf_len > 512) 551 buf_len = 512; 552 553 ptr = buf; 554 reg = PPBUF_BASE2; 555 for (i = 0; i < buf_len / 256; i++) { 556 rtsx_pci_init_cmd(pcr); 557 558 for (j = 0; j < 256; j++) 559 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0); 560 561 err = rtsx_pci_send_cmd(pcr, 250); 562 if (err < 0) 563 return err; 564 565 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256); 566 ptr += 256; 567 } 568 569 if (buf_len % 256) { 570 rtsx_pci_init_cmd(pcr); 571 572 for (j = 0; j < buf_len % 256; j++) 573 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0); 574 575 err = rtsx_pci_send_cmd(pcr, 250); 576 if (err < 0) 577 return err; 578 } 579 580 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256); 581 582 return 0; 583 } 584 EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf); 585 586 int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len) 587 { 588 int err; 589 int i, j; 590 u16 reg; 591 u8 *ptr; 592 593 if (buf_len > 512) 594 buf_len = 512; 595 596 ptr = buf; 597 reg = PPBUF_BASE2; 598 for (i = 0; i < buf_len / 256; i++) { 599 rtsx_pci_init_cmd(pcr); 600 601 for (j = 0; j < 256; j++) { 602 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 603 reg++, 0xFF, *ptr); 604 ptr++; 605 } 606 607 err = rtsx_pci_send_cmd(pcr, 250); 608 if (err < 0) 609 return err; 610 } 611 612 if (buf_len % 256) { 613 rtsx_pci_init_cmd(pcr); 614 615 for (j = 0; j < buf_len % 256; j++) { 616 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 617 reg++, 0xFF, *ptr); 618 ptr++; 619 } 620 621 err = rtsx_pci_send_cmd(pcr, 250); 622 if (err < 0) 623 return err; 624 } 625 626 return 0; 627 } 628 EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf); 629 630 static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl) 631 { 632 rtsx_pci_init_cmd(pcr); 633 634 while (*tbl & 0xFFFF0000) { 635 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 636 (u16)(*tbl >> 16), 0xFF, (u8)(*tbl)); 637 tbl++; 638 } 639 640 return rtsx_pci_send_cmd(pcr, 100); 641 } 642 643 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card) 644 { 645 const u32 *tbl; 646 647 if (card == RTSX_SD_CARD) 648 tbl = pcr->sd_pull_ctl_enable_tbl; 649 else if (card == RTSX_MS_CARD) 650 tbl = pcr->ms_pull_ctl_enable_tbl; 651 else 652 return -EINVAL; 653 654 return rtsx_pci_set_pull_ctl(pcr, tbl); 655 } 656 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable); 657 658 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card) 659 { 660 const u32 *tbl; 661 662 if (card == RTSX_SD_CARD) 663 tbl = pcr->sd_pull_ctl_disable_tbl; 664 else if (card == RTSX_MS_CARD) 665 tbl = pcr->ms_pull_ctl_disable_tbl; 666 else 667 return -EINVAL; 668 669 return rtsx_pci_set_pull_ctl(pcr, tbl); 670 } 671 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable); 672 673 static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr) 674 { 675 struct rtsx_hw_param *hw_param = &pcr->hw_param; 676 677 pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN 678 | hw_param->interrupt_en; 679 680 if (pcr->num_slots > 1) 681 pcr->bier |= MS_INT_EN; 682 683 /* Enable Bus Interrupt */ 684 rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier); 685 686 pcr_dbg(pcr, "RTSX_BIER: 0x%08x\n", pcr->bier); 687 } 688 689 static inline u8 double_ssc_depth(u8 depth) 690 { 691 return ((depth > 1) ? (depth - 1) : depth); 692 } 693 694 static u8 revise_ssc_depth(u8 ssc_depth, u8 div) 695 { 696 if (div > CLK_DIV_1) { 697 if (ssc_depth > (div - 1)) 698 ssc_depth -= (div - 1); 699 else 700 ssc_depth = SSC_DEPTH_4M; 701 } 702 703 return ssc_depth; 704 } 705 706 int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, 707 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk) 708 { 709 int err, clk; 710 u8 n, clk_divider, mcu_cnt, div; 711 static const u8 depth[] = { 712 [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M, 713 [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M, 714 [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M, 715 [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K, 716 [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K, 717 }; 718 719 if (PCI_PID(pcr) == PID_5261) 720 return rts5261_pci_switch_clock(pcr, card_clock, 721 ssc_depth, initial_mode, double_clk, vpclk); 722 if (PCI_PID(pcr) == PID_5228) 723 return rts5228_pci_switch_clock(pcr, card_clock, 724 ssc_depth, initial_mode, double_clk, vpclk); 725 726 if (initial_mode) { 727 /* We use 250k(around) here, in initial stage */ 728 clk_divider = SD_CLK_DIVIDE_128; 729 card_clock = 30000000; 730 } else { 731 clk_divider = SD_CLK_DIVIDE_0; 732 } 733 err = rtsx_pci_write_register(pcr, SD_CFG1, 734 SD_CLK_DIVIDE_MASK, clk_divider); 735 if (err < 0) 736 return err; 737 738 /* Reduce card clock by 20MHz each time a DMA transfer error occurs */ 739 if (card_clock == UHS_SDR104_MAX_DTR && 740 pcr->dma_error_count && 741 PCI_PID(pcr) == RTS5227_DEVICE_ID) 742 card_clock = UHS_SDR104_MAX_DTR - 743 (pcr->dma_error_count * 20000000); 744 745 card_clock /= 1000000; 746 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock); 747 748 clk = card_clock; 749 if (!initial_mode && double_clk) 750 clk = card_clock * 2; 751 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n", 752 clk, pcr->cur_clock); 753 754 if (clk == pcr->cur_clock) 755 return 0; 756 757 if (pcr->ops->conv_clk_and_div_n) 758 n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N); 759 else 760 n = (u8)(clk - 2); 761 if ((clk <= 2) || (n > MAX_DIV_N_PCR)) 762 return -EINVAL; 763 764 mcu_cnt = (u8)(125/clk + 3); 765 if (mcu_cnt > 15) 766 mcu_cnt = 15; 767 768 /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */ 769 div = CLK_DIV_1; 770 while ((n < MIN_DIV_N_PCR) && (div < CLK_DIV_8)) { 771 if (pcr->ops->conv_clk_and_div_n) { 772 int dbl_clk = pcr->ops->conv_clk_and_div_n(n, 773 DIV_N_TO_CLK) * 2; 774 n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk, 775 CLK_TO_DIV_N); 776 } else { 777 n = (n + 2) * 2 - 2; 778 } 779 div++; 780 } 781 pcr_dbg(pcr, "n = %d, div = %d\n", n, div); 782 783 ssc_depth = depth[ssc_depth]; 784 if (double_clk) 785 ssc_depth = double_ssc_depth(ssc_depth); 786 787 ssc_depth = revise_ssc_depth(ssc_depth, div); 788 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth); 789 790 rtsx_pci_init_cmd(pcr); 791 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 792 CLK_LOW_FREQ, CLK_LOW_FREQ); 793 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 794 0xFF, (div << 4) | mcu_cnt); 795 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); 796 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 797 SSC_DEPTH_MASK, ssc_depth); 798 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n); 799 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB); 800 if (vpclk) { 801 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, 802 PHASE_NOT_RESET, 0); 803 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, 804 PHASE_NOT_RESET, PHASE_NOT_RESET); 805 } 806 807 err = rtsx_pci_send_cmd(pcr, 2000); 808 if (err < 0) 809 return err; 810 811 /* Wait SSC clock stable */ 812 udelay(SSC_CLOCK_STABLE_WAIT); 813 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); 814 if (err < 0) 815 return err; 816 817 pcr->cur_clock = clk; 818 return 0; 819 } 820 EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock); 821 822 int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card) 823 { 824 if (pcr->ops->card_power_on) 825 return pcr->ops->card_power_on(pcr, card); 826 827 return 0; 828 } 829 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on); 830 831 int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card) 832 { 833 if (pcr->ops->card_power_off) 834 return pcr->ops->card_power_off(pcr, card); 835 836 return 0; 837 } 838 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off); 839 840 int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card) 841 { 842 static const unsigned int cd_mask[] = { 843 [RTSX_SD_CARD] = SD_EXIST, 844 [RTSX_MS_CARD] = MS_EXIST 845 }; 846 847 if (!(pcr->flags & PCR_MS_PMOS)) { 848 /* When using single PMOS, accessing card is not permitted 849 * if the existing card is not the designated one. 850 */ 851 if (pcr->card_exist & (~cd_mask[card])) 852 return -EIO; 853 } 854 855 return 0; 856 } 857 EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check); 858 859 int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) 860 { 861 if (pcr->ops->switch_output_voltage) 862 return pcr->ops->switch_output_voltage(pcr, voltage); 863 864 return 0; 865 } 866 EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage); 867 868 unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr) 869 { 870 unsigned int val; 871 872 val = rtsx_pci_readl(pcr, RTSX_BIPR); 873 if (pcr->ops->cd_deglitch) 874 val = pcr->ops->cd_deglitch(pcr); 875 876 return val; 877 } 878 EXPORT_SYMBOL_GPL(rtsx_pci_card_exist); 879 880 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr) 881 { 882 struct completion finish; 883 884 pcr->finish_me = &finish; 885 init_completion(&finish); 886 887 if (pcr->done) 888 complete(pcr->done); 889 890 if (!pcr->remove_pci) 891 rtsx_pci_stop_cmd(pcr); 892 893 wait_for_completion_interruptible_timeout(&finish, 894 msecs_to_jiffies(2)); 895 pcr->finish_me = NULL; 896 } 897 EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer); 898 899 static void rtsx_pci_card_detect(struct work_struct *work) 900 { 901 struct delayed_work *dwork; 902 struct rtsx_pcr *pcr; 903 unsigned long flags; 904 unsigned int card_detect = 0, card_inserted, card_removed; 905 u32 irq_status; 906 907 dwork = to_delayed_work(work); 908 pcr = container_of(dwork, struct rtsx_pcr, carddet_work); 909 910 pcr_dbg(pcr, "--> %s\n", __func__); 911 912 mutex_lock(&pcr->pcr_mutex); 913 spin_lock_irqsave(&pcr->lock, flags); 914 915 irq_status = rtsx_pci_readl(pcr, RTSX_BIPR); 916 pcr_dbg(pcr, "irq_status: 0x%08x\n", irq_status); 917 918 irq_status &= CARD_EXIST; 919 card_inserted = pcr->card_inserted & irq_status; 920 card_removed = pcr->card_removed; 921 pcr->card_inserted = 0; 922 pcr->card_removed = 0; 923 924 spin_unlock_irqrestore(&pcr->lock, flags); 925 926 if (card_inserted || card_removed) { 927 pcr_dbg(pcr, "card_inserted: 0x%x, card_removed: 0x%x\n", 928 card_inserted, card_removed); 929 930 if (pcr->ops->cd_deglitch) 931 card_inserted = pcr->ops->cd_deglitch(pcr); 932 933 card_detect = card_inserted | card_removed; 934 935 pcr->card_exist |= card_inserted; 936 pcr->card_exist &= ~card_removed; 937 } 938 939 mutex_unlock(&pcr->pcr_mutex); 940 941 if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event) 942 pcr->slots[RTSX_SD_CARD].card_event( 943 pcr->slots[RTSX_SD_CARD].p_dev); 944 if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event) 945 pcr->slots[RTSX_MS_CARD].card_event( 946 pcr->slots[RTSX_MS_CARD].p_dev); 947 } 948 949 static void rtsx_pci_process_ocp(struct rtsx_pcr *pcr) 950 { 951 if (pcr->ops->process_ocp) { 952 pcr->ops->process_ocp(pcr); 953 } else { 954 if (!pcr->option.ocp_en) 955 return; 956 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat); 957 if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) { 958 rtsx_pci_card_power_off(pcr, RTSX_SD_CARD); 959 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0); 960 rtsx_pci_clear_ocpstat(pcr); 961 pcr->ocp_stat = 0; 962 } 963 } 964 } 965 966 static int rtsx_pci_process_ocp_interrupt(struct rtsx_pcr *pcr) 967 { 968 if (pcr->option.ocp_en) 969 rtsx_pci_process_ocp(pcr); 970 971 return 0; 972 } 973 974 static irqreturn_t rtsx_pci_isr(int irq, void *dev_id) 975 { 976 struct rtsx_pcr *pcr = dev_id; 977 u32 int_reg; 978 979 if (!pcr) 980 return IRQ_NONE; 981 982 spin_lock(&pcr->lock); 983 984 int_reg = rtsx_pci_readl(pcr, RTSX_BIPR); 985 /* Clear interrupt flag */ 986 rtsx_pci_writel(pcr, RTSX_BIPR, int_reg); 987 if ((int_reg & pcr->bier) == 0) { 988 spin_unlock(&pcr->lock); 989 return IRQ_NONE; 990 } 991 if (int_reg == 0xFFFFFFFF) { 992 spin_unlock(&pcr->lock); 993 return IRQ_HANDLED; 994 } 995 996 int_reg &= (pcr->bier | 0x7FFFFF); 997 998 if (int_reg & SD_OC_INT) 999 rtsx_pci_process_ocp_interrupt(pcr); 1000 1001 if (int_reg & SD_INT) { 1002 if (int_reg & SD_EXIST) { 1003 pcr->card_inserted |= SD_EXIST; 1004 } else { 1005 pcr->card_removed |= SD_EXIST; 1006 pcr->card_inserted &= ~SD_EXIST; 1007 } 1008 pcr->dma_error_count = 0; 1009 } 1010 1011 if (int_reg & MS_INT) { 1012 if (int_reg & MS_EXIST) { 1013 pcr->card_inserted |= MS_EXIST; 1014 } else { 1015 pcr->card_removed |= MS_EXIST; 1016 pcr->card_inserted &= ~MS_EXIST; 1017 } 1018 } 1019 1020 if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) { 1021 if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) { 1022 pcr->trans_result = TRANS_RESULT_FAIL; 1023 if (pcr->done) 1024 complete(pcr->done); 1025 } else if (int_reg & TRANS_OK_INT) { 1026 pcr->trans_result = TRANS_RESULT_OK; 1027 if (pcr->done) 1028 complete(pcr->done); 1029 } 1030 } 1031 1032 if ((pcr->card_inserted || pcr->card_removed) && !(int_reg & SD_OC_INT)) 1033 schedule_delayed_work(&pcr->carddet_work, 1034 msecs_to_jiffies(200)); 1035 1036 spin_unlock(&pcr->lock); 1037 return IRQ_HANDLED; 1038 } 1039 1040 static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr) 1041 { 1042 pcr_dbg(pcr, "%s: pcr->msi_en = %d, pci->irq = %d\n", 1043 __func__, pcr->msi_en, pcr->pci->irq); 1044 1045 if (request_irq(pcr->pci->irq, rtsx_pci_isr, 1046 pcr->msi_en ? 0 : IRQF_SHARED, 1047 DRV_NAME_RTSX_PCI, pcr)) { 1048 dev_err(&(pcr->pci->dev), 1049 "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n", 1050 pcr->pci->irq); 1051 return -1; 1052 } 1053 1054 pcr->irq = pcr->pci->irq; 1055 pci_intx(pcr->pci, !pcr->msi_en); 1056 1057 return 0; 1058 } 1059 1060 static void rtsx_enable_aspm(struct rtsx_pcr *pcr) 1061 { 1062 if (pcr->ops->set_aspm) 1063 pcr->ops->set_aspm(pcr, true); 1064 else 1065 rtsx_comm_set_aspm(pcr, true); 1066 } 1067 1068 static void rtsx_comm_pm_power_saving(struct rtsx_pcr *pcr) 1069 { 1070 struct rtsx_cr_option *option = &pcr->option; 1071 1072 if (option->ltr_enabled) { 1073 u32 latency = option->ltr_l1off_latency; 1074 1075 if (rtsx_check_dev_flag(pcr, L1_SNOOZE_TEST_EN)) 1076 mdelay(option->l1_snooze_delay); 1077 1078 rtsx_set_ltr_latency(pcr, latency); 1079 } 1080 1081 if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_EN)) 1082 rtsx_set_l1off_sub_cfg_d0(pcr, 0); 1083 1084 rtsx_enable_aspm(pcr); 1085 } 1086 1087 static void rtsx_pm_power_saving(struct rtsx_pcr *pcr) 1088 { 1089 rtsx_comm_pm_power_saving(pcr); 1090 } 1091 1092 static void rtsx_pci_rtd3_work(struct work_struct *work) 1093 { 1094 struct delayed_work *dwork = to_delayed_work(work); 1095 struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, rtd3_work); 1096 1097 pcr_dbg(pcr, "--> %s\n", __func__); 1098 if (!pcr->is_runtime_suspended) 1099 pm_runtime_put(&(pcr->pci->dev)); 1100 } 1101 1102 static void rtsx_pci_idle_work(struct work_struct *work) 1103 { 1104 struct delayed_work *dwork = to_delayed_work(work); 1105 struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work); 1106 1107 pcr_dbg(pcr, "--> %s\n", __func__); 1108 1109 mutex_lock(&pcr->pcr_mutex); 1110 1111 pcr->state = PDEV_STAT_IDLE; 1112 1113 if (pcr->ops->disable_auto_blink) 1114 pcr->ops->disable_auto_blink(pcr); 1115 if (pcr->ops->turn_off_led) 1116 pcr->ops->turn_off_led(pcr); 1117 1118 rtsx_pm_power_saving(pcr); 1119 1120 mutex_unlock(&pcr->pcr_mutex); 1121 1122 if (pcr->rtd3_en) 1123 mod_delayed_work(system_wq, &pcr->rtd3_work, msecs_to_jiffies(10000)); 1124 } 1125 1126 static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state) 1127 { 1128 /* Set relink_time to 0 */ 1129 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0); 1130 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0); 1131 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 1132 RELINK_TIME_MASK, 0); 1133 1134 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 1135 D3_DELINK_MODE_EN, D3_DELINK_MODE_EN); 1136 1137 rtsx_pci_write_register(pcr, FPDCTL, ALL_POWER_DOWN, ALL_POWER_DOWN); 1138 } 1139 1140 static void __maybe_unused rtsx_pci_power_off(struct rtsx_pcr *pcr, u8 pm_state) 1141 { 1142 if (pcr->ops->turn_off_led) 1143 pcr->ops->turn_off_led(pcr); 1144 1145 rtsx_pci_writel(pcr, RTSX_BIER, 0); 1146 pcr->bier = 0; 1147 1148 rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08); 1149 rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, pm_state); 1150 1151 if (pcr->ops->force_power_down) 1152 pcr->ops->force_power_down(pcr, pm_state); 1153 else 1154 rtsx_base_force_power_down(pcr, pm_state); 1155 } 1156 1157 void rtsx_pci_enable_ocp(struct rtsx_pcr *pcr) 1158 { 1159 u8 val = SD_OCP_INT_EN | SD_DETECT_EN; 1160 1161 if (pcr->ops->enable_ocp) { 1162 pcr->ops->enable_ocp(pcr); 1163 } else { 1164 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0); 1165 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val); 1166 } 1167 1168 } 1169 1170 void rtsx_pci_disable_ocp(struct rtsx_pcr *pcr) 1171 { 1172 u8 mask = SD_OCP_INT_EN | SD_DETECT_EN; 1173 1174 if (pcr->ops->disable_ocp) { 1175 pcr->ops->disable_ocp(pcr); 1176 } else { 1177 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); 1178 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 1179 OC_POWER_DOWN); 1180 } 1181 } 1182 1183 void rtsx_pci_init_ocp(struct rtsx_pcr *pcr) 1184 { 1185 if (pcr->ops->init_ocp) { 1186 pcr->ops->init_ocp(pcr); 1187 } else { 1188 struct rtsx_cr_option *option = &(pcr->option); 1189 1190 if (option->ocp_en) { 1191 u8 val = option->sd_800mA_ocp_thd; 1192 1193 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0); 1194 rtsx_pci_write_register(pcr, REG_OCPPARA1, 1195 SD_OCP_TIME_MASK, SD_OCP_TIME_800); 1196 rtsx_pci_write_register(pcr, REG_OCPPARA2, 1197 SD_OCP_THD_MASK, val); 1198 rtsx_pci_write_register(pcr, REG_OCPGLITCH, 1199 SD_OCP_GLITCH_MASK, pcr->hw_param.ocp_glitch); 1200 rtsx_pci_enable_ocp(pcr); 1201 } 1202 } 1203 } 1204 1205 int rtsx_pci_get_ocpstat(struct rtsx_pcr *pcr, u8 *val) 1206 { 1207 if (pcr->ops->get_ocpstat) 1208 return pcr->ops->get_ocpstat(pcr, val); 1209 else 1210 return rtsx_pci_read_register(pcr, REG_OCPSTAT, val); 1211 } 1212 1213 void rtsx_pci_clear_ocpstat(struct rtsx_pcr *pcr) 1214 { 1215 if (pcr->ops->clear_ocpstat) { 1216 pcr->ops->clear_ocpstat(pcr); 1217 } else { 1218 u8 mask = SD_OCP_INT_CLR | SD_OC_CLR; 1219 u8 val = SD_OCP_INT_CLR | SD_OC_CLR; 1220 1221 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val); 1222 udelay(100); 1223 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); 1224 } 1225 } 1226 1227 void rtsx_pci_enable_oobs_polling(struct rtsx_pcr *pcr) 1228 { 1229 u16 val; 1230 1231 if ((PCI_PID(pcr) != PID_525A) && (PCI_PID(pcr) != PID_5260)) { 1232 rtsx_pci_read_phy_register(pcr, 0x01, &val); 1233 val |= 1<<9; 1234 rtsx_pci_write_phy_register(pcr, 0x01, val); 1235 } 1236 rtsx_pci_write_register(pcr, REG_CFG_OOBS_OFF_TIMER, 0xFF, 0x32); 1237 rtsx_pci_write_register(pcr, REG_CFG_OOBS_ON_TIMER, 0xFF, 0x05); 1238 rtsx_pci_write_register(pcr, REG_CFG_VCM_ON_TIMER, 0xFF, 0x83); 1239 rtsx_pci_write_register(pcr, REG_CFG_OOBS_POLLING, 0xFF, 0xDE); 1240 1241 } 1242 1243 void rtsx_pci_disable_oobs_polling(struct rtsx_pcr *pcr) 1244 { 1245 u16 val; 1246 1247 if ((PCI_PID(pcr) != PID_525A) && (PCI_PID(pcr) != PID_5260)) { 1248 rtsx_pci_read_phy_register(pcr, 0x01, &val); 1249 val &= ~(1<<9); 1250 rtsx_pci_write_phy_register(pcr, 0x01, val); 1251 } 1252 rtsx_pci_write_register(pcr, REG_CFG_VCM_ON_TIMER, 0xFF, 0x03); 1253 rtsx_pci_write_register(pcr, REG_CFG_OOBS_POLLING, 0xFF, 0x00); 1254 1255 } 1256 1257 int rtsx_sd_power_off_card3v3(struct rtsx_pcr *pcr) 1258 { 1259 rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN | 1260 MS_CLK_EN | SD40_CLK_EN, 0); 1261 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0); 1262 rtsx_pci_card_power_off(pcr, RTSX_SD_CARD); 1263 1264 msleep(50); 1265 1266 rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD); 1267 1268 return 0; 1269 } 1270 1271 int rtsx_ms_power_off_card3v3(struct rtsx_pcr *pcr) 1272 { 1273 rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN | 1274 MS_CLK_EN | SD40_CLK_EN, 0); 1275 1276 rtsx_pci_card_pull_ctl_disable(pcr, RTSX_MS_CARD); 1277 1278 rtsx_pci_write_register(pcr, CARD_OE, MS_OUTPUT_EN, 0); 1279 rtsx_pci_card_power_off(pcr, RTSX_MS_CARD); 1280 1281 return 0; 1282 } 1283 1284 static int rtsx_pci_init_hw(struct rtsx_pcr *pcr) 1285 { 1286 struct pci_dev *pdev = pcr->pci; 1287 int err; 1288 1289 if (PCI_PID(pcr) == PID_5228) 1290 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG1, RTS5228_LDO1_SR_TIME_MASK, 1291 RTS5228_LDO1_SR_0_5); 1292 1293 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr); 1294 1295 rtsx_pci_enable_bus_int(pcr); 1296 1297 /* Power on SSC */ 1298 if (PCI_PID(pcr) == PID_5261) { 1299 /* Gating real mcu clock */ 1300 err = rtsx_pci_write_register(pcr, RTS5261_FW_CFG1, 1301 RTS5261_MCU_CLOCK_GATING, 0); 1302 err = rtsx_pci_write_register(pcr, RTS5261_REG_FPDCTL, 1303 SSC_POWER_DOWN, 0); 1304 } else { 1305 err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0); 1306 } 1307 if (err < 0) 1308 return err; 1309 1310 /* Wait SSC power stable */ 1311 udelay(200); 1312 1313 rtsx_disable_aspm(pcr); 1314 if (pcr->ops->optimize_phy) { 1315 err = pcr->ops->optimize_phy(pcr); 1316 if (err < 0) 1317 return err; 1318 } 1319 1320 rtsx_pci_init_cmd(pcr); 1321 1322 /* Set mcu_cnt to 7 to ensure data can be sampled properly */ 1323 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07); 1324 1325 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00); 1326 /* Disable card clock */ 1327 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0); 1328 /* Reset delink mode */ 1329 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0); 1330 /* Card driving select */ 1331 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL, 1332 0xFF, pcr->card_drive_sel); 1333 /* Enable SSC Clock */ 1334 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, 1335 0xFF, SSC_8X_EN | SSC_SEL_4M); 1336 if (PCI_PID(pcr) == PID_5261) 1337 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 1338 RTS5261_SSC_DEPTH_2M); 1339 else if (PCI_PID(pcr) == PID_5228) 1340 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 1341 RTS5228_SSC_DEPTH_2M); 1342 else 1343 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12); 1344 1345 /* Disable cd_pwr_save */ 1346 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10); 1347 /* Clear Link Ready Interrupt */ 1348 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, 1349 LINK_RDY_INT, LINK_RDY_INT); 1350 /* Enlarge the estimation window of PERST# glitch 1351 * to reduce the chance of invalid card interrupt 1352 */ 1353 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80); 1354 /* Update RC oscillator to 400k 1355 * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1 1356 * 1: 2M 0: 400k 1357 */ 1358 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00); 1359 /* Set interrupt write clear 1360 * bit 1: U_elbi_if_rd_clr_en 1361 * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear 1362 * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear 1363 */ 1364 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0); 1365 1366 err = rtsx_pci_send_cmd(pcr, 100); 1367 if (err < 0) 1368 return err; 1369 1370 switch (PCI_PID(pcr)) { 1371 case PID_5250: 1372 case PID_524A: 1373 case PID_525A: 1374 case PID_5260: 1375 case PID_5261: 1376 case PID_5228: 1377 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 1, 1); 1378 break; 1379 default: 1380 break; 1381 } 1382 1383 /*init ocp*/ 1384 rtsx_pci_init_ocp(pcr); 1385 1386 /* Enable clk_request_n to enable clock power management */ 1387 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, 1388 0, PCI_EXP_LNKCTL_CLKREQ_EN); 1389 /* Enter L1 when host tx idle */ 1390 pci_write_config_byte(pdev, 0x70F, 0x5B); 1391 1392 if (pcr->ops->extra_init_hw) { 1393 err = pcr->ops->extra_init_hw(pcr); 1394 if (err < 0) 1395 return err; 1396 } 1397 1398 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0x30, 0x30); 1399 1400 /* No CD interrupt if probing driver with card inserted. 1401 * So we need to initialize pcr->card_exist here. 1402 */ 1403 if (pcr->ops->cd_deglitch) 1404 pcr->card_exist = pcr->ops->cd_deglitch(pcr); 1405 else 1406 pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST; 1407 1408 return 0; 1409 } 1410 1411 static int rtsx_pci_init_chip(struct rtsx_pcr *pcr) 1412 { 1413 int err; 1414 1415 spin_lock_init(&pcr->lock); 1416 mutex_init(&pcr->pcr_mutex); 1417 1418 switch (PCI_PID(pcr)) { 1419 default: 1420 case 0x5209: 1421 rts5209_init_params(pcr); 1422 break; 1423 1424 case 0x5229: 1425 rts5229_init_params(pcr); 1426 break; 1427 1428 case 0x5289: 1429 rtl8411_init_params(pcr); 1430 break; 1431 1432 case 0x5227: 1433 rts5227_init_params(pcr); 1434 break; 1435 1436 case 0x522A: 1437 rts522a_init_params(pcr); 1438 break; 1439 1440 case 0x5249: 1441 rts5249_init_params(pcr); 1442 break; 1443 1444 case 0x524A: 1445 rts524a_init_params(pcr); 1446 break; 1447 1448 case 0x525A: 1449 rts525a_init_params(pcr); 1450 break; 1451 1452 case 0x5287: 1453 rtl8411b_init_params(pcr); 1454 break; 1455 1456 case 0x5286: 1457 rtl8402_init_params(pcr); 1458 break; 1459 1460 case 0x5260: 1461 rts5260_init_params(pcr); 1462 break; 1463 1464 case 0x5261: 1465 rts5261_init_params(pcr); 1466 break; 1467 1468 case 0x5228: 1469 rts5228_init_params(pcr); 1470 break; 1471 } 1472 1473 pcr_dbg(pcr, "PID: 0x%04x, IC version: 0x%02x\n", 1474 PCI_PID(pcr), pcr->ic_version); 1475 1476 pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot), 1477 GFP_KERNEL); 1478 if (!pcr->slots) 1479 return -ENOMEM; 1480 1481 if (pcr->ops->fetch_vendor_settings) 1482 pcr->ops->fetch_vendor_settings(pcr); 1483 1484 pcr_dbg(pcr, "pcr->aspm_en = 0x%x\n", pcr->aspm_en); 1485 pcr_dbg(pcr, "pcr->sd30_drive_sel_1v8 = 0x%x\n", 1486 pcr->sd30_drive_sel_1v8); 1487 pcr_dbg(pcr, "pcr->sd30_drive_sel_3v3 = 0x%x\n", 1488 pcr->sd30_drive_sel_3v3); 1489 pcr_dbg(pcr, "pcr->card_drive_sel = 0x%x\n", 1490 pcr->card_drive_sel); 1491 pcr_dbg(pcr, "pcr->flags = 0x%x\n", pcr->flags); 1492 1493 pcr->state = PDEV_STAT_IDLE; 1494 err = rtsx_pci_init_hw(pcr); 1495 if (err < 0) { 1496 kfree(pcr->slots); 1497 return err; 1498 } 1499 1500 return 0; 1501 } 1502 1503 static int rtsx_pci_probe(struct pci_dev *pcidev, 1504 const struct pci_device_id *id) 1505 { 1506 struct rtsx_pcr *pcr; 1507 struct pcr_handle *handle; 1508 u32 base, len; 1509 int ret, i, bar = 0; 1510 1511 dev_dbg(&(pcidev->dev), 1512 ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n", 1513 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device, 1514 (int)pcidev->revision); 1515 1516 ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32)); 1517 if (ret < 0) 1518 return ret; 1519 1520 ret = pci_enable_device(pcidev); 1521 if (ret) 1522 return ret; 1523 1524 ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI); 1525 if (ret) 1526 goto disable; 1527 1528 pcr = kzalloc(sizeof(*pcr), GFP_KERNEL); 1529 if (!pcr) { 1530 ret = -ENOMEM; 1531 goto release_pci; 1532 } 1533 1534 handle = kzalloc(sizeof(*handle), GFP_KERNEL); 1535 if (!handle) { 1536 ret = -ENOMEM; 1537 goto free_pcr; 1538 } 1539 handle->pcr = pcr; 1540 1541 idr_preload(GFP_KERNEL); 1542 spin_lock(&rtsx_pci_lock); 1543 ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT); 1544 if (ret >= 0) 1545 pcr->id = ret; 1546 spin_unlock(&rtsx_pci_lock); 1547 idr_preload_end(); 1548 if (ret < 0) 1549 goto free_handle; 1550 1551 pcr->pci = pcidev; 1552 dev_set_drvdata(&pcidev->dev, handle); 1553 1554 if (CHK_PCI_PID(pcr, 0x525A)) 1555 bar = 1; 1556 len = pci_resource_len(pcidev, bar); 1557 base = pci_resource_start(pcidev, bar); 1558 pcr->remap_addr = ioremap(base, len); 1559 if (!pcr->remap_addr) { 1560 ret = -ENOMEM; 1561 goto free_handle; 1562 } 1563 1564 pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev), 1565 RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr), 1566 GFP_KERNEL); 1567 if (pcr->rtsx_resv_buf == NULL) { 1568 ret = -ENXIO; 1569 goto unmap; 1570 } 1571 pcr->host_cmds_ptr = pcr->rtsx_resv_buf; 1572 pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr; 1573 pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN; 1574 pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN; 1575 1576 pcr->card_inserted = 0; 1577 pcr->card_removed = 0; 1578 INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect); 1579 INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work); 1580 1581 pcr->msi_en = msi_en; 1582 if (pcr->msi_en) { 1583 ret = pci_enable_msi(pcidev); 1584 if (ret) 1585 pcr->msi_en = false; 1586 } 1587 1588 ret = rtsx_pci_acquire_irq(pcr); 1589 if (ret < 0) 1590 goto disable_msi; 1591 1592 pci_set_master(pcidev); 1593 synchronize_irq(pcr->irq); 1594 1595 ret = rtsx_pci_init_chip(pcr); 1596 if (ret < 0) 1597 goto disable_irq; 1598 1599 for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) { 1600 rtsx_pcr_cells[i].platform_data = handle; 1601 rtsx_pcr_cells[i].pdata_size = sizeof(*handle); 1602 } 1603 1604 if (pcr->rtd3_en) { 1605 INIT_DELAYED_WORK(&pcr->rtd3_work, rtsx_pci_rtd3_work); 1606 pm_runtime_allow(&pcidev->dev); 1607 pm_runtime_enable(&pcidev->dev); 1608 pcr->is_runtime_suspended = false; 1609 } 1610 1611 1612 ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells, 1613 ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL); 1614 if (ret < 0) 1615 goto free_slots; 1616 1617 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200)); 1618 1619 return 0; 1620 1621 free_slots: 1622 kfree(pcr->slots); 1623 disable_irq: 1624 free_irq(pcr->irq, (void *)pcr); 1625 disable_msi: 1626 if (pcr->msi_en) 1627 pci_disable_msi(pcr->pci); 1628 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN, 1629 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr); 1630 unmap: 1631 iounmap(pcr->remap_addr); 1632 free_handle: 1633 kfree(handle); 1634 free_pcr: 1635 kfree(pcr); 1636 release_pci: 1637 pci_release_regions(pcidev); 1638 disable: 1639 pci_disable_device(pcidev); 1640 1641 return ret; 1642 } 1643 1644 static void rtsx_pci_remove(struct pci_dev *pcidev) 1645 { 1646 struct pcr_handle *handle = pci_get_drvdata(pcidev); 1647 struct rtsx_pcr *pcr = handle->pcr; 1648 1649 if (pcr->rtd3_en) 1650 pm_runtime_get_noresume(&pcr->pci->dev); 1651 1652 pcr->remove_pci = true; 1653 1654 /* Disable interrupts at the pcr level */ 1655 spin_lock_irq(&pcr->lock); 1656 rtsx_pci_writel(pcr, RTSX_BIER, 0); 1657 pcr->bier = 0; 1658 spin_unlock_irq(&pcr->lock); 1659 1660 cancel_delayed_work_sync(&pcr->carddet_work); 1661 cancel_delayed_work_sync(&pcr->idle_work); 1662 if (pcr->rtd3_en) 1663 cancel_delayed_work_sync(&pcr->rtd3_work); 1664 1665 mfd_remove_devices(&pcidev->dev); 1666 1667 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN, 1668 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr); 1669 free_irq(pcr->irq, (void *)pcr); 1670 if (pcr->msi_en) 1671 pci_disable_msi(pcr->pci); 1672 iounmap(pcr->remap_addr); 1673 1674 pci_release_regions(pcidev); 1675 pci_disable_device(pcidev); 1676 1677 spin_lock(&rtsx_pci_lock); 1678 idr_remove(&rtsx_pci_idr, pcr->id); 1679 spin_unlock(&rtsx_pci_lock); 1680 1681 if (pcr->rtd3_en) { 1682 pm_runtime_disable(&pcr->pci->dev); 1683 pm_runtime_put_noidle(&pcr->pci->dev); 1684 } 1685 1686 kfree(pcr->slots); 1687 kfree(pcr); 1688 kfree(handle); 1689 1690 dev_dbg(&(pcidev->dev), 1691 ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n", 1692 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device); 1693 } 1694 1695 static int __maybe_unused rtsx_pci_suspend(struct device *dev_d) 1696 { 1697 struct pci_dev *pcidev = to_pci_dev(dev_d); 1698 struct pcr_handle *handle; 1699 struct rtsx_pcr *pcr; 1700 1701 dev_dbg(&(pcidev->dev), "--> %s\n", __func__); 1702 1703 handle = pci_get_drvdata(pcidev); 1704 pcr = handle->pcr; 1705 1706 cancel_delayed_work(&pcr->carddet_work); 1707 cancel_delayed_work(&pcr->idle_work); 1708 1709 mutex_lock(&pcr->pcr_mutex); 1710 1711 rtsx_pci_power_off(pcr, HOST_ENTER_S3); 1712 1713 device_wakeup_disable(dev_d); 1714 1715 mutex_unlock(&pcr->pcr_mutex); 1716 return 0; 1717 } 1718 1719 static int __maybe_unused rtsx_pci_resume(struct device *dev_d) 1720 { 1721 struct pci_dev *pcidev = to_pci_dev(dev_d); 1722 struct pcr_handle *handle; 1723 struct rtsx_pcr *pcr; 1724 int ret = 0; 1725 1726 dev_dbg(&(pcidev->dev), "--> %s\n", __func__); 1727 1728 handle = pci_get_drvdata(pcidev); 1729 pcr = handle->pcr; 1730 1731 mutex_lock(&pcr->pcr_mutex); 1732 1733 ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00); 1734 if (ret) 1735 goto out; 1736 1737 ret = rtsx_pci_init_hw(pcr); 1738 if (ret) 1739 goto out; 1740 1741 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200)); 1742 1743 out: 1744 mutex_unlock(&pcr->pcr_mutex); 1745 return ret; 1746 } 1747 1748 #ifdef CONFIG_PM 1749 1750 static void rtsx_pci_shutdown(struct pci_dev *pcidev) 1751 { 1752 struct pcr_handle *handle; 1753 struct rtsx_pcr *pcr; 1754 1755 dev_dbg(&(pcidev->dev), "--> %s\n", __func__); 1756 1757 handle = pci_get_drvdata(pcidev); 1758 pcr = handle->pcr; 1759 rtsx_pci_power_off(pcr, HOST_ENTER_S1); 1760 1761 pci_disable_device(pcidev); 1762 free_irq(pcr->irq, (void *)pcr); 1763 if (pcr->msi_en) 1764 pci_disable_msi(pcr->pci); 1765 } 1766 1767 static int rtsx_pci_runtime_suspend(struct device *device) 1768 { 1769 struct pci_dev *pcidev = to_pci_dev(device); 1770 struct pcr_handle *handle; 1771 struct rtsx_pcr *pcr; 1772 1773 handle = pci_get_drvdata(pcidev); 1774 pcr = handle->pcr; 1775 dev_dbg(&(pcidev->dev), "--> %s\n", __func__); 1776 1777 cancel_delayed_work(&pcr->carddet_work); 1778 cancel_delayed_work(&pcr->rtd3_work); 1779 cancel_delayed_work(&pcr->idle_work); 1780 1781 mutex_lock(&pcr->pcr_mutex); 1782 rtsx_pci_power_off(pcr, HOST_ENTER_S3); 1783 1784 free_irq(pcr->irq, (void *)pcr); 1785 1786 mutex_unlock(&pcr->pcr_mutex); 1787 1788 pcr->is_runtime_suspended = true; 1789 1790 return 0; 1791 } 1792 1793 static int rtsx_pci_runtime_resume(struct device *device) 1794 { 1795 struct pci_dev *pcidev = to_pci_dev(device); 1796 struct pcr_handle *handle; 1797 struct rtsx_pcr *pcr; 1798 int ret = 0; 1799 1800 handle = pci_get_drvdata(pcidev); 1801 pcr = handle->pcr; 1802 dev_dbg(&(pcidev->dev), "--> %s\n", __func__); 1803 1804 mutex_lock(&pcr->pcr_mutex); 1805 1806 rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00); 1807 rtsx_pci_acquire_irq(pcr); 1808 synchronize_irq(pcr->irq); 1809 1810 if (pcr->ops->fetch_vendor_settings) 1811 pcr->ops->fetch_vendor_settings(pcr); 1812 1813 rtsx_pci_init_hw(pcr); 1814 1815 if (pcr->slots[RTSX_SD_CARD].p_dev != NULL) { 1816 pcr->slots[RTSX_SD_CARD].card_event( 1817 pcr->slots[RTSX_SD_CARD].p_dev); 1818 } 1819 1820 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200)); 1821 1822 mutex_unlock(&pcr->pcr_mutex); 1823 return ret; 1824 } 1825 1826 #else /* CONFIG_PM */ 1827 1828 #define rtsx_pci_shutdown NULL 1829 #define rtsx_pci_runtime_suspend NULL 1830 #define rtsx_pic_runtime_resume NULL 1831 1832 #endif /* CONFIG_PM */ 1833 1834 static const struct dev_pm_ops rtsx_pci_pm_ops = { 1835 SET_SYSTEM_SLEEP_PM_OPS(rtsx_pci_suspend, rtsx_pci_resume) 1836 SET_RUNTIME_PM_OPS(rtsx_pci_runtime_suspend, rtsx_pci_runtime_resume, NULL) 1837 }; 1838 1839 static struct pci_driver rtsx_pci_driver = { 1840 .name = DRV_NAME_RTSX_PCI, 1841 .id_table = rtsx_pci_ids, 1842 .probe = rtsx_pci_probe, 1843 .remove = rtsx_pci_remove, 1844 .driver.pm = &rtsx_pci_pm_ops, 1845 .shutdown = rtsx_pci_shutdown, 1846 }; 1847 module_pci_driver(rtsx_pci_driver); 1848 1849 MODULE_LICENSE("GPL"); 1850 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>"); 1851 MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver"); 1852