1 /* Driver for Realtek PCI-Express card reader 2 * 3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2, or (at your option) any 8 * later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 * 18 * Author: 19 * Wei WANG <wei_wang@realsil.com.cn> 20 */ 21 22 #include <linux/pci.h> 23 #include <linux/module.h> 24 #include <linux/slab.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/highmem.h> 27 #include <linux/interrupt.h> 28 #include <linux/delay.h> 29 #include <linux/idr.h> 30 #include <linux/platform_device.h> 31 #include <linux/mfd/core.h> 32 #include <linux/rtsx_pci.h> 33 #include <linux/mmc/card.h> 34 #include <asm/unaligned.h> 35 36 #include "rtsx_pcr.h" 37 38 static bool msi_en = true; 39 module_param(msi_en, bool, S_IRUGO | S_IWUSR); 40 MODULE_PARM_DESC(msi_en, "Enable MSI"); 41 42 static DEFINE_IDR(rtsx_pci_idr); 43 static DEFINE_SPINLOCK(rtsx_pci_lock); 44 45 static struct mfd_cell rtsx_pcr_cells[] = { 46 [RTSX_SD_CARD] = { 47 .name = DRV_NAME_RTSX_PCI_SDMMC, 48 }, 49 [RTSX_MS_CARD] = { 50 .name = DRV_NAME_RTSX_PCI_MS, 51 }, 52 }; 53 54 static const struct pci_device_id rtsx_pci_ids[] = { 55 { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 56 { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 57 { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 58 { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 59 { PCI_DEVICE(0x10EC, 0x522A), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 60 { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 61 { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 62 { PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 63 { PCI_DEVICE(0x10EC, 0x524A), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 64 { PCI_DEVICE(0x10EC, 0x525A), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 65 { PCI_DEVICE(0x10EC, 0x5260), PCI_CLASS_OTHERS << 16, 0xFF0000 }, 66 { 0, } 67 }; 68 69 MODULE_DEVICE_TABLE(pci, rtsx_pci_ids); 70 71 static inline void rtsx_pci_enable_aspm(struct rtsx_pcr *pcr) 72 { 73 rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL, 74 0xFC, pcr->aspm_en); 75 } 76 77 static inline void rtsx_pci_disable_aspm(struct rtsx_pcr *pcr) 78 { 79 rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL, 80 0xFC, 0); 81 } 82 83 static int rtsx_comm_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency) 84 { 85 rtsx_pci_write_register(pcr, MSGTXDATA0, 86 MASK_8_BIT_DEF, (u8) (latency & 0xFF)); 87 rtsx_pci_write_register(pcr, MSGTXDATA1, 88 MASK_8_BIT_DEF, (u8)((latency >> 8) & 0xFF)); 89 rtsx_pci_write_register(pcr, MSGTXDATA2, 90 MASK_8_BIT_DEF, (u8)((latency >> 16) & 0xFF)); 91 rtsx_pci_write_register(pcr, MSGTXDATA3, 92 MASK_8_BIT_DEF, (u8)((latency >> 24) & 0xFF)); 93 rtsx_pci_write_register(pcr, LTR_CTL, LTR_TX_EN_MASK | 94 LTR_LATENCY_MODE_MASK, LTR_TX_EN_1 | LTR_LATENCY_MODE_SW); 95 96 return 0; 97 } 98 99 int rtsx_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency) 100 { 101 if (pcr->ops->set_ltr_latency) 102 return pcr->ops->set_ltr_latency(pcr, latency); 103 else 104 return rtsx_comm_set_ltr_latency(pcr, latency); 105 } 106 107 static void rtsx_comm_set_aspm(struct rtsx_pcr *pcr, bool enable) 108 { 109 struct rtsx_cr_option *option = &pcr->option; 110 111 if (pcr->aspm_enabled == enable) 112 return; 113 114 if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) { 115 if (enable) 116 rtsx_pci_enable_aspm(pcr); 117 else 118 rtsx_pci_disable_aspm(pcr); 119 } else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) { 120 u8 mask = FORCE_ASPM_VAL_MASK; 121 u8 val = 0; 122 123 if (enable) 124 val = pcr->aspm_en; 125 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); 126 } 127 128 pcr->aspm_enabled = enable; 129 } 130 131 static void rtsx_disable_aspm(struct rtsx_pcr *pcr) 132 { 133 if (pcr->ops->set_aspm) 134 pcr->ops->set_aspm(pcr, false); 135 else 136 rtsx_comm_set_aspm(pcr, false); 137 } 138 139 int rtsx_set_l1off_sub(struct rtsx_pcr *pcr, u8 val) 140 { 141 rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, val); 142 143 return 0; 144 } 145 146 static void rtsx_set_l1off_sub_cfg_d0(struct rtsx_pcr *pcr, int active) 147 { 148 if (pcr->ops->set_l1off_cfg_sub_d0) 149 pcr->ops->set_l1off_cfg_sub_d0(pcr, active); 150 } 151 152 static void rtsx_comm_pm_full_on(struct rtsx_pcr *pcr) 153 { 154 struct rtsx_cr_option *option = &pcr->option; 155 156 rtsx_disable_aspm(pcr); 157 158 if (option->ltr_enabled) 159 rtsx_set_ltr_latency(pcr, option->ltr_active_latency); 160 161 if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_EN)) 162 rtsx_set_l1off_sub_cfg_d0(pcr, 1); 163 } 164 165 static void rtsx_pm_full_on(struct rtsx_pcr *pcr) 166 { 167 if (pcr->ops->full_on) 168 pcr->ops->full_on(pcr); 169 else 170 rtsx_comm_pm_full_on(pcr); 171 } 172 173 void rtsx_pci_start_run(struct rtsx_pcr *pcr) 174 { 175 /* If pci device removed, don't queue idle work any more */ 176 if (pcr->remove_pci) 177 return; 178 179 if (pcr->state != PDEV_STAT_RUN) { 180 pcr->state = PDEV_STAT_RUN; 181 if (pcr->ops->enable_auto_blink) 182 pcr->ops->enable_auto_blink(pcr); 183 rtsx_pm_full_on(pcr); 184 } 185 186 mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200)); 187 } 188 EXPORT_SYMBOL_GPL(rtsx_pci_start_run); 189 190 int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data) 191 { 192 int i; 193 u32 val = HAIMR_WRITE_START; 194 195 val |= (u32)(addr & 0x3FFF) << 16; 196 val |= (u32)mask << 8; 197 val |= (u32)data; 198 199 rtsx_pci_writel(pcr, RTSX_HAIMR, val); 200 201 for (i = 0; i < MAX_RW_REG_CNT; i++) { 202 val = rtsx_pci_readl(pcr, RTSX_HAIMR); 203 if ((val & HAIMR_TRANS_END) == 0) { 204 if (data != (u8)val) 205 return -EIO; 206 return 0; 207 } 208 } 209 210 return -ETIMEDOUT; 211 } 212 EXPORT_SYMBOL_GPL(rtsx_pci_write_register); 213 214 int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data) 215 { 216 u32 val = HAIMR_READ_START; 217 int i; 218 219 val |= (u32)(addr & 0x3FFF) << 16; 220 rtsx_pci_writel(pcr, RTSX_HAIMR, val); 221 222 for (i = 0; i < MAX_RW_REG_CNT; i++) { 223 val = rtsx_pci_readl(pcr, RTSX_HAIMR); 224 if ((val & HAIMR_TRANS_END) == 0) 225 break; 226 } 227 228 if (i >= MAX_RW_REG_CNT) 229 return -ETIMEDOUT; 230 231 if (data) 232 *data = (u8)(val & 0xFF); 233 234 return 0; 235 } 236 EXPORT_SYMBOL_GPL(rtsx_pci_read_register); 237 238 int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val) 239 { 240 int err, i, finished = 0; 241 u8 tmp; 242 243 rtsx_pci_init_cmd(pcr); 244 245 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val); 246 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8)); 247 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr); 248 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81); 249 250 err = rtsx_pci_send_cmd(pcr, 100); 251 if (err < 0) 252 return err; 253 254 for (i = 0; i < 100000; i++) { 255 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp); 256 if (err < 0) 257 return err; 258 259 if (!(tmp & 0x80)) { 260 finished = 1; 261 break; 262 } 263 } 264 265 if (!finished) 266 return -ETIMEDOUT; 267 268 return 0; 269 } 270 271 int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val) 272 { 273 if (pcr->ops->write_phy) 274 return pcr->ops->write_phy(pcr, addr, val); 275 276 return __rtsx_pci_write_phy_register(pcr, addr, val); 277 } 278 EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register); 279 280 int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val) 281 { 282 int err, i, finished = 0; 283 u16 data; 284 u8 *ptr, tmp; 285 286 rtsx_pci_init_cmd(pcr); 287 288 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr); 289 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80); 290 291 err = rtsx_pci_send_cmd(pcr, 100); 292 if (err < 0) 293 return err; 294 295 for (i = 0; i < 100000; i++) { 296 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp); 297 if (err < 0) 298 return err; 299 300 if (!(tmp & 0x80)) { 301 finished = 1; 302 break; 303 } 304 } 305 306 if (!finished) 307 return -ETIMEDOUT; 308 309 rtsx_pci_init_cmd(pcr); 310 311 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0); 312 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0); 313 314 err = rtsx_pci_send_cmd(pcr, 100); 315 if (err < 0) 316 return err; 317 318 ptr = rtsx_pci_get_cmd_data(pcr); 319 data = ((u16)ptr[1] << 8) | ptr[0]; 320 321 if (val) 322 *val = data; 323 324 return 0; 325 } 326 327 int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val) 328 { 329 if (pcr->ops->read_phy) 330 return pcr->ops->read_phy(pcr, addr, val); 331 332 return __rtsx_pci_read_phy_register(pcr, addr, val); 333 } 334 EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register); 335 336 void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr) 337 { 338 if (pcr->ops->stop_cmd) 339 return pcr->ops->stop_cmd(pcr); 340 341 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD); 342 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA); 343 344 rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80); 345 rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80); 346 } 347 EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd); 348 349 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr, 350 u8 cmd_type, u16 reg_addr, u8 mask, u8 data) 351 { 352 unsigned long flags; 353 u32 val = 0; 354 u32 *ptr = (u32 *)(pcr->host_cmds_ptr); 355 356 val |= (u32)(cmd_type & 0x03) << 30; 357 val |= (u32)(reg_addr & 0x3FFF) << 16; 358 val |= (u32)mask << 8; 359 val |= (u32)data; 360 361 spin_lock_irqsave(&pcr->lock, flags); 362 ptr += pcr->ci; 363 if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) { 364 put_unaligned_le32(val, ptr); 365 ptr++; 366 pcr->ci++; 367 } 368 spin_unlock_irqrestore(&pcr->lock, flags); 369 } 370 EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd); 371 372 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr) 373 { 374 u32 val = 1 << 31; 375 376 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr); 377 378 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF; 379 /* Hardware Auto Response */ 380 val |= 0x40000000; 381 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val); 382 } 383 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait); 384 385 int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout) 386 { 387 struct completion trans_done; 388 u32 val = 1 << 31; 389 long timeleft; 390 unsigned long flags; 391 int err = 0; 392 393 spin_lock_irqsave(&pcr->lock, flags); 394 395 /* set up data structures for the wakeup system */ 396 pcr->done = &trans_done; 397 pcr->trans_result = TRANS_NOT_READY; 398 init_completion(&trans_done); 399 400 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr); 401 402 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF; 403 /* Hardware Auto Response */ 404 val |= 0x40000000; 405 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val); 406 407 spin_unlock_irqrestore(&pcr->lock, flags); 408 409 /* Wait for TRANS_OK_INT */ 410 timeleft = wait_for_completion_interruptible_timeout( 411 &trans_done, msecs_to_jiffies(timeout)); 412 if (timeleft <= 0) { 413 pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__); 414 err = -ETIMEDOUT; 415 goto finish_send_cmd; 416 } 417 418 spin_lock_irqsave(&pcr->lock, flags); 419 if (pcr->trans_result == TRANS_RESULT_FAIL) 420 err = -EINVAL; 421 else if (pcr->trans_result == TRANS_RESULT_OK) 422 err = 0; 423 else if (pcr->trans_result == TRANS_NO_DEVICE) 424 err = -ENODEV; 425 spin_unlock_irqrestore(&pcr->lock, flags); 426 427 finish_send_cmd: 428 spin_lock_irqsave(&pcr->lock, flags); 429 pcr->done = NULL; 430 spin_unlock_irqrestore(&pcr->lock, flags); 431 432 if ((err < 0) && (err != -ENODEV)) 433 rtsx_pci_stop_cmd(pcr); 434 435 if (pcr->finish_me) 436 complete(pcr->finish_me); 437 438 return err; 439 } 440 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd); 441 442 static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr, 443 dma_addr_t addr, unsigned int len, int end) 444 { 445 u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi; 446 u64 val; 447 u8 option = RTSX_SG_VALID | RTSX_SG_TRANS_DATA; 448 449 pcr_dbg(pcr, "DMA addr: 0x%x, Len: 0x%x\n", (unsigned int)addr, len); 450 451 if (end) 452 option |= RTSX_SG_END; 453 val = ((u64)addr << 32) | ((u64)len << 12) | option; 454 455 put_unaligned_le64(val, ptr); 456 pcr->sgi++; 457 } 458 459 int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist, 460 int num_sg, bool read, int timeout) 461 { 462 int err = 0, count; 463 464 pcr_dbg(pcr, "--> %s: num_sg = %d\n", __func__, num_sg); 465 count = rtsx_pci_dma_map_sg(pcr, sglist, num_sg, read); 466 if (count < 1) 467 return -EINVAL; 468 pcr_dbg(pcr, "DMA mapping count: %d\n", count); 469 470 err = rtsx_pci_dma_transfer(pcr, sglist, count, read, timeout); 471 472 rtsx_pci_dma_unmap_sg(pcr, sglist, num_sg, read); 473 474 return err; 475 } 476 EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data); 477 478 int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist, 479 int num_sg, bool read) 480 { 481 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 482 483 if (pcr->remove_pci) 484 return -EINVAL; 485 486 if ((sglist == NULL) || (num_sg <= 0)) 487 return -EINVAL; 488 489 return dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dir); 490 } 491 EXPORT_SYMBOL_GPL(rtsx_pci_dma_map_sg); 492 493 void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist, 494 int num_sg, bool read) 495 { 496 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 497 498 dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dir); 499 } 500 EXPORT_SYMBOL_GPL(rtsx_pci_dma_unmap_sg); 501 502 int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist, 503 int count, bool read, int timeout) 504 { 505 struct completion trans_done; 506 struct scatterlist *sg; 507 dma_addr_t addr; 508 long timeleft; 509 unsigned long flags; 510 unsigned int len; 511 int i, err = 0; 512 u32 val; 513 u8 dir = read ? DEVICE_TO_HOST : HOST_TO_DEVICE; 514 515 if (pcr->remove_pci) 516 return -ENODEV; 517 518 if ((sglist == NULL) || (count < 1)) 519 return -EINVAL; 520 521 val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE; 522 pcr->sgi = 0; 523 for_each_sg(sglist, sg, count, i) { 524 addr = sg_dma_address(sg); 525 len = sg_dma_len(sg); 526 rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1); 527 } 528 529 spin_lock_irqsave(&pcr->lock, flags); 530 531 pcr->done = &trans_done; 532 pcr->trans_result = TRANS_NOT_READY; 533 init_completion(&trans_done); 534 rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr); 535 rtsx_pci_writel(pcr, RTSX_HDBCTLR, val); 536 537 spin_unlock_irqrestore(&pcr->lock, flags); 538 539 timeleft = wait_for_completion_interruptible_timeout( 540 &trans_done, msecs_to_jiffies(timeout)); 541 if (timeleft <= 0) { 542 pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__); 543 err = -ETIMEDOUT; 544 goto out; 545 } 546 547 spin_lock_irqsave(&pcr->lock, flags); 548 if (pcr->trans_result == TRANS_RESULT_FAIL) { 549 err = -EILSEQ; 550 if (pcr->dma_error_count < RTS_MAX_TIMES_FREQ_REDUCTION) 551 pcr->dma_error_count++; 552 } 553 554 else if (pcr->trans_result == TRANS_NO_DEVICE) 555 err = -ENODEV; 556 spin_unlock_irqrestore(&pcr->lock, flags); 557 558 out: 559 spin_lock_irqsave(&pcr->lock, flags); 560 pcr->done = NULL; 561 spin_unlock_irqrestore(&pcr->lock, flags); 562 563 if ((err < 0) && (err != -ENODEV)) 564 rtsx_pci_stop_cmd(pcr); 565 566 if (pcr->finish_me) 567 complete(pcr->finish_me); 568 569 return err; 570 } 571 EXPORT_SYMBOL_GPL(rtsx_pci_dma_transfer); 572 573 int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len) 574 { 575 int err; 576 int i, j; 577 u16 reg; 578 u8 *ptr; 579 580 if (buf_len > 512) 581 buf_len = 512; 582 583 ptr = buf; 584 reg = PPBUF_BASE2; 585 for (i = 0; i < buf_len / 256; i++) { 586 rtsx_pci_init_cmd(pcr); 587 588 for (j = 0; j < 256; j++) 589 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0); 590 591 err = rtsx_pci_send_cmd(pcr, 250); 592 if (err < 0) 593 return err; 594 595 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256); 596 ptr += 256; 597 } 598 599 if (buf_len % 256) { 600 rtsx_pci_init_cmd(pcr); 601 602 for (j = 0; j < buf_len % 256; j++) 603 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0); 604 605 err = rtsx_pci_send_cmd(pcr, 250); 606 if (err < 0) 607 return err; 608 } 609 610 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256); 611 612 return 0; 613 } 614 EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf); 615 616 int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len) 617 { 618 int err; 619 int i, j; 620 u16 reg; 621 u8 *ptr; 622 623 if (buf_len > 512) 624 buf_len = 512; 625 626 ptr = buf; 627 reg = PPBUF_BASE2; 628 for (i = 0; i < buf_len / 256; i++) { 629 rtsx_pci_init_cmd(pcr); 630 631 for (j = 0; j < 256; j++) { 632 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 633 reg++, 0xFF, *ptr); 634 ptr++; 635 } 636 637 err = rtsx_pci_send_cmd(pcr, 250); 638 if (err < 0) 639 return err; 640 } 641 642 if (buf_len % 256) { 643 rtsx_pci_init_cmd(pcr); 644 645 for (j = 0; j < buf_len % 256; j++) { 646 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 647 reg++, 0xFF, *ptr); 648 ptr++; 649 } 650 651 err = rtsx_pci_send_cmd(pcr, 250); 652 if (err < 0) 653 return err; 654 } 655 656 return 0; 657 } 658 EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf); 659 660 static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl) 661 { 662 rtsx_pci_init_cmd(pcr); 663 664 while (*tbl & 0xFFFF0000) { 665 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 666 (u16)(*tbl >> 16), 0xFF, (u8)(*tbl)); 667 tbl++; 668 } 669 670 return rtsx_pci_send_cmd(pcr, 100); 671 } 672 673 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card) 674 { 675 const u32 *tbl; 676 677 if (card == RTSX_SD_CARD) 678 tbl = pcr->sd_pull_ctl_enable_tbl; 679 else if (card == RTSX_MS_CARD) 680 tbl = pcr->ms_pull_ctl_enable_tbl; 681 else 682 return -EINVAL; 683 684 return rtsx_pci_set_pull_ctl(pcr, tbl); 685 } 686 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable); 687 688 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card) 689 { 690 const u32 *tbl; 691 692 if (card == RTSX_SD_CARD) 693 tbl = pcr->sd_pull_ctl_disable_tbl; 694 else if (card == RTSX_MS_CARD) 695 tbl = pcr->ms_pull_ctl_disable_tbl; 696 else 697 return -EINVAL; 698 699 700 return rtsx_pci_set_pull_ctl(pcr, tbl); 701 } 702 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable); 703 704 static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr) 705 { 706 struct rtsx_hw_param *hw_param = &pcr->hw_param; 707 708 pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN 709 | hw_param->interrupt_en; 710 711 if (pcr->num_slots > 1) 712 pcr->bier |= MS_INT_EN; 713 714 /* Enable Bus Interrupt */ 715 rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier); 716 717 pcr_dbg(pcr, "RTSX_BIER: 0x%08x\n", pcr->bier); 718 } 719 720 static inline u8 double_ssc_depth(u8 depth) 721 { 722 return ((depth > 1) ? (depth - 1) : depth); 723 } 724 725 static u8 revise_ssc_depth(u8 ssc_depth, u8 div) 726 { 727 if (div > CLK_DIV_1) { 728 if (ssc_depth > (div - 1)) 729 ssc_depth -= (div - 1); 730 else 731 ssc_depth = SSC_DEPTH_4M; 732 } 733 734 return ssc_depth; 735 } 736 737 int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, 738 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk) 739 { 740 int err, clk; 741 u8 n, clk_divider, mcu_cnt, div; 742 static const u8 depth[] = { 743 [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M, 744 [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M, 745 [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M, 746 [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K, 747 [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K, 748 }; 749 750 if (initial_mode) { 751 /* We use 250k(around) here, in initial stage */ 752 clk_divider = SD_CLK_DIVIDE_128; 753 card_clock = 30000000; 754 } else { 755 clk_divider = SD_CLK_DIVIDE_0; 756 } 757 err = rtsx_pci_write_register(pcr, SD_CFG1, 758 SD_CLK_DIVIDE_MASK, clk_divider); 759 if (err < 0) 760 return err; 761 762 /* Reduce card clock by 20MHz each time a DMA transfer error occurs */ 763 if (card_clock == UHS_SDR104_MAX_DTR && 764 pcr->dma_error_count && 765 PCI_PID(pcr) == RTS5227_DEVICE_ID) 766 card_clock = UHS_SDR104_MAX_DTR - 767 (pcr->dma_error_count * 20000000); 768 769 card_clock /= 1000000; 770 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock); 771 772 clk = card_clock; 773 if (!initial_mode && double_clk) 774 clk = card_clock * 2; 775 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n", 776 clk, pcr->cur_clock); 777 778 if (clk == pcr->cur_clock) 779 return 0; 780 781 if (pcr->ops->conv_clk_and_div_n) 782 n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N); 783 else 784 n = (u8)(clk - 2); 785 if ((clk <= 2) || (n > MAX_DIV_N_PCR)) 786 return -EINVAL; 787 788 mcu_cnt = (u8)(125/clk + 3); 789 if (mcu_cnt > 15) 790 mcu_cnt = 15; 791 792 /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */ 793 div = CLK_DIV_1; 794 while ((n < MIN_DIV_N_PCR) && (div < CLK_DIV_8)) { 795 if (pcr->ops->conv_clk_and_div_n) { 796 int dbl_clk = pcr->ops->conv_clk_and_div_n(n, 797 DIV_N_TO_CLK) * 2; 798 n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk, 799 CLK_TO_DIV_N); 800 } else { 801 n = (n + 2) * 2 - 2; 802 } 803 div++; 804 } 805 pcr_dbg(pcr, "n = %d, div = %d\n", n, div); 806 807 ssc_depth = depth[ssc_depth]; 808 if (double_clk) 809 ssc_depth = double_ssc_depth(ssc_depth); 810 811 ssc_depth = revise_ssc_depth(ssc_depth, div); 812 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth); 813 814 rtsx_pci_init_cmd(pcr); 815 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 816 CLK_LOW_FREQ, CLK_LOW_FREQ); 817 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 818 0xFF, (div << 4) | mcu_cnt); 819 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); 820 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 821 SSC_DEPTH_MASK, ssc_depth); 822 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n); 823 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB); 824 if (vpclk) { 825 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, 826 PHASE_NOT_RESET, 0); 827 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, 828 PHASE_NOT_RESET, PHASE_NOT_RESET); 829 } 830 831 err = rtsx_pci_send_cmd(pcr, 2000); 832 if (err < 0) 833 return err; 834 835 /* Wait SSC clock stable */ 836 udelay(SSC_CLOCK_STABLE_WAIT); 837 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); 838 if (err < 0) 839 return err; 840 841 pcr->cur_clock = clk; 842 return 0; 843 } 844 EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock); 845 846 int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card) 847 { 848 if (pcr->ops->card_power_on) 849 return pcr->ops->card_power_on(pcr, card); 850 851 return 0; 852 } 853 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on); 854 855 int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card) 856 { 857 if (pcr->ops->card_power_off) 858 return pcr->ops->card_power_off(pcr, card); 859 860 return 0; 861 } 862 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off); 863 864 int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card) 865 { 866 static const unsigned int cd_mask[] = { 867 [RTSX_SD_CARD] = SD_EXIST, 868 [RTSX_MS_CARD] = MS_EXIST 869 }; 870 871 if (!(pcr->flags & PCR_MS_PMOS)) { 872 /* When using single PMOS, accessing card is not permitted 873 * if the existing card is not the designated one. 874 */ 875 if (pcr->card_exist & (~cd_mask[card])) 876 return -EIO; 877 } 878 879 return 0; 880 } 881 EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check); 882 883 int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) 884 { 885 if (pcr->ops->switch_output_voltage) 886 return pcr->ops->switch_output_voltage(pcr, voltage); 887 888 return 0; 889 } 890 EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage); 891 892 unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr) 893 { 894 unsigned int val; 895 896 val = rtsx_pci_readl(pcr, RTSX_BIPR); 897 if (pcr->ops->cd_deglitch) 898 val = pcr->ops->cd_deglitch(pcr); 899 900 return val; 901 } 902 EXPORT_SYMBOL_GPL(rtsx_pci_card_exist); 903 904 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr) 905 { 906 struct completion finish; 907 908 pcr->finish_me = &finish; 909 init_completion(&finish); 910 911 if (pcr->done) 912 complete(pcr->done); 913 914 if (!pcr->remove_pci) 915 rtsx_pci_stop_cmd(pcr); 916 917 wait_for_completion_interruptible_timeout(&finish, 918 msecs_to_jiffies(2)); 919 pcr->finish_me = NULL; 920 } 921 EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer); 922 923 static void rtsx_pci_card_detect(struct work_struct *work) 924 { 925 struct delayed_work *dwork; 926 struct rtsx_pcr *pcr; 927 unsigned long flags; 928 unsigned int card_detect = 0, card_inserted, card_removed; 929 u32 irq_status; 930 931 dwork = to_delayed_work(work); 932 pcr = container_of(dwork, struct rtsx_pcr, carddet_work); 933 934 pcr_dbg(pcr, "--> %s\n", __func__); 935 936 mutex_lock(&pcr->pcr_mutex); 937 spin_lock_irqsave(&pcr->lock, flags); 938 939 irq_status = rtsx_pci_readl(pcr, RTSX_BIPR); 940 pcr_dbg(pcr, "irq_status: 0x%08x\n", irq_status); 941 942 irq_status &= CARD_EXIST; 943 card_inserted = pcr->card_inserted & irq_status; 944 card_removed = pcr->card_removed; 945 pcr->card_inserted = 0; 946 pcr->card_removed = 0; 947 948 spin_unlock_irqrestore(&pcr->lock, flags); 949 950 if (card_inserted || card_removed) { 951 pcr_dbg(pcr, "card_inserted: 0x%x, card_removed: 0x%x\n", 952 card_inserted, card_removed); 953 954 if (pcr->ops->cd_deglitch) 955 card_inserted = pcr->ops->cd_deglitch(pcr); 956 957 card_detect = card_inserted | card_removed; 958 959 pcr->card_exist |= card_inserted; 960 pcr->card_exist &= ~card_removed; 961 } 962 963 mutex_unlock(&pcr->pcr_mutex); 964 965 if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event) 966 pcr->slots[RTSX_SD_CARD].card_event( 967 pcr->slots[RTSX_SD_CARD].p_dev); 968 if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event) 969 pcr->slots[RTSX_MS_CARD].card_event( 970 pcr->slots[RTSX_MS_CARD].p_dev); 971 } 972 973 static void rtsx_pci_process_ocp(struct rtsx_pcr *pcr) 974 { 975 if (pcr->ops->process_ocp) { 976 pcr->ops->process_ocp(pcr); 977 } else { 978 if (!pcr->option.ocp_en) 979 return; 980 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat); 981 if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) { 982 rtsx_pci_card_power_off(pcr, RTSX_SD_CARD); 983 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0); 984 rtsx_pci_clear_ocpstat(pcr); 985 pcr->ocp_stat = 0; 986 } 987 } 988 } 989 990 static int rtsx_pci_process_ocp_interrupt(struct rtsx_pcr *pcr) 991 { 992 if (pcr->option.ocp_en) 993 rtsx_pci_process_ocp(pcr); 994 995 return 0; 996 } 997 998 static irqreturn_t rtsx_pci_isr(int irq, void *dev_id) 999 { 1000 struct rtsx_pcr *pcr = dev_id; 1001 u32 int_reg; 1002 1003 if (!pcr) 1004 return IRQ_NONE; 1005 1006 spin_lock(&pcr->lock); 1007 1008 int_reg = rtsx_pci_readl(pcr, RTSX_BIPR); 1009 /* Clear interrupt flag */ 1010 rtsx_pci_writel(pcr, RTSX_BIPR, int_reg); 1011 if ((int_reg & pcr->bier) == 0) { 1012 spin_unlock(&pcr->lock); 1013 return IRQ_NONE; 1014 } 1015 if (int_reg == 0xFFFFFFFF) { 1016 spin_unlock(&pcr->lock); 1017 return IRQ_HANDLED; 1018 } 1019 1020 int_reg &= (pcr->bier | 0x7FFFFF); 1021 1022 if (int_reg & SD_OC_INT) 1023 rtsx_pci_process_ocp_interrupt(pcr); 1024 1025 if (int_reg & SD_INT) { 1026 if (int_reg & SD_EXIST) { 1027 pcr->card_inserted |= SD_EXIST; 1028 } else { 1029 pcr->card_removed |= SD_EXIST; 1030 pcr->card_inserted &= ~SD_EXIST; 1031 } 1032 pcr->dma_error_count = 0; 1033 } 1034 1035 if (int_reg & MS_INT) { 1036 if (int_reg & MS_EXIST) { 1037 pcr->card_inserted |= MS_EXIST; 1038 } else { 1039 pcr->card_removed |= MS_EXIST; 1040 pcr->card_inserted &= ~MS_EXIST; 1041 } 1042 } 1043 1044 if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) { 1045 if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) { 1046 pcr->trans_result = TRANS_RESULT_FAIL; 1047 if (pcr->done) 1048 complete(pcr->done); 1049 } else if (int_reg & TRANS_OK_INT) { 1050 pcr->trans_result = TRANS_RESULT_OK; 1051 if (pcr->done) 1052 complete(pcr->done); 1053 } 1054 } 1055 1056 if ((pcr->card_inserted || pcr->card_removed) && !(int_reg & SD_OC_INT)) 1057 schedule_delayed_work(&pcr->carddet_work, 1058 msecs_to_jiffies(200)); 1059 1060 spin_unlock(&pcr->lock); 1061 return IRQ_HANDLED; 1062 } 1063 1064 static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr) 1065 { 1066 pcr_dbg(pcr, "%s: pcr->msi_en = %d, pci->irq = %d\n", 1067 __func__, pcr->msi_en, pcr->pci->irq); 1068 1069 if (request_irq(pcr->pci->irq, rtsx_pci_isr, 1070 pcr->msi_en ? 0 : IRQF_SHARED, 1071 DRV_NAME_RTSX_PCI, pcr)) { 1072 dev_err(&(pcr->pci->dev), 1073 "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n", 1074 pcr->pci->irq); 1075 return -1; 1076 } 1077 1078 pcr->irq = pcr->pci->irq; 1079 pci_intx(pcr->pci, !pcr->msi_en); 1080 1081 return 0; 1082 } 1083 1084 static void rtsx_enable_aspm(struct rtsx_pcr *pcr) 1085 { 1086 if (pcr->ops->set_aspm) 1087 pcr->ops->set_aspm(pcr, true); 1088 else 1089 rtsx_comm_set_aspm(pcr, true); 1090 } 1091 1092 static void rtsx_comm_pm_power_saving(struct rtsx_pcr *pcr) 1093 { 1094 struct rtsx_cr_option *option = &pcr->option; 1095 1096 if (option->ltr_enabled) { 1097 u32 latency = option->ltr_l1off_latency; 1098 1099 if (rtsx_check_dev_flag(pcr, L1_SNOOZE_TEST_EN)) 1100 mdelay(option->l1_snooze_delay); 1101 1102 rtsx_set_ltr_latency(pcr, latency); 1103 } 1104 1105 if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_EN)) 1106 rtsx_set_l1off_sub_cfg_d0(pcr, 0); 1107 1108 rtsx_enable_aspm(pcr); 1109 } 1110 1111 static void rtsx_pm_power_saving(struct rtsx_pcr *pcr) 1112 { 1113 if (pcr->ops->power_saving) 1114 pcr->ops->power_saving(pcr); 1115 else 1116 rtsx_comm_pm_power_saving(pcr); 1117 } 1118 1119 static void rtsx_pci_idle_work(struct work_struct *work) 1120 { 1121 struct delayed_work *dwork = to_delayed_work(work); 1122 struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work); 1123 1124 pcr_dbg(pcr, "--> %s\n", __func__); 1125 1126 mutex_lock(&pcr->pcr_mutex); 1127 1128 pcr->state = PDEV_STAT_IDLE; 1129 1130 if (pcr->ops->disable_auto_blink) 1131 pcr->ops->disable_auto_blink(pcr); 1132 if (pcr->ops->turn_off_led) 1133 pcr->ops->turn_off_led(pcr); 1134 1135 rtsx_pm_power_saving(pcr); 1136 1137 mutex_unlock(&pcr->pcr_mutex); 1138 } 1139 1140 #ifdef CONFIG_PM 1141 static void rtsx_pci_power_off(struct rtsx_pcr *pcr, u8 pm_state) 1142 { 1143 if (pcr->ops->turn_off_led) 1144 pcr->ops->turn_off_led(pcr); 1145 1146 rtsx_pci_writel(pcr, RTSX_BIER, 0); 1147 pcr->bier = 0; 1148 1149 rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08); 1150 rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, pm_state); 1151 1152 if (pcr->ops->force_power_down) 1153 pcr->ops->force_power_down(pcr, pm_state); 1154 } 1155 #endif 1156 1157 void rtsx_pci_enable_ocp(struct rtsx_pcr *pcr) 1158 { 1159 u8 val = SD_OCP_INT_EN | SD_DETECT_EN; 1160 1161 if (pcr->ops->enable_ocp) { 1162 pcr->ops->enable_ocp(pcr); 1163 } else { 1164 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0); 1165 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val); 1166 } 1167 1168 } 1169 1170 void rtsx_pci_disable_ocp(struct rtsx_pcr *pcr) 1171 { 1172 u8 mask = SD_OCP_INT_EN | SD_DETECT_EN; 1173 1174 if (pcr->ops->disable_ocp) { 1175 pcr->ops->disable_ocp(pcr); 1176 } else { 1177 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); 1178 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 1179 OC_POWER_DOWN); 1180 } 1181 } 1182 1183 void rtsx_pci_init_ocp(struct rtsx_pcr *pcr) 1184 { 1185 if (pcr->ops->init_ocp) { 1186 pcr->ops->init_ocp(pcr); 1187 } else { 1188 struct rtsx_cr_option *option = &(pcr->option); 1189 1190 if (option->ocp_en) { 1191 u8 val = option->sd_800mA_ocp_thd; 1192 1193 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0); 1194 rtsx_pci_write_register(pcr, REG_OCPPARA1, 1195 SD_OCP_TIME_MASK, SD_OCP_TIME_800); 1196 rtsx_pci_write_register(pcr, REG_OCPPARA2, 1197 SD_OCP_THD_MASK, val); 1198 rtsx_pci_write_register(pcr, REG_OCPGLITCH, 1199 SD_OCP_GLITCH_MASK, pcr->hw_param.ocp_glitch); 1200 rtsx_pci_enable_ocp(pcr); 1201 } else { 1202 /* OC power down */ 1203 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 1204 OC_POWER_DOWN); 1205 } 1206 } 1207 } 1208 1209 int rtsx_pci_get_ocpstat(struct rtsx_pcr *pcr, u8 *val) 1210 { 1211 if (pcr->ops->get_ocpstat) 1212 return pcr->ops->get_ocpstat(pcr, val); 1213 else 1214 return rtsx_pci_read_register(pcr, REG_OCPSTAT, val); 1215 } 1216 1217 void rtsx_pci_clear_ocpstat(struct rtsx_pcr *pcr) 1218 { 1219 if (pcr->ops->clear_ocpstat) { 1220 pcr->ops->clear_ocpstat(pcr); 1221 } else { 1222 u8 mask = SD_OCP_INT_CLR | SD_OC_CLR; 1223 u8 val = SD_OCP_INT_CLR | SD_OC_CLR; 1224 1225 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val); 1226 udelay(100); 1227 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); 1228 } 1229 } 1230 1231 int rtsx_sd_power_off_card3v3(struct rtsx_pcr *pcr) 1232 { 1233 rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN | 1234 MS_CLK_EN | SD40_CLK_EN, 0); 1235 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0); 1236 rtsx_pci_card_power_off(pcr, RTSX_SD_CARD); 1237 1238 msleep(50); 1239 1240 rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD); 1241 1242 return 0; 1243 } 1244 1245 int rtsx_ms_power_off_card3v3(struct rtsx_pcr *pcr) 1246 { 1247 rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN | 1248 MS_CLK_EN | SD40_CLK_EN, 0); 1249 1250 rtsx_pci_card_pull_ctl_disable(pcr, RTSX_MS_CARD); 1251 1252 rtsx_pci_write_register(pcr, CARD_OE, MS_OUTPUT_EN, 0); 1253 rtsx_pci_card_power_off(pcr, RTSX_MS_CARD); 1254 1255 return 0; 1256 } 1257 1258 static int rtsx_pci_init_hw(struct rtsx_pcr *pcr) 1259 { 1260 int err; 1261 1262 pcr->pcie_cap = pci_find_capability(pcr->pci, PCI_CAP_ID_EXP); 1263 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr); 1264 1265 rtsx_pci_enable_bus_int(pcr); 1266 1267 /* Power on SSC */ 1268 err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0); 1269 if (err < 0) 1270 return err; 1271 1272 /* Wait SSC power stable */ 1273 udelay(200); 1274 1275 rtsx_pci_disable_aspm(pcr); 1276 if (pcr->ops->optimize_phy) { 1277 err = pcr->ops->optimize_phy(pcr); 1278 if (err < 0) 1279 return err; 1280 } 1281 1282 rtsx_pci_init_cmd(pcr); 1283 1284 /* Set mcu_cnt to 7 to ensure data can be sampled properly */ 1285 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07); 1286 1287 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00); 1288 /* Disable card clock */ 1289 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0); 1290 /* Reset delink mode */ 1291 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0); 1292 /* Card driving select */ 1293 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL, 1294 0xFF, pcr->card_drive_sel); 1295 /* Enable SSC Clock */ 1296 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, 1297 0xFF, SSC_8X_EN | SSC_SEL_4M); 1298 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12); 1299 /* Disable cd_pwr_save */ 1300 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10); 1301 /* Clear Link Ready Interrupt */ 1302 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, 1303 LINK_RDY_INT, LINK_RDY_INT); 1304 /* Enlarge the estimation window of PERST# glitch 1305 * to reduce the chance of invalid card interrupt 1306 */ 1307 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80); 1308 /* Update RC oscillator to 400k 1309 * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1 1310 * 1: 2M 0: 400k 1311 */ 1312 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00); 1313 /* Set interrupt write clear 1314 * bit 1: U_elbi_if_rd_clr_en 1315 * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear 1316 * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear 1317 */ 1318 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0); 1319 1320 err = rtsx_pci_send_cmd(pcr, 100); 1321 if (err < 0) 1322 return err; 1323 1324 switch (PCI_PID(pcr)) { 1325 case PID_5250: 1326 case PID_524A: 1327 case PID_525A: 1328 case PID_5260: 1329 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 1, 1); 1330 break; 1331 default: 1332 break; 1333 } 1334 1335 /*init ocp*/ 1336 rtsx_pci_init_ocp(pcr); 1337 1338 /* Enable clk_request_n to enable clock power management */ 1339 rtsx_pci_write_config_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL + 1, 1); 1340 /* Enter L1 when host tx idle */ 1341 rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B); 1342 1343 if (pcr->ops->extra_init_hw) { 1344 err = pcr->ops->extra_init_hw(pcr); 1345 if (err < 0) 1346 return err; 1347 } 1348 1349 /* No CD interrupt if probing driver with card inserted. 1350 * So we need to initialize pcr->card_exist here. 1351 */ 1352 if (pcr->ops->cd_deglitch) 1353 pcr->card_exist = pcr->ops->cd_deglitch(pcr); 1354 else 1355 pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST; 1356 1357 return 0; 1358 } 1359 1360 static int rtsx_pci_init_chip(struct rtsx_pcr *pcr) 1361 { 1362 int err; 1363 1364 spin_lock_init(&pcr->lock); 1365 mutex_init(&pcr->pcr_mutex); 1366 1367 switch (PCI_PID(pcr)) { 1368 default: 1369 case 0x5209: 1370 rts5209_init_params(pcr); 1371 break; 1372 1373 case 0x5229: 1374 rts5229_init_params(pcr); 1375 break; 1376 1377 case 0x5289: 1378 rtl8411_init_params(pcr); 1379 break; 1380 1381 case 0x5227: 1382 rts5227_init_params(pcr); 1383 break; 1384 1385 case 0x522A: 1386 rts522a_init_params(pcr); 1387 break; 1388 1389 case 0x5249: 1390 rts5249_init_params(pcr); 1391 break; 1392 1393 case 0x524A: 1394 rts524a_init_params(pcr); 1395 break; 1396 1397 case 0x525A: 1398 rts525a_init_params(pcr); 1399 break; 1400 1401 case 0x5287: 1402 rtl8411b_init_params(pcr); 1403 break; 1404 1405 case 0x5286: 1406 rtl8402_init_params(pcr); 1407 break; 1408 case 0x5260: 1409 rts5260_init_params(pcr); 1410 break; 1411 } 1412 1413 pcr_dbg(pcr, "PID: 0x%04x, IC version: 0x%02x\n", 1414 PCI_PID(pcr), pcr->ic_version); 1415 1416 pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot), 1417 GFP_KERNEL); 1418 if (!pcr->slots) 1419 return -ENOMEM; 1420 1421 if (pcr->ops->fetch_vendor_settings) 1422 pcr->ops->fetch_vendor_settings(pcr); 1423 1424 pcr_dbg(pcr, "pcr->aspm_en = 0x%x\n", pcr->aspm_en); 1425 pcr_dbg(pcr, "pcr->sd30_drive_sel_1v8 = 0x%x\n", 1426 pcr->sd30_drive_sel_1v8); 1427 pcr_dbg(pcr, "pcr->sd30_drive_sel_3v3 = 0x%x\n", 1428 pcr->sd30_drive_sel_3v3); 1429 pcr_dbg(pcr, "pcr->card_drive_sel = 0x%x\n", 1430 pcr->card_drive_sel); 1431 pcr_dbg(pcr, "pcr->flags = 0x%x\n", pcr->flags); 1432 1433 pcr->state = PDEV_STAT_IDLE; 1434 err = rtsx_pci_init_hw(pcr); 1435 if (err < 0) { 1436 kfree(pcr->slots); 1437 return err; 1438 } 1439 1440 return 0; 1441 } 1442 1443 static int rtsx_pci_probe(struct pci_dev *pcidev, 1444 const struct pci_device_id *id) 1445 { 1446 struct rtsx_pcr *pcr; 1447 struct pcr_handle *handle; 1448 u32 base, len; 1449 int ret, i, bar = 0; 1450 1451 dev_dbg(&(pcidev->dev), 1452 ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n", 1453 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device, 1454 (int)pcidev->revision); 1455 1456 ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32)); 1457 if (ret < 0) 1458 return ret; 1459 1460 ret = pci_enable_device(pcidev); 1461 if (ret) 1462 return ret; 1463 1464 ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI); 1465 if (ret) 1466 goto disable; 1467 1468 pcr = kzalloc(sizeof(*pcr), GFP_KERNEL); 1469 if (!pcr) { 1470 ret = -ENOMEM; 1471 goto release_pci; 1472 } 1473 1474 handle = kzalloc(sizeof(*handle), GFP_KERNEL); 1475 if (!handle) { 1476 ret = -ENOMEM; 1477 goto free_pcr; 1478 } 1479 handle->pcr = pcr; 1480 1481 idr_preload(GFP_KERNEL); 1482 spin_lock(&rtsx_pci_lock); 1483 ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT); 1484 if (ret >= 0) 1485 pcr->id = ret; 1486 spin_unlock(&rtsx_pci_lock); 1487 idr_preload_end(); 1488 if (ret < 0) 1489 goto free_handle; 1490 1491 pcr->pci = pcidev; 1492 dev_set_drvdata(&pcidev->dev, handle); 1493 1494 if (CHK_PCI_PID(pcr, 0x525A)) 1495 bar = 1; 1496 len = pci_resource_len(pcidev, bar); 1497 base = pci_resource_start(pcidev, bar); 1498 pcr->remap_addr = ioremap_nocache(base, len); 1499 if (!pcr->remap_addr) { 1500 ret = -ENOMEM; 1501 goto free_handle; 1502 } 1503 1504 pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev), 1505 RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr), 1506 GFP_KERNEL); 1507 if (pcr->rtsx_resv_buf == NULL) { 1508 ret = -ENXIO; 1509 goto unmap; 1510 } 1511 pcr->host_cmds_ptr = pcr->rtsx_resv_buf; 1512 pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr; 1513 pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN; 1514 pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN; 1515 1516 pcr->card_inserted = 0; 1517 pcr->card_removed = 0; 1518 INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect); 1519 INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work); 1520 1521 pcr->msi_en = msi_en; 1522 if (pcr->msi_en) { 1523 ret = pci_enable_msi(pcidev); 1524 if (ret) 1525 pcr->msi_en = false; 1526 } 1527 1528 ret = rtsx_pci_acquire_irq(pcr); 1529 if (ret < 0) 1530 goto disable_msi; 1531 1532 pci_set_master(pcidev); 1533 synchronize_irq(pcr->irq); 1534 1535 ret = rtsx_pci_init_chip(pcr); 1536 if (ret < 0) 1537 goto disable_irq; 1538 1539 for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) { 1540 rtsx_pcr_cells[i].platform_data = handle; 1541 rtsx_pcr_cells[i].pdata_size = sizeof(*handle); 1542 } 1543 ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells, 1544 ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL); 1545 if (ret < 0) 1546 goto disable_irq; 1547 1548 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200)); 1549 1550 return 0; 1551 1552 disable_irq: 1553 free_irq(pcr->irq, (void *)pcr); 1554 disable_msi: 1555 if (pcr->msi_en) 1556 pci_disable_msi(pcr->pci); 1557 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN, 1558 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr); 1559 unmap: 1560 iounmap(pcr->remap_addr); 1561 free_handle: 1562 kfree(handle); 1563 free_pcr: 1564 kfree(pcr); 1565 release_pci: 1566 pci_release_regions(pcidev); 1567 disable: 1568 pci_disable_device(pcidev); 1569 1570 return ret; 1571 } 1572 1573 static void rtsx_pci_remove(struct pci_dev *pcidev) 1574 { 1575 struct pcr_handle *handle = pci_get_drvdata(pcidev); 1576 struct rtsx_pcr *pcr = handle->pcr; 1577 1578 pcr->remove_pci = true; 1579 1580 /* Disable interrupts at the pcr level */ 1581 spin_lock_irq(&pcr->lock); 1582 rtsx_pci_writel(pcr, RTSX_BIER, 0); 1583 pcr->bier = 0; 1584 spin_unlock_irq(&pcr->lock); 1585 1586 cancel_delayed_work_sync(&pcr->carddet_work); 1587 cancel_delayed_work_sync(&pcr->idle_work); 1588 1589 mfd_remove_devices(&pcidev->dev); 1590 1591 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN, 1592 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr); 1593 free_irq(pcr->irq, (void *)pcr); 1594 if (pcr->msi_en) 1595 pci_disable_msi(pcr->pci); 1596 iounmap(pcr->remap_addr); 1597 1598 pci_release_regions(pcidev); 1599 pci_disable_device(pcidev); 1600 1601 spin_lock(&rtsx_pci_lock); 1602 idr_remove(&rtsx_pci_idr, pcr->id); 1603 spin_unlock(&rtsx_pci_lock); 1604 1605 kfree(pcr->slots); 1606 kfree(pcr); 1607 kfree(handle); 1608 1609 dev_dbg(&(pcidev->dev), 1610 ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n", 1611 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device); 1612 } 1613 1614 #ifdef CONFIG_PM 1615 1616 static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state) 1617 { 1618 struct pcr_handle *handle; 1619 struct rtsx_pcr *pcr; 1620 1621 dev_dbg(&(pcidev->dev), "--> %s\n", __func__); 1622 1623 handle = pci_get_drvdata(pcidev); 1624 pcr = handle->pcr; 1625 1626 cancel_delayed_work(&pcr->carddet_work); 1627 cancel_delayed_work(&pcr->idle_work); 1628 1629 mutex_lock(&pcr->pcr_mutex); 1630 1631 rtsx_pci_power_off(pcr, HOST_ENTER_S3); 1632 1633 pci_save_state(pcidev); 1634 pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0); 1635 pci_disable_device(pcidev); 1636 pci_set_power_state(pcidev, pci_choose_state(pcidev, state)); 1637 1638 mutex_unlock(&pcr->pcr_mutex); 1639 return 0; 1640 } 1641 1642 static int rtsx_pci_resume(struct pci_dev *pcidev) 1643 { 1644 struct pcr_handle *handle; 1645 struct rtsx_pcr *pcr; 1646 int ret = 0; 1647 1648 dev_dbg(&(pcidev->dev), "--> %s\n", __func__); 1649 1650 handle = pci_get_drvdata(pcidev); 1651 pcr = handle->pcr; 1652 1653 mutex_lock(&pcr->pcr_mutex); 1654 1655 pci_set_power_state(pcidev, PCI_D0); 1656 pci_restore_state(pcidev); 1657 ret = pci_enable_device(pcidev); 1658 if (ret) 1659 goto out; 1660 pci_set_master(pcidev); 1661 1662 ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00); 1663 if (ret) 1664 goto out; 1665 1666 ret = rtsx_pci_init_hw(pcr); 1667 if (ret) 1668 goto out; 1669 1670 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200)); 1671 1672 out: 1673 mutex_unlock(&pcr->pcr_mutex); 1674 return ret; 1675 } 1676 1677 static void rtsx_pci_shutdown(struct pci_dev *pcidev) 1678 { 1679 struct pcr_handle *handle; 1680 struct rtsx_pcr *pcr; 1681 1682 dev_dbg(&(pcidev->dev), "--> %s\n", __func__); 1683 1684 handle = pci_get_drvdata(pcidev); 1685 pcr = handle->pcr; 1686 rtsx_pci_power_off(pcr, HOST_ENTER_S1); 1687 1688 pci_disable_device(pcidev); 1689 free_irq(pcr->irq, (void *)pcr); 1690 if (pcr->msi_en) 1691 pci_disable_msi(pcr->pci); 1692 } 1693 1694 #else /* CONFIG_PM */ 1695 1696 #define rtsx_pci_suspend NULL 1697 #define rtsx_pci_resume NULL 1698 #define rtsx_pci_shutdown NULL 1699 1700 #endif /* CONFIG_PM */ 1701 1702 static struct pci_driver rtsx_pci_driver = { 1703 .name = DRV_NAME_RTSX_PCI, 1704 .id_table = rtsx_pci_ids, 1705 .probe = rtsx_pci_probe, 1706 .remove = rtsx_pci_remove, 1707 .suspend = rtsx_pci_suspend, 1708 .resume = rtsx_pci_resume, 1709 .shutdown = rtsx_pci_shutdown, 1710 }; 1711 module_pci_driver(rtsx_pci_driver); 1712 1713 MODULE_LICENSE("GPL"); 1714 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>"); 1715 MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver"); 1716