1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Driver for Realtek PCI-Express card reader 3 * 4 * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved. 5 * 6 * Author: 7 * Rui FENG <rui_feng@realsil.com.cn> 8 * Wei WANG <wei_wang@realsil.com.cn> 9 */ 10 11 #include <linux/module.h> 12 #include <linux/delay.h> 13 #include <linux/rtsx_pci.h> 14 15 #include "rts5261.h" 16 #include "rtsx_pcr.h" 17 18 static u8 rts5261_get_ic_version(struct rtsx_pcr *pcr) 19 { 20 u8 val; 21 22 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val); 23 return val & IC_VERSION_MASK; 24 } 25 26 static void rts5261_fill_driving(struct rtsx_pcr *pcr, u8 voltage) 27 { 28 u8 driving_3v3[4][3] = { 29 {0x13, 0x13, 0x13}, 30 {0x96, 0x96, 0x96}, 31 {0x7F, 0x7F, 0x7F}, 32 {0x96, 0x96, 0x96}, 33 }; 34 u8 driving_1v8[4][3] = { 35 {0x99, 0x99, 0x99}, 36 {0x3A, 0x3A, 0x3A}, 37 {0xE6, 0xE6, 0xE6}, 38 {0xB3, 0xB3, 0xB3}, 39 }; 40 u8 (*driving)[3], drive_sel; 41 42 if (voltage == OUTPUT_3V3) { 43 driving = driving_3v3; 44 drive_sel = pcr->sd30_drive_sel_3v3; 45 } else { 46 driving = driving_1v8; 47 drive_sel = pcr->sd30_drive_sel_1v8; 48 } 49 50 rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL, 51 0xFF, driving[drive_sel][0]); 52 53 rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL, 54 0xFF, driving[drive_sel][1]); 55 56 rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL, 57 0xFF, driving[drive_sel][2]); 58 } 59 60 static void rtsx5261_fetch_vendor_settings(struct rtsx_pcr *pcr) 61 { 62 struct pci_dev *pdev = pcr->pci; 63 u32 reg; 64 65 /* 0x814~0x817 */ 66 pci_read_config_dword(pdev, PCR_SETTING_REG2, ®); 67 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg); 68 69 if (!rts5261_vendor_setting_valid(reg)) { 70 pcr_dbg(pcr, "skip fetch vendor setting\n"); 71 return; 72 } 73 74 pcr->card_drive_sel &= 0x3F; 75 pcr->card_drive_sel |= rts5261_reg_to_card_drive_sel(reg); 76 77 if (rts5261_reg_check_reverse_socket(reg)) 78 pcr->flags |= PCR_REVERSE_SOCKET; 79 80 /* 0x724~0x727 */ 81 pci_read_config_dword(pdev, PCR_SETTING_REG1, ®); 82 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg); 83 84 pcr->aspm_en = rts5261_reg_to_aspm(reg); 85 pcr->sd30_drive_sel_1v8 = rts5261_reg_to_sd30_drive_sel_1v8(reg); 86 pcr->sd30_drive_sel_3v3 = rts5261_reg_to_sd30_drive_sel_3v3(reg); 87 } 88 89 static void rts5261_force_power_down(struct rtsx_pcr *pcr, u8 pm_state) 90 { 91 /* Set relink_time to 0 */ 92 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0); 93 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0); 94 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 95 RELINK_TIME_MASK, 0); 96 97 if (pm_state == HOST_ENTER_S3) 98 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 99 D3_DELINK_MODE_EN, D3_DELINK_MODE_EN); 100 101 rtsx_pci_write_register(pcr, RTS5261_REG_FPDCTL, 102 SSC_POWER_DOWN, SSC_POWER_DOWN); 103 } 104 105 static int rts5261_enable_auto_blink(struct rtsx_pcr *pcr) 106 { 107 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 108 LED_SHINE_MASK, LED_SHINE_EN); 109 } 110 111 static int rts5261_disable_auto_blink(struct rtsx_pcr *pcr) 112 { 113 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 114 LED_SHINE_MASK, LED_SHINE_DISABLE); 115 } 116 117 static int rts5261_turn_on_led(struct rtsx_pcr *pcr) 118 { 119 return rtsx_pci_write_register(pcr, GPIO_CTL, 120 0x02, 0x02); 121 } 122 123 static int rts5261_turn_off_led(struct rtsx_pcr *pcr) 124 { 125 return rtsx_pci_write_register(pcr, GPIO_CTL, 126 0x02, 0x00); 127 } 128 129 /* SD Pull Control Enable: 130 * SD_DAT[3:0] ==> pull up 131 * SD_CD ==> pull up 132 * SD_WP ==> pull up 133 * SD_CMD ==> pull up 134 * SD_CLK ==> pull down 135 */ 136 static const u32 rts5261_sd_pull_ctl_enable_tbl[] = { 137 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA), 138 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9), 139 0, 140 }; 141 142 /* SD Pull Control Disable: 143 * SD_DAT[3:0] ==> pull down 144 * SD_CD ==> pull up 145 * SD_WP ==> pull down 146 * SD_CMD ==> pull down 147 * SD_CLK ==> pull down 148 */ 149 static const u32 rts5261_sd_pull_ctl_disable_tbl[] = { 150 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 151 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5), 152 0, 153 }; 154 155 static int rts5261_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr) 156 { 157 rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK 158 | SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST); 159 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); 160 rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF, 161 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 162 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); 163 164 return 0; 165 } 166 167 static int rts5261_card_power_on(struct rtsx_pcr *pcr, int card) 168 { 169 struct rtsx_cr_option *option = &pcr->option; 170 171 if (option->ocp_en) 172 rtsx_pci_enable_ocp(pcr); 173 174 175 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG1, 176 RTS5261_LDO1_TUNE_MASK, RTS5261_LDO1_33); 177 rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL, 178 RTS5261_LDO1_POWERON, RTS5261_LDO1_POWERON); 179 180 rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL, 181 RTS5261_LDO3318_POWERON, RTS5261_LDO3318_POWERON); 182 183 msleep(20); 184 185 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); 186 187 /* Initialize SD_CFG1 register */ 188 rtsx_pci_write_register(pcr, SD_CFG1, 0xFF, 189 SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1BIT); 190 191 rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL, 192 0xFF, SD20_RX_POS_EDGE); 193 rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0); 194 rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR, 195 SD_STOP | SD_CLR_ERR); 196 197 /* Reset SD_CFG3 register */ 198 rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0); 199 rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG, 200 SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 | 201 SD30_CLK_STOP_CFG0, 0); 202 203 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 || 204 pcr->extra_caps & EXTRA_CAPS_SD_SDR104) 205 rts5261_sd_set_sample_push_timing_sd30(pcr); 206 207 return 0; 208 } 209 210 static int rts5261_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) 211 { 212 int err; 213 u16 val = 0; 214 215 rtsx_pci_write_register(pcr, RTS5261_CARD_PWR_CTL, 216 RTS5261_PUPDC, RTS5261_PUPDC); 217 218 switch (voltage) { 219 case OUTPUT_3V3: 220 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val); 221 val |= PHY_TUNE_SDBUS_33; 222 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val); 223 if (err < 0) 224 return err; 225 226 rtsx_pci_write_register(pcr, RTS5261_DV3318_CFG, 227 RTS5261_DV3318_TUNE_MASK, RTS5261_DV3318_33); 228 rtsx_pci_write_register(pcr, SD_PAD_CTL, 229 SD_IO_USING_1V8, 0); 230 break; 231 case OUTPUT_1V8: 232 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val); 233 val &= ~PHY_TUNE_SDBUS_33; 234 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val); 235 if (err < 0) 236 return err; 237 238 rtsx_pci_write_register(pcr, RTS5261_DV3318_CFG, 239 RTS5261_DV3318_TUNE_MASK, RTS5261_DV3318_18); 240 rtsx_pci_write_register(pcr, SD_PAD_CTL, 241 SD_IO_USING_1V8, SD_IO_USING_1V8); 242 break; 243 default: 244 return -EINVAL; 245 } 246 247 /* set pad drive */ 248 rts5261_fill_driving(pcr, voltage); 249 250 return 0; 251 } 252 253 static void rts5261_stop_cmd(struct rtsx_pcr *pcr) 254 { 255 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD); 256 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA); 257 rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0, 258 RTS5260_DMA_RST | RTS5260_ADMA3_RST, 259 RTS5260_DMA_RST | RTS5260_ADMA3_RST); 260 rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH); 261 } 262 263 static void rts5261_card_before_power_off(struct rtsx_pcr *pcr) 264 { 265 rts5261_stop_cmd(pcr); 266 rts5261_switch_output_voltage(pcr, OUTPUT_3V3); 267 268 } 269 270 static void rts5261_enable_ocp(struct rtsx_pcr *pcr) 271 { 272 u8 val = 0; 273 274 val = SD_OCP_INT_EN | SD_DETECT_EN; 275 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val); 276 277 } 278 279 static void rts5261_disable_ocp(struct rtsx_pcr *pcr) 280 { 281 u8 mask = 0; 282 283 mask = SD_OCP_INT_EN | SD_DETECT_EN; 284 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); 285 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0, 286 RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN, 0); 287 288 } 289 290 static int rts5261_card_power_off(struct rtsx_pcr *pcr, int card) 291 { 292 int err = 0; 293 294 rts5261_card_before_power_off(pcr); 295 err = rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL, 296 RTS5261_LDO_POWERON_MASK, 0); 297 298 if (pcr->option.ocp_en) 299 rtsx_pci_disable_ocp(pcr); 300 301 return err; 302 } 303 304 static void rts5261_init_ocp(struct rtsx_pcr *pcr) 305 { 306 struct rtsx_cr_option *option = &pcr->option; 307 308 if (option->ocp_en) { 309 u8 mask, val; 310 311 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0, 312 RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN, 313 RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN); 314 315 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0, 316 RTS5261_LDO1_OCP_THD_MASK, option->sd_800mA_ocp_thd); 317 318 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0, 319 RTS5261_LDO1_OCP_LMT_THD_MASK, 320 RTS5261_LDO1_LMT_THD_2000); 321 322 mask = SD_OCP_GLITCH_MASK; 323 val = pcr->hw_param.ocp_glitch; 324 rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val); 325 326 rts5261_enable_ocp(pcr); 327 } else { 328 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0, 329 RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN, 0); 330 } 331 } 332 333 static void rts5261_clear_ocpstat(struct rtsx_pcr *pcr) 334 { 335 u8 mask = 0; 336 u8 val = 0; 337 338 mask = SD_OCP_INT_CLR | SD_OC_CLR; 339 val = SD_OCP_INT_CLR | SD_OC_CLR; 340 341 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val); 342 343 udelay(10); 344 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); 345 346 } 347 348 static void rts5261_process_ocp(struct rtsx_pcr *pcr) 349 { 350 if (!pcr->option.ocp_en) 351 return; 352 353 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat); 354 355 if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) { 356 rts5261_card_power_off(pcr, RTSX_SD_CARD); 357 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0); 358 rts5261_clear_ocpstat(pcr); 359 pcr->ocp_stat = 0; 360 } 361 362 } 363 364 static int rts5261_init_from_hw(struct rtsx_pcr *pcr) 365 { 366 struct pci_dev *pdev = pcr->pci; 367 int retval; 368 u32 lval, i; 369 u8 valid, efuse_valid, tmp; 370 371 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL, 372 REG_EFUSE_POR | REG_EFUSE_POWER_MASK, 373 REG_EFUSE_POR | REG_EFUSE_POWERON); 374 udelay(1); 375 rtsx_pci_write_register(pcr, RTS5261_EFUSE_ADDR, 376 RTS5261_EFUSE_ADDR_MASK, 0x00); 377 rtsx_pci_write_register(pcr, RTS5261_EFUSE_CTL, 378 RTS5261_EFUSE_ENABLE | RTS5261_EFUSE_MODE_MASK, 379 RTS5261_EFUSE_ENABLE); 380 381 /* Wait transfer end */ 382 for (i = 0; i < MAX_RW_REG_CNT; i++) { 383 rtsx_pci_read_register(pcr, RTS5261_EFUSE_CTL, &tmp); 384 if ((tmp & 0x80) == 0) 385 break; 386 } 387 rtsx_pci_read_register(pcr, RTS5261_EFUSE_READ_DATA, &tmp); 388 efuse_valid = ((tmp & 0x0C) >> 2); 389 pcr_dbg(pcr, "Load efuse valid: 0x%x\n", efuse_valid); 390 391 if (efuse_valid == 0) { 392 retval = pci_read_config_dword(pdev, PCR_SETTING_REG2, &lval); 393 if (retval != 0) 394 pcr_dbg(pcr, "read 0x814 DW fail\n"); 395 pcr_dbg(pcr, "DW from 0x814: 0x%x\n", lval); 396 /* 0x816 */ 397 valid = (u8)((lval >> 16) & 0x03); 398 pcr_dbg(pcr, "0x816: %d\n", valid); 399 } 400 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL, 401 REG_EFUSE_POR, 0); 402 pcr_dbg(pcr, "Disable efuse por!\n"); 403 404 pci_read_config_dword(pdev, PCR_SETTING_REG2, &lval); 405 lval = lval & 0x00FFFFFF; 406 retval = pci_write_config_dword(pdev, PCR_SETTING_REG2, lval); 407 if (retval != 0) 408 pcr_dbg(pcr, "write config fail\n"); 409 410 return retval; 411 } 412 413 static void rts5261_init_from_cfg(struct rtsx_pcr *pcr) 414 { 415 struct pci_dev *pdev = pcr->pci; 416 int l1ss; 417 u32 lval; 418 struct rtsx_cr_option *option = &pcr->option; 419 420 l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); 421 if (!l1ss) 422 return; 423 424 pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval); 425 426 if (lval & PCI_L1SS_CTL1_ASPM_L1_1) 427 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); 428 else 429 rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN); 430 431 if (lval & PCI_L1SS_CTL1_ASPM_L1_2) 432 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); 433 else 434 rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN); 435 436 if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) 437 rtsx_set_dev_flag(pcr, PM_L1_1_EN); 438 else 439 rtsx_clear_dev_flag(pcr, PM_L1_1_EN); 440 441 if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) 442 rtsx_set_dev_flag(pcr, PM_L1_2_EN); 443 else 444 rtsx_clear_dev_flag(pcr, PM_L1_2_EN); 445 446 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0); 447 if (option->ltr_en) { 448 u16 val; 449 450 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val); 451 if (val & PCI_EXP_DEVCTL2_LTR_EN) { 452 option->ltr_enabled = true; 453 option->ltr_active = true; 454 rtsx_set_ltr_latency(pcr, option->ltr_active_latency); 455 } else { 456 option->ltr_enabled = false; 457 } 458 } 459 460 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN 461 | PM_L1_1_EN | PM_L1_2_EN)) 462 option->force_clkreq_0 = false; 463 else 464 option->force_clkreq_0 = true; 465 } 466 467 static int rts5261_extra_init_hw(struct rtsx_pcr *pcr) 468 { 469 struct rtsx_cr_option *option = &pcr->option; 470 471 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1, 472 CD_RESUME_EN_MASK, CD_RESUME_EN_MASK); 473 474 rts5261_init_from_cfg(pcr); 475 rts5261_init_from_hw(pcr); 476 477 /* power off efuse */ 478 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL, 479 REG_EFUSE_POWER_MASK, REG_EFUSE_POWEROFF); 480 rtsx_pci_write_register(pcr, L1SUB_CONFIG1, 481 AUX_CLK_ACTIVE_SEL_MASK, MAC_CKSW_DONE); 482 rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0); 483 484 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4, 485 RTS5261_AUX_CLK_16M_EN, 0); 486 487 /* Release PRSNT# */ 488 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4, 489 RTS5261_FORCE_PRSNT_LOW, 0); 490 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, 491 FUNC_FORCE_UPME_XMT_DBG, FUNC_FORCE_UPME_XMT_DBG); 492 493 rtsx_pci_write_register(pcr, PCLK_CTL, 494 PCLK_MODE_SEL, PCLK_MODE_SEL); 495 496 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0); 497 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, CLK_PM_EN, CLK_PM_EN); 498 499 /* LED shine disabled, set initial shine cycle period */ 500 rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02); 501 502 /* Configure driving */ 503 rts5261_fill_driving(pcr, OUTPUT_3V3); 504 505 /* 506 * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced 507 * to drive low, and we forcibly request clock. 508 */ 509 if (option->force_clkreq_0) 510 rtsx_pci_write_register(pcr, PETXCFG, 511 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); 512 else 513 rtsx_pci_write_register(pcr, PETXCFG, 514 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); 515 516 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00); 517 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL, 518 FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL); 519 520 /* Clear Enter RTD3_cold Information*/ 521 rtsx_pci_write_register(pcr, RTS5261_FW_CTL, 522 RTS5261_INFORM_RTD3_COLD, 0); 523 524 return 0; 525 } 526 527 static void rts5261_enable_aspm(struct rtsx_pcr *pcr, bool enable) 528 { 529 if (pcr->aspm_enabled == enable) 530 return; 531 532 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, 533 PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en); 534 pcr->aspm_enabled = enable; 535 536 } 537 538 static void rts5261_disable_aspm(struct rtsx_pcr *pcr, bool enable) 539 { 540 if (pcr->aspm_enabled == enable) 541 return; 542 543 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, 544 PCI_EXP_LNKCTL_ASPMC, 0); 545 rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); 546 udelay(10); 547 pcr->aspm_enabled = enable; 548 } 549 550 static void rts5261_set_aspm(struct rtsx_pcr *pcr, bool enable) 551 { 552 if (enable) 553 rts5261_enable_aspm(pcr, true); 554 else 555 rts5261_disable_aspm(pcr, false); 556 } 557 558 static void rts5261_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active) 559 { 560 struct rtsx_cr_option *option = &pcr->option; 561 int aspm_L1_1, aspm_L1_2; 562 u8 val = 0; 563 564 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN); 565 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN); 566 567 if (active) { 568 /* run, latency: 60us */ 569 if (aspm_L1_1) 570 val = option->ltr_l1off_snooze_sspwrgate; 571 } else { 572 /* l1off, latency: 300us */ 573 if (aspm_L1_2) 574 val = option->ltr_l1off_sspwrgate; 575 } 576 577 rtsx_set_l1off_sub(pcr, val); 578 } 579 580 static const struct pcr_ops rts5261_pcr_ops = { 581 .fetch_vendor_settings = rtsx5261_fetch_vendor_settings, 582 .turn_on_led = rts5261_turn_on_led, 583 .turn_off_led = rts5261_turn_off_led, 584 .extra_init_hw = rts5261_extra_init_hw, 585 .enable_auto_blink = rts5261_enable_auto_blink, 586 .disable_auto_blink = rts5261_disable_auto_blink, 587 .card_power_on = rts5261_card_power_on, 588 .card_power_off = rts5261_card_power_off, 589 .switch_output_voltage = rts5261_switch_output_voltage, 590 .force_power_down = rts5261_force_power_down, 591 .stop_cmd = rts5261_stop_cmd, 592 .set_aspm = rts5261_set_aspm, 593 .set_l1off_cfg_sub_d0 = rts5261_set_l1off_cfg_sub_d0, 594 .enable_ocp = rts5261_enable_ocp, 595 .disable_ocp = rts5261_disable_ocp, 596 .init_ocp = rts5261_init_ocp, 597 .process_ocp = rts5261_process_ocp, 598 .clear_ocpstat = rts5261_clear_ocpstat, 599 }; 600 601 static inline u8 double_ssc_depth(u8 depth) 602 { 603 return ((depth > 1) ? (depth - 1) : depth); 604 } 605 606 int rts5261_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, 607 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk) 608 { 609 int err, clk; 610 u16 n; 611 u8 clk_divider, mcu_cnt, div; 612 static const u8 depth[] = { 613 [RTSX_SSC_DEPTH_4M] = RTS5261_SSC_DEPTH_4M, 614 [RTSX_SSC_DEPTH_2M] = RTS5261_SSC_DEPTH_2M, 615 [RTSX_SSC_DEPTH_1M] = RTS5261_SSC_DEPTH_1M, 616 [RTSX_SSC_DEPTH_500K] = RTS5261_SSC_DEPTH_512K, 617 }; 618 619 if (initial_mode) { 620 /* We use 250k(around) here, in initial stage */ 621 if (is_version(pcr, PID_5261, IC_VER_D)) { 622 clk_divider = SD_CLK_DIVIDE_256; 623 card_clock = 60000000; 624 } else { 625 clk_divider = SD_CLK_DIVIDE_128; 626 card_clock = 30000000; 627 } 628 } else { 629 clk_divider = SD_CLK_DIVIDE_0; 630 } 631 err = rtsx_pci_write_register(pcr, SD_CFG1, 632 SD_CLK_DIVIDE_MASK, clk_divider); 633 if (err < 0) 634 return err; 635 636 card_clock /= 1000000; 637 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock); 638 639 clk = card_clock; 640 if (!initial_mode && double_clk) 641 clk = card_clock * 2; 642 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n", 643 clk, pcr->cur_clock); 644 645 if (clk == pcr->cur_clock) 646 return 0; 647 648 if (pcr->ops->conv_clk_and_div_n) 649 n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N); 650 else 651 n = clk - 4; 652 if ((clk <= 4) || (n > 396)) 653 return -EINVAL; 654 655 mcu_cnt = 125/clk + 3; 656 if (mcu_cnt > 15) 657 mcu_cnt = 15; 658 659 div = CLK_DIV_1; 660 while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) { 661 if (pcr->ops->conv_clk_and_div_n) { 662 int dbl_clk = pcr->ops->conv_clk_and_div_n(n, 663 DIV_N_TO_CLK) * 2; 664 n = pcr->ops->conv_clk_and_div_n(dbl_clk, 665 CLK_TO_DIV_N); 666 } else { 667 n = (n + 4) * 2 - 4; 668 } 669 div++; 670 } 671 672 n = (n / 2); 673 pcr_dbg(pcr, "n = %d, div = %d\n", n, div); 674 675 ssc_depth = depth[ssc_depth]; 676 if (double_clk) 677 ssc_depth = double_ssc_depth(ssc_depth); 678 679 if (ssc_depth) { 680 if (div == CLK_DIV_2) { 681 if (ssc_depth > 1) 682 ssc_depth -= 1; 683 else 684 ssc_depth = RTS5261_SSC_DEPTH_8M; 685 } else if (div == CLK_DIV_4) { 686 if (ssc_depth > 2) 687 ssc_depth -= 2; 688 else 689 ssc_depth = RTS5261_SSC_DEPTH_8M; 690 } else if (div == CLK_DIV_8) { 691 if (ssc_depth > 3) 692 ssc_depth -= 3; 693 else 694 ssc_depth = RTS5261_SSC_DEPTH_8M; 695 } 696 } else { 697 ssc_depth = 0; 698 } 699 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth); 700 701 rtsx_pci_init_cmd(pcr); 702 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 703 CLK_LOW_FREQ, CLK_LOW_FREQ); 704 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 705 0xFF, (div << 4) | mcu_cnt); 706 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); 707 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 708 SSC_DEPTH_MASK, ssc_depth); 709 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n); 710 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB); 711 if (vpclk) { 712 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, 713 PHASE_NOT_RESET, 0); 714 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL, 715 PHASE_NOT_RESET, 0); 716 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, 717 PHASE_NOT_RESET, PHASE_NOT_RESET); 718 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL, 719 PHASE_NOT_RESET, PHASE_NOT_RESET); 720 } 721 722 err = rtsx_pci_send_cmd(pcr, 2000); 723 if (err < 0) 724 return err; 725 726 /* Wait SSC clock stable */ 727 udelay(SSC_CLOCK_STABLE_WAIT); 728 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); 729 if (err < 0) 730 return err; 731 732 pcr->cur_clock = clk; 733 return 0; 734 735 } 736 737 void rts5261_init_params(struct rtsx_pcr *pcr) 738 { 739 struct rtsx_cr_option *option = &pcr->option; 740 struct rtsx_hw_param *hw_param = &pcr->hw_param; 741 742 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104; 743 pcr->num_slots = 1; 744 pcr->ops = &rts5261_pcr_ops; 745 746 pcr->flags = 0; 747 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT; 748 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B; 749 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B; 750 pcr->aspm_en = ASPM_L1_EN; 751 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 11); 752 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); 753 754 pcr->ic_version = rts5261_get_ic_version(pcr); 755 pcr->sd_pull_ctl_enable_tbl = rts5261_sd_pull_ctl_enable_tbl; 756 pcr->sd_pull_ctl_disable_tbl = rts5261_sd_pull_ctl_disable_tbl; 757 758 pcr->reg_pm_ctrl3 = RTS5261_AUTOLOAD_CFG3; 759 760 option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN 761 | LTR_L1SS_PWR_GATE_EN); 762 option->ltr_en = true; 763 764 /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */ 765 option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF; 766 option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF; 767 option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF; 768 option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF; 769 option->ltr_l1off_sspwrgate = 0x7F; 770 option->ltr_l1off_snooze_sspwrgate = 0x78; 771 772 option->ocp_en = 1; 773 hw_param->interrupt_en |= SD_OC_INT_EN; 774 hw_param->ocp_glitch = SD_OCP_GLITCH_800U; 775 option->sd_800mA_ocp_thd = RTS5261_LDO1_OCP_THD_1040; 776 } 777