1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Driver for Realtek PCI-Express card reader
3  *
4  * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.
5  *
6  * Author:
7  *   Rui FENG <rui_feng@realsil.com.cn>
8  *   Wei WANG <wei_wang@realsil.com.cn>
9  */
10 
11 #include <linux/module.h>
12 #include <linux/delay.h>
13 #include <linux/rtsx_pci.h>
14 
15 #include "rts5261.h"
16 #include "rtsx_pcr.h"
17 
18 static u8 rts5261_get_ic_version(struct rtsx_pcr *pcr)
19 {
20 	u8 val;
21 
22 	rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
23 	return val & IC_VERSION_MASK;
24 }
25 
26 static void rts5261_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
27 {
28 	u8 driving_3v3[4][3] = {
29 		{0x96, 0x96, 0x96},
30 		{0x96, 0x96, 0x96},
31 		{0x7F, 0x7F, 0x7F},
32 		{0x13, 0x13, 0x13},
33 	};
34 	u8 driving_1v8[4][3] = {
35 		{0xB3, 0xB3, 0xB3},
36 		{0x3A, 0x3A, 0x3A},
37 		{0xE6, 0xE6, 0xE6},
38 		{0x99, 0x99, 0x99},
39 	};
40 	u8 (*driving)[3], drive_sel;
41 
42 	if (voltage == OUTPUT_3V3) {
43 		driving = driving_3v3;
44 		drive_sel = pcr->sd30_drive_sel_3v3;
45 	} else {
46 		driving = driving_1v8;
47 		drive_sel = pcr->sd30_drive_sel_1v8;
48 	}
49 
50 	rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
51 			 0xFF, driving[drive_sel][0]);
52 
53 	rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
54 			 0xFF, driving[drive_sel][1]);
55 
56 	rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
57 			 0xFF, driving[drive_sel][2]);
58 }
59 
60 static void rtsx5261_fetch_vendor_settings(struct rtsx_pcr *pcr)
61 {
62 	struct pci_dev *pdev = pcr->pci;
63 	u32 reg;
64 
65 	/* 0x814~0x817 */
66 	pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
67 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
68 
69 	if (!rts5261_vendor_setting_valid(reg)) {
70 		/* Not support MMC default */
71 		pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
72 		pcr_dbg(pcr, "skip fetch vendor setting\n");
73 		return;
74 	}
75 
76 	if (!rts5261_reg_check_mmc_support(reg))
77 		pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
78 
79 	/* TO do: need to add rtd3 function */
80 	pcr->rtd3_en = rts5261_reg_to_rtd3(reg);
81 
82 	if (rts5261_reg_check_reverse_socket(reg))
83 		pcr->flags |= PCR_REVERSE_SOCKET;
84 
85 	/* 0x724~0x727 */
86 	pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
87 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
88 
89 	pcr->aspm_en = rts5261_reg_to_aspm(reg);
90 	pcr->sd30_drive_sel_1v8 = rts5261_reg_to_sd30_drive_sel_1v8(reg);
91 	pcr->sd30_drive_sel_3v3 = rts5261_reg_to_sd30_drive_sel_3v3(reg);
92 }
93 
94 static void rts5261_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
95 {
96 	/* Set relink_time to 0 */
97 	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
98 	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
99 	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
100 				RELINK_TIME_MASK, 0);
101 
102 	if (pm_state == HOST_ENTER_S3)
103 		rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
104 					D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
105 
106 	rtsx_pci_write_register(pcr, RTS5261_REG_FPDCTL,
107 		SSC_POWER_DOWN, SSC_POWER_DOWN);
108 }
109 
110 static int rts5261_enable_auto_blink(struct rtsx_pcr *pcr)
111 {
112 	return rtsx_pci_write_register(pcr, OLT_LED_CTL,
113 		LED_SHINE_MASK, LED_SHINE_EN);
114 }
115 
116 static int rts5261_disable_auto_blink(struct rtsx_pcr *pcr)
117 {
118 	return rtsx_pci_write_register(pcr, OLT_LED_CTL,
119 		LED_SHINE_MASK, LED_SHINE_DISABLE);
120 }
121 
122 static int rts5261_turn_on_led(struct rtsx_pcr *pcr)
123 {
124 	return rtsx_pci_write_register(pcr, GPIO_CTL,
125 		0x02, 0x02);
126 }
127 
128 static int rts5261_turn_off_led(struct rtsx_pcr *pcr)
129 {
130 	return rtsx_pci_write_register(pcr, GPIO_CTL,
131 		0x02, 0x00);
132 }
133 
134 /* SD Pull Control Enable:
135  *     SD_DAT[3:0] ==> pull up
136  *     SD_CD       ==> pull up
137  *     SD_WP       ==> pull up
138  *     SD_CMD      ==> pull up
139  *     SD_CLK      ==> pull down
140  */
141 static const u32 rts5261_sd_pull_ctl_enable_tbl[] = {
142 	RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
143 	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
144 	0,
145 };
146 
147 /* SD Pull Control Disable:
148  *     SD_DAT[3:0] ==> pull down
149  *     SD_CD       ==> pull up
150  *     SD_WP       ==> pull down
151  *     SD_CMD      ==> pull down
152  *     SD_CLK      ==> pull down
153  */
154 static const u32 rts5261_sd_pull_ctl_disable_tbl[] = {
155 	RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
156 	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
157 	0,
158 };
159 
160 static int rts5261_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr)
161 {
162 	rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK
163 		| SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
164 	rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
165 	rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,
166 			CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
167 	rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
168 
169 	return 0;
170 }
171 
172 static int rts5261_card_power_on(struct rtsx_pcr *pcr, int card)
173 {
174 	struct rtsx_cr_option *option = &pcr->option;
175 
176 	if (option->ocp_en)
177 		rtsx_pci_enable_ocp(pcr);
178 
179 	rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0,
180 		CFG_SD_POW_AUTO_PD, CFG_SD_POW_AUTO_PD);
181 
182 	rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG1,
183 			RTS5261_LDO1_TUNE_MASK, RTS5261_LDO1_33);
184 	rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
185 			RTS5261_LDO1_POWERON, RTS5261_LDO1_POWERON);
186 
187 	rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
188 			RTS5261_LDO3318_POWERON, RTS5261_LDO3318_POWERON);
189 
190 	msleep(20);
191 
192 	rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
193 
194 	/* Initialize SD_CFG1 register */
195 	rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,
196 			SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1BIT);
197 
198 	rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL,
199 			0xFF, SD20_RX_POS_EDGE);
200 	rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);
201 	rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR,
202 			SD_STOP | SD_CLR_ERR);
203 
204 	/* Reset SD_CFG3 register */
205 	rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);
206 	rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,
207 			SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 |
208 			SD30_CLK_STOP_CFG0, 0);
209 
210 	if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||
211 	    pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
212 		rts5261_sd_set_sample_push_timing_sd30(pcr);
213 
214 	return 0;
215 }
216 
217 static int rts5261_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
218 {
219 	int err;
220 	u16 val = 0;
221 
222 	rtsx_pci_write_register(pcr, RTS5261_CARD_PWR_CTL,
223 			RTS5261_PUPDC, RTS5261_PUPDC);
224 
225 	switch (voltage) {
226 	case OUTPUT_3V3:
227 		rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
228 		val |= PHY_TUNE_SDBUS_33;
229 		err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
230 		if (err < 0)
231 			return err;
232 
233 		rtsx_pci_write_register(pcr, RTS5261_DV3318_CFG,
234 				RTS5261_DV3318_TUNE_MASK, RTS5261_DV3318_33);
235 		rtsx_pci_write_register(pcr, SD_PAD_CTL,
236 				SD_IO_USING_1V8, 0);
237 		break;
238 	case OUTPUT_1V8:
239 		rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
240 		val &= ~PHY_TUNE_SDBUS_33;
241 		err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
242 		if (err < 0)
243 			return err;
244 
245 		rtsx_pci_write_register(pcr, RTS5261_DV3318_CFG,
246 				RTS5261_DV3318_TUNE_MASK, RTS5261_DV3318_18);
247 		rtsx_pci_write_register(pcr, SD_PAD_CTL,
248 				SD_IO_USING_1V8, SD_IO_USING_1V8);
249 		break;
250 	default:
251 		return -EINVAL;
252 	}
253 
254 	/* set pad drive */
255 	rts5261_fill_driving(pcr, voltage);
256 
257 	return 0;
258 }
259 
260 static void rts5261_stop_cmd(struct rtsx_pcr *pcr)
261 {
262 	rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
263 	rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
264 	rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0,
265 				RTS5260_DMA_RST | RTS5260_ADMA3_RST,
266 				RTS5260_DMA_RST | RTS5260_ADMA3_RST);
267 	rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH);
268 }
269 
270 static void rts5261_card_before_power_off(struct rtsx_pcr *pcr)
271 {
272 	rts5261_stop_cmd(pcr);
273 	rts5261_switch_output_voltage(pcr, OUTPUT_3V3);
274 
275 }
276 
277 static void rts5261_enable_ocp(struct rtsx_pcr *pcr)
278 {
279 	u8 val = 0;
280 
281 	val = SD_OCP_INT_EN | SD_DETECT_EN;
282 	rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
283 			RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN,
284 			RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN);
285 	rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
286 
287 }
288 
289 static void rts5261_disable_ocp(struct rtsx_pcr *pcr)
290 {
291 	u8 mask = 0;
292 
293 	mask = SD_OCP_INT_EN | SD_DETECT_EN;
294 	rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
295 	rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
296 			RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN, 0);
297 
298 }
299 
300 static int rts5261_card_power_off(struct rtsx_pcr *pcr, int card)
301 {
302 	int err = 0;
303 
304 	rts5261_card_before_power_off(pcr);
305 	err = rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
306 				RTS5261_LDO_POWERON_MASK, 0);
307 
308 	rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0,
309 		CFG_SD_POW_AUTO_PD, 0);
310 	if (pcr->option.ocp_en)
311 		rtsx_pci_disable_ocp(pcr);
312 
313 	return err;
314 }
315 
316 static void rts5261_init_ocp(struct rtsx_pcr *pcr)
317 {
318 	struct rtsx_cr_option *option = &pcr->option;
319 
320 	if (option->ocp_en) {
321 		u8 mask, val;
322 
323 		rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
324 			RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN,
325 			RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN);
326 
327 		rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
328 			RTS5261_LDO1_OCP_THD_MASK, option->sd_800mA_ocp_thd);
329 
330 		rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
331 			RTS5261_LDO1_OCP_LMT_THD_MASK,
332 			RTS5261_LDO1_LMT_THD_2000);
333 
334 		mask = SD_OCP_GLITCH_MASK;
335 		val = pcr->hw_param.ocp_glitch;
336 		rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
337 
338 		rts5261_enable_ocp(pcr);
339 	} else {
340 		rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
341 			RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN, 0);
342 	}
343 }
344 
345 static void rts5261_clear_ocpstat(struct rtsx_pcr *pcr)
346 {
347 	u8 mask = 0;
348 	u8 val = 0;
349 
350 	mask = SD_OCP_INT_CLR | SD_OC_CLR;
351 	val = SD_OCP_INT_CLR | SD_OC_CLR;
352 
353 	rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
354 
355 	udelay(1000);
356 	rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
357 
358 }
359 
360 static void rts5261_process_ocp(struct rtsx_pcr *pcr)
361 {
362 	if (!pcr->option.ocp_en)
363 		return;
364 
365 	rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
366 
367 	if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
368 		rts5261_clear_ocpstat(pcr);
369 		rts5261_card_power_off(pcr, RTSX_SD_CARD);
370 		rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
371 		pcr->ocp_stat = 0;
372 	}
373 
374 }
375 
376 static int rts5261_init_from_hw(struct rtsx_pcr *pcr)
377 {
378 	struct pci_dev *pdev = pcr->pci;
379 	int retval;
380 	u32 lval, i;
381 	u8 valid, efuse_valid, tmp;
382 
383 	rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
384 		REG_EFUSE_POR | REG_EFUSE_POWER_MASK,
385 		REG_EFUSE_POR | REG_EFUSE_POWERON);
386 	udelay(1);
387 	rtsx_pci_write_register(pcr, RTS5261_EFUSE_ADDR,
388 		RTS5261_EFUSE_ADDR_MASK, 0x00);
389 	rtsx_pci_write_register(pcr, RTS5261_EFUSE_CTL,
390 		RTS5261_EFUSE_ENABLE | RTS5261_EFUSE_MODE_MASK,
391 		RTS5261_EFUSE_ENABLE);
392 
393 	/* Wait transfer end */
394 	for (i = 0; i < MAX_RW_REG_CNT; i++) {
395 		rtsx_pci_read_register(pcr, RTS5261_EFUSE_CTL, &tmp);
396 		if ((tmp & 0x80) == 0)
397 			break;
398 	}
399 	rtsx_pci_read_register(pcr, RTS5261_EFUSE_READ_DATA, &tmp);
400 	efuse_valid = ((tmp & 0x0C) >> 2);
401 	pcr_dbg(pcr, "Load efuse valid: 0x%x\n", efuse_valid);
402 
403 	if (efuse_valid == 0) {
404 		retval = pci_read_config_dword(pdev, PCR_SETTING_REG2, &lval);
405 		if (retval != 0)
406 			pcr_dbg(pcr, "read 0x814 DW fail\n");
407 		pcr_dbg(pcr, "DW from 0x814: 0x%x\n", lval);
408 		/* 0x816 */
409 		valid = (u8)((lval >> 16) & 0x03);
410 		pcr_dbg(pcr, "0x816: %d\n", valid);
411 	}
412 	rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
413 		REG_EFUSE_POR, 0);
414 	pcr_dbg(pcr, "Disable efuse por!\n");
415 
416 	pci_read_config_dword(pdev, PCR_SETTING_REG2, &lval);
417 	lval = lval & 0x00FFFFFF;
418 	retval = pci_write_config_dword(pdev, PCR_SETTING_REG2, lval);
419 	if (retval != 0)
420 		pcr_dbg(pcr, "write config fail\n");
421 
422 	return retval;
423 }
424 
425 static void rts5261_init_from_cfg(struct rtsx_pcr *pcr)
426 {
427 	struct pci_dev *pdev = pcr->pci;
428 	int l1ss;
429 	u32 lval;
430 	struct rtsx_cr_option *option = &pcr->option;
431 
432 	l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
433 	if (!l1ss)
434 		return;
435 
436 	pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
437 
438 	if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
439 		rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
440 	else
441 		rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
442 
443 	if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
444 		rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
445 	else
446 		rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
447 
448 	if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
449 		rtsx_set_dev_flag(pcr, PM_L1_1_EN);
450 	else
451 		rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
452 
453 	if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
454 		rtsx_set_dev_flag(pcr, PM_L1_2_EN);
455 	else
456 		rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
457 
458 	rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
459 	if (option->ltr_en) {
460 		u16 val;
461 
462 		pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val);
463 		if (val & PCI_EXP_DEVCTL2_LTR_EN) {
464 			option->ltr_enabled = true;
465 			option->ltr_active = true;
466 			rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
467 		} else {
468 			option->ltr_enabled = false;
469 		}
470 	}
471 
472 	if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
473 				| PM_L1_1_EN | PM_L1_2_EN))
474 		option->force_clkreq_0 = false;
475 	else
476 		option->force_clkreq_0 = true;
477 }
478 
479 static int rts5261_extra_init_hw(struct rtsx_pcr *pcr)
480 {
481 	struct rtsx_cr_option *option = &pcr->option;
482 	u32 val;
483 
484 	rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1,
485 			CD_RESUME_EN_MASK, CD_RESUME_EN_MASK);
486 
487 	rts5261_init_from_cfg(pcr);
488 	rts5261_init_from_hw(pcr);
489 
490 	/* power off efuse */
491 	rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
492 			REG_EFUSE_POWER_MASK, REG_EFUSE_POWEROFF);
493 	rtsx_pci_write_register(pcr, L1SUB_CONFIG1,
494 			AUX_CLK_ACTIVE_SEL_MASK, MAC_CKSW_DONE);
495 	rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0);
496 
497 	if (is_version_higher_than(pcr, PID_5261, IC_VER_B)) {
498 		val = rtsx_pci_readl(pcr, RTSX_DUM_REG);
499 		rtsx_pci_writel(pcr, RTSX_DUM_REG, val | 0x1);
500 	}
501 	rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4,
502 			RTS5261_AUX_CLK_16M_EN, 0);
503 
504 	/* Release PRSNT# */
505 	rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4,
506 			RTS5261_FORCE_PRSNT_LOW, 0);
507 	rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
508 			FUNC_FORCE_UPME_XMT_DBG, FUNC_FORCE_UPME_XMT_DBG);
509 
510 	rtsx_pci_write_register(pcr, PCLK_CTL,
511 			PCLK_MODE_SEL, PCLK_MODE_SEL);
512 
513 	rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
514 	rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, CLK_PM_EN, CLK_PM_EN);
515 
516 	/* LED shine disabled, set initial shine cycle period */
517 	rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02);
518 
519 	/* Configure driving */
520 	rts5261_fill_driving(pcr, OUTPUT_3V3);
521 
522 	if (pcr->flags & PCR_REVERSE_SOCKET)
523 		rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30);
524 	else
525 		rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00);
526 
527 	/*
528 	 * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
529 	 * to drive low, and we forcibly request clock.
530 	 */
531 	if (option->force_clkreq_0)
532 		rtsx_pci_write_register(pcr, PETXCFG,
533 				 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
534 	else
535 		rtsx_pci_write_register(pcr, PETXCFG,
536 				 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
537 
538 	rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB);
539 	rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
540 	rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
541 			FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
542 
543 	/* Clear Enter RTD3_cold Information*/
544 	rtsx_pci_write_register(pcr, RTS5261_FW_CTL,
545 		RTS5261_INFORM_RTD3_COLD, 0);
546 
547 	return 0;
548 }
549 
550 static void rts5261_enable_aspm(struct rtsx_pcr *pcr, bool enable)
551 {
552 	u8 val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
553 	u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
554 
555 	if (pcr->aspm_enabled == enable)
556 		return;
557 
558 	val |= (pcr->aspm_en & 0x02);
559 	rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
560 	pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
561 					   PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en);
562 	pcr->aspm_enabled = enable;
563 }
564 
565 static void rts5261_disable_aspm(struct rtsx_pcr *pcr, bool enable)
566 {
567 	u8 val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
568 	u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
569 
570 	if (pcr->aspm_enabled == enable)
571 		return;
572 
573 	pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
574 					   PCI_EXP_LNKCTL_ASPMC, 0);
575 	rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
576 	rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
577 	udelay(10);
578 	pcr->aspm_enabled = enable;
579 }
580 
581 static void rts5261_set_aspm(struct rtsx_pcr *pcr, bool enable)
582 {
583 	if (enable)
584 		rts5261_enable_aspm(pcr, true);
585 	else
586 		rts5261_disable_aspm(pcr, false);
587 }
588 
589 static void rts5261_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
590 {
591 	struct rtsx_cr_option *option = &pcr->option;
592 	int aspm_L1_1, aspm_L1_2;
593 	u8 val = 0;
594 
595 	aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
596 	aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
597 
598 	if (active) {
599 		/* run, latency: 60us */
600 		if (aspm_L1_1)
601 			val = option->ltr_l1off_snooze_sspwrgate;
602 	} else {
603 		/* l1off, latency: 300us */
604 		if (aspm_L1_2)
605 			val = option->ltr_l1off_sspwrgate;
606 	}
607 
608 	rtsx_set_l1off_sub(pcr, val);
609 }
610 
611 static const struct pcr_ops rts5261_pcr_ops = {
612 	.fetch_vendor_settings = rtsx5261_fetch_vendor_settings,
613 	.turn_on_led = rts5261_turn_on_led,
614 	.turn_off_led = rts5261_turn_off_led,
615 	.extra_init_hw = rts5261_extra_init_hw,
616 	.enable_auto_blink = rts5261_enable_auto_blink,
617 	.disable_auto_blink = rts5261_disable_auto_blink,
618 	.card_power_on = rts5261_card_power_on,
619 	.card_power_off = rts5261_card_power_off,
620 	.switch_output_voltage = rts5261_switch_output_voltage,
621 	.force_power_down = rts5261_force_power_down,
622 	.stop_cmd = rts5261_stop_cmd,
623 	.set_aspm = rts5261_set_aspm,
624 	.set_l1off_cfg_sub_d0 = rts5261_set_l1off_cfg_sub_d0,
625 	.enable_ocp = rts5261_enable_ocp,
626 	.disable_ocp = rts5261_disable_ocp,
627 	.init_ocp = rts5261_init_ocp,
628 	.process_ocp = rts5261_process_ocp,
629 	.clear_ocpstat = rts5261_clear_ocpstat,
630 };
631 
632 static inline u8 double_ssc_depth(u8 depth)
633 {
634 	return ((depth > 1) ? (depth - 1) : depth);
635 }
636 
637 int rts5261_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
638 		u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
639 {
640 	int err, clk;
641 	u16 n;
642 	u8 clk_divider, mcu_cnt, div;
643 	static const u8 depth[] = {
644 		[RTSX_SSC_DEPTH_4M] = RTS5261_SSC_DEPTH_4M,
645 		[RTSX_SSC_DEPTH_2M] = RTS5261_SSC_DEPTH_2M,
646 		[RTSX_SSC_DEPTH_1M] = RTS5261_SSC_DEPTH_1M,
647 		[RTSX_SSC_DEPTH_500K] = RTS5261_SSC_DEPTH_512K,
648 	};
649 
650 	if (initial_mode) {
651 		/* We use 250k(around) here, in initial stage */
652 		if (is_version_higher_than(pcr, PID_5261, IC_VER_C)) {
653 			clk_divider = SD_CLK_DIVIDE_256;
654 			card_clock = 60000000;
655 		} else {
656 			clk_divider = SD_CLK_DIVIDE_128;
657 			card_clock = 30000000;
658 		}
659 	} else {
660 		clk_divider = SD_CLK_DIVIDE_0;
661 	}
662 	err = rtsx_pci_write_register(pcr, SD_CFG1,
663 			SD_CLK_DIVIDE_MASK, clk_divider);
664 	if (err < 0)
665 		return err;
666 
667 	card_clock /= 1000000;
668 	pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
669 
670 	clk = card_clock;
671 	if (!initial_mode && double_clk)
672 		clk = card_clock * 2;
673 	pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
674 		clk, pcr->cur_clock);
675 
676 	if (clk == pcr->cur_clock)
677 		return 0;
678 
679 	if (pcr->ops->conv_clk_and_div_n)
680 		n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
681 	else
682 		n = clk - 4;
683 	if ((clk <= 4) || (n > 396))
684 		return -EINVAL;
685 
686 	mcu_cnt = 125/clk + 3;
687 	if (mcu_cnt > 15)
688 		mcu_cnt = 15;
689 
690 	div = CLK_DIV_1;
691 	while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) {
692 		if (pcr->ops->conv_clk_and_div_n) {
693 			int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
694 					DIV_N_TO_CLK) * 2;
695 			n = pcr->ops->conv_clk_and_div_n(dbl_clk,
696 					CLK_TO_DIV_N);
697 		} else {
698 			n = (n + 4) * 2 - 4;
699 		}
700 		div++;
701 	}
702 
703 	n = (n / 2) - 1;
704 	pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
705 
706 	ssc_depth = depth[ssc_depth];
707 	if (double_clk)
708 		ssc_depth = double_ssc_depth(ssc_depth);
709 
710 	if (ssc_depth) {
711 		if (div == CLK_DIV_2) {
712 			if (ssc_depth > 1)
713 				ssc_depth -= 1;
714 			else
715 				ssc_depth = RTS5261_SSC_DEPTH_8M;
716 		} else if (div == CLK_DIV_4) {
717 			if (ssc_depth > 2)
718 				ssc_depth -= 2;
719 			else
720 				ssc_depth = RTS5261_SSC_DEPTH_8M;
721 		} else if (div == CLK_DIV_8) {
722 			if (ssc_depth > 3)
723 				ssc_depth -= 3;
724 			else
725 				ssc_depth = RTS5261_SSC_DEPTH_8M;
726 		}
727 	} else {
728 		ssc_depth = 0;
729 	}
730 	pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
731 
732 	rtsx_pci_init_cmd(pcr);
733 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
734 				CLK_LOW_FREQ, CLK_LOW_FREQ);
735 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
736 			0xFF, (div << 4) | mcu_cnt);
737 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
738 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
739 			SSC_DEPTH_MASK, ssc_depth);
740 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
741 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
742 	if (vpclk) {
743 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
744 				PHASE_NOT_RESET, 0);
745 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
746 				PHASE_NOT_RESET, 0);
747 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
748 				PHASE_NOT_RESET, PHASE_NOT_RESET);
749 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
750 				PHASE_NOT_RESET, PHASE_NOT_RESET);
751 	}
752 
753 	err = rtsx_pci_send_cmd(pcr, 2000);
754 	if (err < 0)
755 		return err;
756 
757 	/* Wait SSC clock stable */
758 	udelay(SSC_CLOCK_STABLE_WAIT);
759 	err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
760 	if (err < 0)
761 		return err;
762 
763 	pcr->cur_clock = clk;
764 	return 0;
765 
766 }
767 
768 void rts5261_init_params(struct rtsx_pcr *pcr)
769 {
770 	struct rtsx_cr_option *option = &pcr->option;
771 	struct rtsx_hw_param *hw_param = &pcr->hw_param;
772 	u8 val;
773 
774 	pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
775 	rtsx_pci_read_register(pcr, RTS5261_FW_STATUS, &val);
776 	if (!(val & RTS5261_EXPRESS_LINK_FAIL_MASK))
777 		pcr->extra_caps |= EXTRA_CAPS_SD_EXPRESS;
778 	pcr->num_slots = 1;
779 	pcr->ops = &rts5261_pcr_ops;
780 
781 	pcr->flags = 0;
782 	pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
783 	pcr->sd30_drive_sel_1v8 = 0x00;
784 	pcr->sd30_drive_sel_3v3 = 0x00;
785 	pcr->aspm_en = ASPM_L1_EN;
786 	pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 11);
787 	pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
788 
789 	pcr->ic_version = rts5261_get_ic_version(pcr);
790 	pcr->sd_pull_ctl_enable_tbl = rts5261_sd_pull_ctl_enable_tbl;
791 	pcr->sd_pull_ctl_disable_tbl = rts5261_sd_pull_ctl_disable_tbl;
792 
793 	pcr->reg_pm_ctrl3 = RTS5261_AUTOLOAD_CFG3;
794 
795 	option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
796 				| LTR_L1SS_PWR_GATE_EN);
797 	option->ltr_en = true;
798 
799 	/* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
800 	option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
801 	option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
802 	option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
803 	option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
804 	option->ltr_l1off_sspwrgate = 0x7F;
805 	option->ltr_l1off_snooze_sspwrgate = 0x78;
806 
807 	option->ocp_en = 1;
808 	hw_param->interrupt_en |= SD_OC_INT_EN;
809 	hw_param->ocp_glitch =  SD_OCP_GLITCH_800U;
810 	option->sd_800mA_ocp_thd =  RTS5261_LDO1_OCP_THD_1040;
811 }
812