15da4e04aSRui Feng #ifndef __RTS5260_H__ 25da4e04aSRui Feng #define __RTS5260_H__ 35da4e04aSRui Feng 45da4e04aSRui Feng #define RTS5260_DVCC_CTRL 0xFF73 55da4e04aSRui Feng #define RTS5260_DVCC_OCP_EN (0x01 << 7) 65da4e04aSRui Feng #define RTS5260_DVCC_OCP_THD_MASK (0x07 << 4) 75da4e04aSRui Feng #define RTS5260_DVCC_POWERON (0x01 << 3) 85da4e04aSRui Feng #define RTS5260_DVCC_OCP_CL_EN (0x01 << 2) 95da4e04aSRui Feng 105da4e04aSRui Feng #define RTS5260_DVIO_CTRL 0xFF75 115da4e04aSRui Feng #define RTS5260_DVIO_OCP_EN (0x01 << 7) 125da4e04aSRui Feng #define RTS5260_DVIO_OCP_THD_MASK (0x07 << 4) 135da4e04aSRui Feng #define RTS5260_DVIO_POWERON (0x01 << 3) 145da4e04aSRui Feng #define RTS5260_DVIO_OCP_CL_EN (0x01 << 2) 155da4e04aSRui Feng 165da4e04aSRui Feng #define RTS5260_DV331812_CFG 0xFF71 175da4e04aSRui Feng #define RTS5260_DV331812_OCP_EN (0x01 << 7) 185da4e04aSRui Feng #define RTS5260_DV331812_OCP_THD_MASK (0x07 << 4) 195da4e04aSRui Feng #define RTS5260_DV331812_POWERON (0x01 << 3) 205da4e04aSRui Feng #define RTS5260_DV331812_SEL (0x01 << 2) 215da4e04aSRui Feng #define RTS5260_DV331812_VDD1 (0x01 << 2) 225da4e04aSRui Feng #define RTS5260_DV331812_VDD2 (0x00 << 2) 235da4e04aSRui Feng 245da4e04aSRui Feng #define RTS5260_DV331812_OCP_THD_120 (0x00 << 4) 255da4e04aSRui Feng #define RTS5260_DV331812_OCP_THD_140 (0x01 << 4) 265da4e04aSRui Feng #define RTS5260_DV331812_OCP_THD_160 (0x02 << 4) 275da4e04aSRui Feng #define RTS5260_DV331812_OCP_THD_180 (0x03 << 4) 285da4e04aSRui Feng #define RTS5260_DV331812_OCP_THD_210 (0x04 << 4) 295da4e04aSRui Feng #define RTS5260_DV331812_OCP_THD_240 (0x05 << 4) 305da4e04aSRui Feng #define RTS5260_DV331812_OCP_THD_270 (0x06 << 4) 315da4e04aSRui Feng #define RTS5260_DV331812_OCP_THD_300 (0x07 << 4) 325da4e04aSRui Feng 335da4e04aSRui Feng #define RTS5260_DVIO_OCP_THD_250 (0x00 << 4) 345da4e04aSRui Feng #define RTS5260_DVIO_OCP_THD_300 (0x01 << 4) 355da4e04aSRui Feng #define RTS5260_DVIO_OCP_THD_350 (0x02 << 4) 365da4e04aSRui Feng #define RTS5260_DVIO_OCP_THD_400 (0x03 << 4) 375da4e04aSRui Feng #define RTS5260_DVIO_OCP_THD_450 (0x04 << 4) 385da4e04aSRui Feng #define RTS5260_DVIO_OCP_THD_500 (0x05 << 4) 395da4e04aSRui Feng #define RTS5260_DVIO_OCP_THD_550 (0x06 << 4) 405da4e04aSRui Feng #define RTS5260_DVIO_OCP_THD_600 (0x07 << 4) 415da4e04aSRui Feng 425da4e04aSRui Feng #define RTS5260_DVCC_OCP_THD_550 (0x00 << 4) 435da4e04aSRui Feng #define RTS5260_DVCC_OCP_THD_970 (0x05 << 4) 445da4e04aSRui Feng 455da4e04aSRui Feng #endif 46