1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Driver for Realtek PCI-Express card reader 3 * 4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 5 * 6 * Author: 7 * Wei WANG <wei_wang@realsil.com.cn> 8 */ 9 10 #include <linux/module.h> 11 #include <linux/delay.h> 12 #include <linux/rtsx_pci.h> 13 14 #include "rtsx_pcr.h" 15 16 static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr) 17 { 18 u8 val; 19 20 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val); 21 return val & 0x0F; 22 } 23 24 static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage) 25 { 26 u8 driving_3v3[4][3] = { 27 {0x11, 0x11, 0x18}, 28 {0x55, 0x55, 0x5C}, 29 {0xFF, 0xFF, 0xFF}, 30 {0x96, 0x96, 0x96}, 31 }; 32 u8 driving_1v8[4][3] = { 33 {0xC4, 0xC4, 0xC4}, 34 {0x3C, 0x3C, 0x3C}, 35 {0xFE, 0xFE, 0xFE}, 36 {0xB3, 0xB3, 0xB3}, 37 }; 38 u8 (*driving)[3], drive_sel; 39 40 if (voltage == OUTPUT_3V3) { 41 driving = driving_3v3; 42 drive_sel = pcr->sd30_drive_sel_3v3; 43 } else { 44 driving = driving_1v8; 45 drive_sel = pcr->sd30_drive_sel_1v8; 46 } 47 48 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL, 49 0xFF, driving[drive_sel][0]); 50 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL, 51 0xFF, driving[drive_sel][1]); 52 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL, 53 0xFF, driving[drive_sel][2]); 54 } 55 56 static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr) 57 { 58 u32 reg; 59 60 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®); 61 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg); 62 63 if (!rtsx_vendor_setting_valid(reg)) { 64 pcr_dbg(pcr, "skip fetch vendor setting\n"); 65 return; 66 } 67 68 pcr->aspm_en = rtsx_reg_to_aspm(reg); 69 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg); 70 pcr->card_drive_sel &= 0x3F; 71 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg); 72 73 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, ®); 74 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg); 75 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg); 76 if (rtsx_reg_check_reverse_socket(reg)) 77 pcr->flags |= PCR_REVERSE_SOCKET; 78 } 79 80 static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state) 81 { 82 /* Set relink_time to 0 */ 83 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0); 84 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0); 85 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0); 86 87 if (pm_state == HOST_ENTER_S3) 88 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 89 D3_DELINK_MODE_EN, D3_DELINK_MODE_EN); 90 91 rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03); 92 } 93 94 static void rts5249_init_from_cfg(struct rtsx_pcr *pcr) 95 { 96 struct rtsx_cr_option *option = &(pcr->option); 97 u32 lval; 98 99 if (CHK_PCI_PID(pcr, PID_524A)) 100 rtsx_pci_read_config_dword(pcr, 101 PCR_ASPM_SETTING_REG1, &lval); 102 else 103 rtsx_pci_read_config_dword(pcr, 104 PCR_ASPM_SETTING_REG2, &lval); 105 106 if (lval & ASPM_L1_1_EN_MASK) 107 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); 108 109 if (lval & ASPM_L1_2_EN_MASK) 110 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); 111 112 if (lval & PM_L1_1_EN_MASK) 113 rtsx_set_dev_flag(pcr, PM_L1_1_EN); 114 115 if (lval & PM_L1_2_EN_MASK) 116 rtsx_set_dev_flag(pcr, PM_L1_2_EN); 117 118 if (option->ltr_en) { 119 u16 val; 120 121 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val); 122 if (val & PCI_EXP_DEVCTL2_LTR_EN) { 123 option->ltr_enabled = true; 124 option->ltr_active = true; 125 rtsx_set_ltr_latency(pcr, option->ltr_active_latency); 126 } else { 127 option->ltr_enabled = false; 128 } 129 } 130 } 131 132 static int rts5249_init_from_hw(struct rtsx_pcr *pcr) 133 { 134 struct rtsx_cr_option *option = &(pcr->option); 135 136 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN 137 | PM_L1_1_EN | PM_L1_2_EN)) 138 option->force_clkreq_0 = false; 139 else 140 option->force_clkreq_0 = true; 141 142 return 0; 143 } 144 145 static int rts5249_extra_init_hw(struct rtsx_pcr *pcr) 146 { 147 struct rtsx_cr_option *option = &(pcr->option); 148 149 rts5249_init_from_cfg(pcr); 150 rts5249_init_from_hw(pcr); 151 152 rtsx_pci_init_cmd(pcr); 153 154 /* Rest L1SUB Config */ 155 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00); 156 /* Configure GPIO as output */ 157 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02); 158 /* Reset ASPM state to default value */ 159 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0); 160 /* Switch LDO3318 source from DV33 to card_3v3 */ 161 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00); 162 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01); 163 /* LED shine disabled, set initial shine cycle period */ 164 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02); 165 /* Configure driving */ 166 rts5249_fill_driving(pcr, OUTPUT_3V3); 167 if (pcr->flags & PCR_REVERSE_SOCKET) 168 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0); 169 else 170 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80); 171 172 /* 173 * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced 174 * to drive low, and we forcibly request clock. 175 */ 176 if (option->force_clkreq_0) 177 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 178 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); 179 else 180 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 181 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); 182 183 return rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF); 184 } 185 186 static int rts5249_optimize_phy(struct rtsx_pcr *pcr) 187 { 188 int err; 189 190 err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00); 191 if (err < 0) 192 return err; 193 194 err = rtsx_pci_write_phy_register(pcr, PHY_REV, 195 PHY_REV_RESV | PHY_REV_RXIDLE_LATCHED | 196 PHY_REV_P1_EN | PHY_REV_RXIDLE_EN | 197 PHY_REV_CLKREQ_TX_EN | PHY_REV_RX_PWST | 198 PHY_REV_CLKREQ_DT_1_0 | PHY_REV_STOP_CLKRD | 199 PHY_REV_STOP_CLKWR); 200 if (err < 0) 201 return err; 202 203 msleep(1); 204 205 err = rtsx_pci_write_phy_register(pcr, PHY_BPCR, 206 PHY_BPCR_IBRXSEL | PHY_BPCR_IBTXSEL | 207 PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN); 208 if (err < 0) 209 return err; 210 211 err = rtsx_pci_write_phy_register(pcr, PHY_PCR, 212 PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 | 213 PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | 214 PHY_PCR_RSSI_EN | PHY_PCR_RX10K); 215 if (err < 0) 216 return err; 217 218 err = rtsx_pci_write_phy_register(pcr, PHY_RCR2, 219 PHY_RCR2_EMPHASE_EN | PHY_RCR2_NADJR | 220 PHY_RCR2_CDR_SR_2 | PHY_RCR2_FREQSEL_12 | 221 PHY_RCR2_CDR_SC_12P | PHY_RCR2_CALIB_LATE); 222 if (err < 0) 223 return err; 224 225 err = rtsx_pci_write_phy_register(pcr, PHY_FLD4, 226 PHY_FLD4_FLDEN_SEL | PHY_FLD4_REQ_REF | 227 PHY_FLD4_RXAMP_OFF | PHY_FLD4_REQ_ADDA | 228 PHY_FLD4_BER_COUNT | PHY_FLD4_BER_TIMER | 229 PHY_FLD4_BER_CHK_EN); 230 if (err < 0) 231 return err; 232 err = rtsx_pci_write_phy_register(pcr, PHY_RDR, 233 PHY_RDR_RXDSEL_1_9 | PHY_SSC_AUTO_PWD); 234 if (err < 0) 235 return err; 236 err = rtsx_pci_write_phy_register(pcr, PHY_RCR1, 237 PHY_RCR1_ADP_TIME_4 | PHY_RCR1_VCO_COARSE); 238 if (err < 0) 239 return err; 240 err = rtsx_pci_write_phy_register(pcr, PHY_FLD3, 241 PHY_FLD3_TIMER_4 | PHY_FLD3_TIMER_6 | 242 PHY_FLD3_RXDELINK); 243 if (err < 0) 244 return err; 245 246 return rtsx_pci_write_phy_register(pcr, PHY_TUNE, 247 PHY_TUNE_TUNEREF_1_0 | PHY_TUNE_VBGSEL_1252 | 248 PHY_TUNE_SDBUS_33 | PHY_TUNE_TUNED18 | 249 PHY_TUNE_TUNED12 | PHY_TUNE_TUNEA12); 250 } 251 252 static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr) 253 { 254 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02); 255 } 256 257 static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr) 258 { 259 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00); 260 } 261 262 static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr) 263 { 264 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08); 265 } 266 267 static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr) 268 { 269 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00); 270 } 271 272 static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card) 273 { 274 int err; 275 struct rtsx_cr_option *option = &pcr->option; 276 277 if (option->ocp_en) 278 rtsx_pci_enable_ocp(pcr); 279 280 rtsx_pci_init_cmd(pcr); 281 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, 282 SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON); 283 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, 284 LDO3318_PWR_MASK, 0x02); 285 err = rtsx_pci_send_cmd(pcr, 100); 286 if (err < 0) 287 return err; 288 289 msleep(5); 290 291 rtsx_pci_init_cmd(pcr); 292 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, 293 SD_POWER_MASK, SD_VCC_POWER_ON); 294 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, 295 LDO3318_PWR_MASK, 0x06); 296 return rtsx_pci_send_cmd(pcr, 100); 297 } 298 299 static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card) 300 { 301 struct rtsx_cr_option *option = &pcr->option; 302 303 if (option->ocp_en) 304 rtsx_pci_disable_ocp(pcr); 305 306 rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK, SD_POWER_OFF); 307 308 rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0x00); 309 return 0; 310 } 311 312 static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) 313 { 314 int err; 315 u16 append; 316 317 switch (voltage) { 318 case OUTPUT_3V3: 319 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK, 320 PHY_TUNE_VOLTAGE_3V3); 321 if (err < 0) 322 return err; 323 break; 324 case OUTPUT_1V8: 325 append = PHY_TUNE_D18_1V8; 326 if (CHK_PCI_PID(pcr, 0x5249)) { 327 err = rtsx_pci_update_phy(pcr, PHY_BACR, 328 PHY_BACR_BASIC_MASK, 0); 329 if (err < 0) 330 return err; 331 append = PHY_TUNE_D18_1V7; 332 } 333 334 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK, 335 append); 336 if (err < 0) 337 return err; 338 break; 339 default: 340 pcr_dbg(pcr, "unknown output voltage %d\n", voltage); 341 return -EINVAL; 342 } 343 344 /* set pad drive */ 345 rtsx_pci_init_cmd(pcr); 346 rts5249_fill_driving(pcr, voltage); 347 return rtsx_pci_send_cmd(pcr, 100); 348 } 349 350 static void rts5249_set_aspm(struct rtsx_pcr *pcr, bool enable) 351 { 352 struct rtsx_cr_option *option = &pcr->option; 353 u8 val = 0; 354 355 if (pcr->aspm_enabled == enable) 356 return; 357 358 if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) { 359 if (enable) 360 val = pcr->aspm_en; 361 rtsx_pci_update_cfg_byte(pcr, 362 pcr->pcie_cap + PCI_EXP_LNKCTL, 363 ASPM_MASK_NEG, val); 364 } else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) { 365 u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0; 366 367 if (!enable) 368 val = FORCE_ASPM_CTL0; 369 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); 370 } 371 372 pcr->aspm_enabled = enable; 373 } 374 375 static const struct pcr_ops rts5249_pcr_ops = { 376 .fetch_vendor_settings = rtsx_base_fetch_vendor_settings, 377 .extra_init_hw = rts5249_extra_init_hw, 378 .optimize_phy = rts5249_optimize_phy, 379 .turn_on_led = rtsx_base_turn_on_led, 380 .turn_off_led = rtsx_base_turn_off_led, 381 .enable_auto_blink = rtsx_base_enable_auto_blink, 382 .disable_auto_blink = rtsx_base_disable_auto_blink, 383 .card_power_on = rtsx_base_card_power_on, 384 .card_power_off = rtsx_base_card_power_off, 385 .switch_output_voltage = rtsx_base_switch_output_voltage, 386 .force_power_down = rtsx_base_force_power_down, 387 .set_aspm = rts5249_set_aspm, 388 }; 389 390 /* SD Pull Control Enable: 391 * SD_DAT[3:0] ==> pull up 392 * SD_CD ==> pull up 393 * SD_WP ==> pull up 394 * SD_CMD ==> pull up 395 * SD_CLK ==> pull down 396 */ 397 static const u32 rts5249_sd_pull_ctl_enable_tbl[] = { 398 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66), 399 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA), 400 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9), 401 RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA), 402 0, 403 }; 404 405 /* SD Pull Control Disable: 406 * SD_DAT[3:0] ==> pull down 407 * SD_CD ==> pull up 408 * SD_WP ==> pull down 409 * SD_CMD ==> pull down 410 * SD_CLK ==> pull down 411 */ 412 static const u32 rts5249_sd_pull_ctl_disable_tbl[] = { 413 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66), 414 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 415 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5), 416 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55), 417 0, 418 }; 419 420 /* MS Pull Control Enable: 421 * MS CD ==> pull up 422 * others ==> pull down 423 */ 424 static const u32 rts5249_ms_pull_ctl_enable_tbl[] = { 425 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55), 426 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55), 427 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15), 428 0, 429 }; 430 431 /* MS Pull Control Disable: 432 * MS CD ==> pull up 433 * others ==> pull down 434 */ 435 static const u32 rts5249_ms_pull_ctl_disable_tbl[] = { 436 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55), 437 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55), 438 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15), 439 0, 440 }; 441 442 void rts5249_init_params(struct rtsx_pcr *pcr) 443 { 444 struct rtsx_cr_option *option = &(pcr->option); 445 446 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104; 447 pcr->num_slots = 2; 448 pcr->ops = &rts5249_pcr_ops; 449 450 pcr->flags = 0; 451 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT; 452 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B; 453 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B; 454 pcr->aspm_en = ASPM_L1_EN; 455 pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16); 456 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); 457 458 pcr->ic_version = rts5249_get_ic_version(pcr); 459 pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl; 460 pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl; 461 pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl; 462 pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl; 463 464 pcr->reg_pm_ctrl3 = PM_CTRL3; 465 466 option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN 467 | LTR_L1SS_PWR_GATE_EN); 468 option->ltr_en = true; 469 470 /* Init latency of active, idle, L1OFF to 60us, 300us, 3ms */ 471 option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF; 472 option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF; 473 option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF; 474 option->dev_aspm_mode = DEV_ASPM_DYNAMIC; 475 option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF; 476 option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5249_DEF; 477 option->ltr_l1off_snooze_sspwrgate = 478 LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF; 479 } 480 481 static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val) 482 { 483 addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr; 484 485 return __rtsx_pci_write_phy_register(pcr, addr, val); 486 } 487 488 static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val) 489 { 490 addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr; 491 492 return __rtsx_pci_read_phy_register(pcr, addr, val); 493 } 494 495 static int rts524a_optimize_phy(struct rtsx_pcr *pcr) 496 { 497 int err; 498 499 err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 500 D3_DELINK_MODE_EN, 0x00); 501 if (err < 0) 502 return err; 503 504 rtsx_pci_write_phy_register(pcr, PHY_PCR, 505 PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 | 506 PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | PHY_PCR_RSSI_EN); 507 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3, 508 PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY); 509 510 if (is_version(pcr, 0x524A, IC_VER_A)) { 511 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3, 512 PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY); 513 rtsx_pci_write_phy_register(pcr, PHY_SSCCR2, 514 PHY_SSCCR2_PLL_NCODE | PHY_SSCCR2_TIME0 | 515 PHY_SSCCR2_TIME2_WIDTH); 516 rtsx_pci_write_phy_register(pcr, PHY_ANA1A, 517 PHY_ANA1A_TXR_LOOPBACK | PHY_ANA1A_RXT_BIST | 518 PHY_ANA1A_TXR_BIST | PHY_ANA1A_REV); 519 rtsx_pci_write_phy_register(pcr, PHY_ANA1D, 520 PHY_ANA1D_DEBUG_ADDR); 521 rtsx_pci_write_phy_register(pcr, PHY_DIG1E, 522 PHY_DIG1E_REV | PHY_DIG1E_D0_X_D1 | 523 PHY_DIG1E_RX_ON_HOST | PHY_DIG1E_RCLK_REF_HOST | 524 PHY_DIG1E_RCLK_TX_EN_KEEP | 525 PHY_DIG1E_RCLK_TX_TERM_KEEP | 526 PHY_DIG1E_RCLK_RX_EIDLE_ON | PHY_DIG1E_TX_TERM_KEEP | 527 PHY_DIG1E_RX_TERM_KEEP | PHY_DIG1E_TX_EN_KEEP | 528 PHY_DIG1E_RX_EN_KEEP); 529 } 530 531 rtsx_pci_write_phy_register(pcr, PHY_ANA08, 532 PHY_ANA08_RX_EQ_DCGAIN | PHY_ANA08_SEL_RX_EN | 533 PHY_ANA08_RX_EQ_VAL | PHY_ANA08_SCP | PHY_ANA08_SEL_IPI); 534 535 return 0; 536 } 537 538 static int rts524a_extra_init_hw(struct rtsx_pcr *pcr) 539 { 540 rts5249_extra_init_hw(pcr); 541 542 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, 543 FORCE_ASPM_L1_EN, FORCE_ASPM_L1_EN); 544 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0); 545 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN, 546 LDO_VCC_LMT_EN); 547 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL); 548 if (is_version(pcr, 0x524A, IC_VER_A)) { 549 rtsx_pci_write_register(pcr, LDO_DV18_CFG, 550 LDO_DV18_SR_MASK, LDO_DV18_SR_DF); 551 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, 552 LDO_VCC_REF_TUNE_MASK, LDO_VCC_REF_1V2); 553 rtsx_pci_write_register(pcr, LDO_VIO_CFG, 554 LDO_VIO_REF_TUNE_MASK, LDO_VIO_REF_1V2); 555 rtsx_pci_write_register(pcr, LDO_VIO_CFG, 556 LDO_VIO_SR_MASK, LDO_VIO_SR_DF); 557 rtsx_pci_write_register(pcr, LDO_DV12S_CFG, 558 LDO_REF12_TUNE_MASK, LDO_REF12_TUNE_DF); 559 rtsx_pci_write_register(pcr, SD40_LDO_CTL1, 560 SD40_VIO_TUNE_MASK, SD40_VIO_TUNE_1V7); 561 } 562 563 return 0; 564 } 565 566 static void rts5250_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active) 567 { 568 struct rtsx_cr_option *option = &(pcr->option); 569 570 u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR); 571 int card_exist = (interrupt & SD_EXIST) | (interrupt & MS_EXIST); 572 int aspm_L1_1, aspm_L1_2; 573 u8 val = 0; 574 575 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN); 576 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN); 577 578 if (active) { 579 /* Run, latency: 60us */ 580 if (aspm_L1_1) 581 val = option->ltr_l1off_snooze_sspwrgate; 582 } else { 583 /* L1off, latency: 300us */ 584 if (aspm_L1_2) 585 val = option->ltr_l1off_sspwrgate; 586 } 587 588 if (aspm_L1_1 || aspm_L1_2) { 589 if (rtsx_check_dev_flag(pcr, 590 LTR_L1SS_PWR_GATE_CHECK_CARD_EN)) { 591 if (card_exist) 592 val &= ~L1OFF_MBIAS2_EN_5250; 593 else 594 val |= L1OFF_MBIAS2_EN_5250; 595 } 596 } 597 rtsx_set_l1off_sub(pcr, val); 598 } 599 600 static const struct pcr_ops rts524a_pcr_ops = { 601 .write_phy = rts524a_write_phy, 602 .read_phy = rts524a_read_phy, 603 .fetch_vendor_settings = rtsx_base_fetch_vendor_settings, 604 .extra_init_hw = rts524a_extra_init_hw, 605 .optimize_phy = rts524a_optimize_phy, 606 .turn_on_led = rtsx_base_turn_on_led, 607 .turn_off_led = rtsx_base_turn_off_led, 608 .enable_auto_blink = rtsx_base_enable_auto_blink, 609 .disable_auto_blink = rtsx_base_disable_auto_blink, 610 .card_power_on = rtsx_base_card_power_on, 611 .card_power_off = rtsx_base_card_power_off, 612 .switch_output_voltage = rtsx_base_switch_output_voltage, 613 .force_power_down = rtsx_base_force_power_down, 614 .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0, 615 .set_aspm = rts5249_set_aspm, 616 }; 617 618 void rts524a_init_params(struct rtsx_pcr *pcr) 619 { 620 rts5249_init_params(pcr); 621 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF; 622 pcr->option.ltr_l1off_snooze_sspwrgate = 623 LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF; 624 625 pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3; 626 pcr->ops = &rts524a_pcr_ops; 627 628 pcr->option.ocp_en = 1; 629 if (pcr->option.ocp_en) 630 pcr->hw_param.interrupt_en |= SD_OC_INT_EN; 631 pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M; 632 pcr->option.sd_800mA_ocp_thd = RTS524A_OCP_THD_800; 633 634 } 635 636 static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card) 637 { 638 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, 639 LDO_VCC_TUNE_MASK, LDO_VCC_3V3); 640 return rtsx_base_card_power_on(pcr, card); 641 } 642 643 static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) 644 { 645 switch (voltage) { 646 case OUTPUT_3V3: 647 rtsx_pci_write_register(pcr, LDO_CONFIG2, 648 LDO_D3318_MASK, LDO_D3318_33V); 649 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0); 650 break; 651 case OUTPUT_1V8: 652 rtsx_pci_write_register(pcr, LDO_CONFIG2, 653 LDO_D3318_MASK, LDO_D3318_18V); 654 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 655 SD_IO_USING_1V8); 656 break; 657 default: 658 return -EINVAL; 659 } 660 661 rtsx_pci_init_cmd(pcr); 662 rts5249_fill_driving(pcr, voltage); 663 return rtsx_pci_send_cmd(pcr, 100); 664 } 665 666 static int rts525a_optimize_phy(struct rtsx_pcr *pcr) 667 { 668 int err; 669 670 err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 671 D3_DELINK_MODE_EN, 0x00); 672 if (err < 0) 673 return err; 674 675 rtsx_pci_write_phy_register(pcr, _PHY_FLD0, 676 _PHY_FLD0_CLK_REQ_20C | _PHY_FLD0_RX_IDLE_EN | 677 _PHY_FLD0_BIT_ERR_RSTN | _PHY_FLD0_BER_COUNT | 678 _PHY_FLD0_BER_TIMER | _PHY_FLD0_CHECK_EN); 679 680 rtsx_pci_write_phy_register(pcr, _PHY_ANA03, 681 _PHY_ANA03_TIMER_MAX | _PHY_ANA03_OOBS_DEB_EN | 682 _PHY_CMU_DEBUG_EN); 683 684 if (is_version(pcr, 0x525A, IC_VER_A)) 685 rtsx_pci_write_phy_register(pcr, _PHY_REV0, 686 _PHY_REV0_FILTER_OUT | _PHY_REV0_CDR_BYPASS_PFD | 687 _PHY_REV0_CDR_RX_IDLE_BYPASS); 688 689 return 0; 690 } 691 692 static int rts525a_extra_init_hw(struct rtsx_pcr *pcr) 693 { 694 rts5249_extra_init_hw(pcr); 695 696 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL); 697 if (is_version(pcr, 0x525A, IC_VER_A)) { 698 rtsx_pci_write_register(pcr, L1SUB_CONFIG2, 699 L1SUB_AUTO_CFG, L1SUB_AUTO_CFG); 700 rtsx_pci_write_register(pcr, RREF_CFG, 701 RREF_VBGSEL_MASK, RREF_VBGSEL_1V25); 702 rtsx_pci_write_register(pcr, LDO_VIO_CFG, 703 LDO_VIO_TUNE_MASK, LDO_VIO_1V7); 704 rtsx_pci_write_register(pcr, LDO_DV12S_CFG, 705 LDO_D12_TUNE_MASK, LDO_D12_TUNE_DF); 706 rtsx_pci_write_register(pcr, LDO_AV12S_CFG, 707 LDO_AV12S_TUNE_MASK, LDO_AV12S_TUNE_DF); 708 rtsx_pci_write_register(pcr, LDO_VCC_CFG0, 709 LDO_VCC_LMTVTH_MASK, LDO_VCC_LMTVTH_2A); 710 rtsx_pci_write_register(pcr, OOBS_CONFIG, 711 OOBS_AUTOK_DIS | OOBS_VAL_MASK, 0x89); 712 } 713 714 return 0; 715 } 716 717 static const struct pcr_ops rts525a_pcr_ops = { 718 .fetch_vendor_settings = rtsx_base_fetch_vendor_settings, 719 .extra_init_hw = rts525a_extra_init_hw, 720 .optimize_phy = rts525a_optimize_phy, 721 .turn_on_led = rtsx_base_turn_on_led, 722 .turn_off_led = rtsx_base_turn_off_led, 723 .enable_auto_blink = rtsx_base_enable_auto_blink, 724 .disable_auto_blink = rtsx_base_disable_auto_blink, 725 .card_power_on = rts525a_card_power_on, 726 .card_power_off = rtsx_base_card_power_off, 727 .switch_output_voltage = rts525a_switch_output_voltage, 728 .force_power_down = rtsx_base_force_power_down, 729 .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0, 730 .set_aspm = rts5249_set_aspm, 731 }; 732 733 void rts525a_init_params(struct rtsx_pcr *pcr) 734 { 735 rts5249_init_params(pcr); 736 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF; 737 pcr->option.ltr_l1off_snooze_sspwrgate = 738 LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF; 739 740 pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3; 741 pcr->ops = &rts525a_pcr_ops; 742 743 pcr->option.ocp_en = 1; 744 if (pcr->option.ocp_en) 745 pcr->hw_param.interrupt_en |= SD_OC_INT_EN; 746 pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M; 747 pcr->option.sd_800mA_ocp_thd = RTS525A_OCP_THD_800; 748 } 749