1849a9366SRicky Wu /* SPDX-License-Identifier: GPL-2.0-only */ 2849a9366SRicky Wu /* Driver for Realtek PCI-Express card reader 3849a9366SRicky Wu * 4849a9366SRicky Wu * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved. 5849a9366SRicky Wu * 6849a9366SRicky Wu * Author: 7849a9366SRicky Wu * Ricky WU <ricky_wu@realtek.com> 8849a9366SRicky Wu * Rui FENG <rui_feng@realsil.com.cn> 9849a9366SRicky Wu * Wei WANG <wei_wang@realsil.com.cn> 10849a9366SRicky Wu */ 11849a9366SRicky Wu #ifndef RTS5228_H 12849a9366SRicky Wu #define RTS5228_H 13849a9366SRicky Wu 14849a9366SRicky Wu 15849a9366SRicky Wu #define RTS5228_AUTOLOAD_CFG0 0xFF7B 16849a9366SRicky Wu #define RTS5228_AUTOLOAD_CFG1 0xFF7C 17849a9366SRicky Wu #define RTS5228_AUTOLOAD_CFG2 0xFF7D 18849a9366SRicky Wu #define RTS5228_AUTOLOAD_CFG3 0xFF7E 19849a9366SRicky Wu #define RTS5228_AUTOLOAD_CFG4 0xFF7F 20849a9366SRicky Wu 21849a9366SRicky Wu #define RTS5228_REG_VREF 0xFE97 22849a9366SRicky Wu #define RTS5228_PWD_SUSPND_EN (1 << 4) 23849a9366SRicky Wu 24849a9366SRicky Wu #define RTS5228_PAD_H3L1 0xFF79 25849a9366SRicky Wu #define PAD_GPIO_H3L1 (1 << 3) 26849a9366SRicky Wu 27849a9366SRicky Wu /* SSC_CTL2 0xFC12 */ 28849a9366SRicky Wu #define RTS5228_SSC_DEPTH_MASK 0x07 29849a9366SRicky Wu #define RTS5228_SSC_DEPTH_DISALBE 0x00 30849a9366SRicky Wu #define RTS5228_SSC_DEPTH_8M 0x01 31849a9366SRicky Wu #define RTS5228_SSC_DEPTH_4M 0x02 32849a9366SRicky Wu #define RTS5228_SSC_DEPTH_2M 0x03 33849a9366SRicky Wu #define RTS5228_SSC_DEPTH_1M 0x04 34849a9366SRicky Wu #define RTS5228_SSC_DEPTH_512K 0x05 35849a9366SRicky Wu #define RTS5228_SSC_DEPTH_256K 0x06 36849a9366SRicky Wu #define RTS5228_SSC_DEPTH_128K 0x07 37849a9366SRicky Wu 38849a9366SRicky Wu /* DMACTL 0xFE2C */ 39849a9366SRicky Wu #define RTS5228_DMA_PACK_SIZE_MASK 0xF0 40849a9366SRicky Wu 41849a9366SRicky Wu #define RTS5228_REG_LDO12_CFG 0xFF6E 42849a9366SRicky Wu #define RTS5228_LDO12_VO_TUNE_MASK (0x07<<1) 43849a9366SRicky Wu #define RTS5228_LDO12_100 (0x00<<1) 44849a9366SRicky Wu #define RTS5228_LDO12_105 (0x01<<1) 45849a9366SRicky Wu #define RTS5228_LDO12_110 (0x02<<1) 46849a9366SRicky Wu #define RTS5228_LDO12_115 (0x03<<1) 47849a9366SRicky Wu #define RTS5228_LDO12_120 (0x04<<1) 48849a9366SRicky Wu #define RTS5228_LDO12_125 (0x05<<1) 49849a9366SRicky Wu #define RTS5228_LDO12_130 (0x06<<1) 50849a9366SRicky Wu #define RTS5228_LDO12_135 (0x07<<1) 51849a9366SRicky Wu #define RTS5228_REG_PWD_LDO12 (0x01<<0) 52849a9366SRicky Wu 53849a9366SRicky Wu #define RTS5228_REG_LDO12_L12 0xFF6F 54849a9366SRicky Wu #define RTS5228_LDO12_L12_MASK (0x07<<4) 55849a9366SRicky Wu #define RTS5228_LDO12_L12_120 (0x04<<4) 56849a9366SRicky Wu 57849a9366SRicky Wu /* LDO control register */ 58849a9366SRicky Wu #define RTS5228_CARD_PWR_CTL 0xFD50 59849a9366SRicky Wu #define RTS5228_PUPDC (0x01<<5) 60849a9366SRicky Wu 61849a9366SRicky Wu #define RTS5228_LDO1233318_POW_CTL 0xFF70 62849a9366SRicky Wu #define RTS5228_LDO3318_POWERON (0x01<<3) 63849a9366SRicky Wu #define RTS5228_LDO1_POWEROFF (0x00<<0) 64849a9366SRicky Wu #define RTS5228_LDO1_SOFTSTART (0x01<<0) 65849a9366SRicky Wu #define RTS5228_LDO1_FULLON (0x03<<0) 66849a9366SRicky Wu #define RTS5228_LDO1_POWERON_MASK (0x03<<0) 67849a9366SRicky Wu #define RTS5228_LDO_POWERON_MASK (0x0F<<0) 68849a9366SRicky Wu 69849a9366SRicky Wu #define RTS5228_DV3318_CFG 0xFF71 70849a9366SRicky Wu #define RTS5228_DV3318_TUNE_MASK (0x07<<4) 71849a9366SRicky Wu #define RTS5228_DV3318_17 (0x00<<4) 72849a9366SRicky Wu #define RTS5228_DV3318_1V75 (0x01<<4) 73849a9366SRicky Wu #define RTS5228_DV3318_18 (0x02<<4) 74849a9366SRicky Wu #define RTS5228_DV3318_1V85 (0x03<<4) 75849a9366SRicky Wu #define RTS5228_DV3318_19 (0x04<<4) 76849a9366SRicky Wu #define RTS5228_DV3318_33 (0x07<<4) 77849a9366SRicky Wu #define RTS5228_DV3318_SR_MASK (0x03<<2) 78849a9366SRicky Wu #define RTS5228_DV3318_SR_0 (0x00<<2) 79849a9366SRicky Wu #define RTS5228_DV3318_SR_250 (0x01<<2) 80849a9366SRicky Wu #define RTS5228_DV3318_SR_500 (0x02<<2) 81849a9366SRicky Wu #define RTS5228_DV3318_SR_1000 (0x03<<2) 82849a9366SRicky Wu 83849a9366SRicky Wu #define RTS5228_LDO1_CFG0 0xFF72 84849a9366SRicky Wu #define RTS5228_LDO1_OCP_THD_MASK (0x07<<5) 85849a9366SRicky Wu #define RTS5228_LDO1_OCP_EN (0x01<<4) 86849a9366SRicky Wu #define RTS5228_LDO1_OCP_LMT_THD_MASK (0x03<<2) 87849a9366SRicky Wu #define RTS5228_LDO1_OCP_LMT_EN (0x01<<1) 88849a9366SRicky Wu 89849a9366SRicky Wu #define RTS5228_LDO1_OCP_THD_730 (0x00<<5) 90849a9366SRicky Wu #define RTS5228_LDO1_OCP_THD_780 (0x01<<5) 91849a9366SRicky Wu #define RTS5228_LDO1_OCP_THD_860 (0x02<<5) 92849a9366SRicky Wu #define RTS5228_LDO1_OCP_THD_930 (0x03<<5) 93849a9366SRicky Wu #define RTS5228_LDO1_OCP_THD_1000 (0x04<<5) 94849a9366SRicky Wu #define RTS5228_LDO1_OCP_THD_1070 (0x05<<5) 95849a9366SRicky Wu #define RTS5228_LDO1_OCP_THD_1140 (0x06<<5) 96849a9366SRicky Wu #define RTS5228_LDO1_OCP_THD_1220 (0x07<<5) 97849a9366SRicky Wu 98849a9366SRicky Wu #define RTS5228_LDO1_LMT_THD_450 (0x00<<2) 99849a9366SRicky Wu #define RTS5228_LDO1_LMT_THD_1000 (0x01<<2) 100849a9366SRicky Wu #define RTS5228_LDO1_LMT_THD_1500 (0x02<<2) 101849a9366SRicky Wu #define RTS5228_LDO1_LMT_THD_2000 (0x03<<2) 102849a9366SRicky Wu 103849a9366SRicky Wu #define RTS5228_LDO1_CFG1 0xFF73 104849a9366SRicky Wu #define RTS5228_LDO1_SR_TIME_MASK (0x03<<6) 105849a9366SRicky Wu #define RTS5228_LDO1_SR_0_0 (0x00<<6) 106849a9366SRicky Wu #define RTS5228_LDO1_SR_0_25 (0x01<<6) 107849a9366SRicky Wu #define RTS5228_LDO1_SR_0_5 (0x02<<6) 108849a9366SRicky Wu #define RTS5228_LDO1_SR_1_0 (0x03<<6) 109849a9366SRicky Wu #define RTS5228_LDO1_TUNE_MASK (0x07<<1) 110849a9366SRicky Wu #define RTS5228_LDO1_18 (0x05<<1) 111849a9366SRicky Wu #define RTS5228_LDO1_33 (0x07<<1) 112849a9366SRicky Wu #define RTS5228_LDO1_PWD_MASK (0x01<<0) 113849a9366SRicky Wu 114849a9366SRicky Wu #define RTS5228_AUXCLK_GAT_CTL 0xFF74 115849a9366SRicky Wu 116849a9366SRicky Wu #define RTS5228_REG_RREF_CTL_0 0xFF75 117849a9366SRicky Wu #define RTS5228_FORCE_RREF_EXTL (0x01<<7) 118849a9366SRicky Wu #define RTS5228_REG_BG33_MASK (0x07<<0) 119849a9366SRicky Wu #define RTS5228_RREF_12_1V (0x04<<0) 120849a9366SRicky Wu #define RTS5228_RREF_12_3V (0x05<<0) 121849a9366SRicky Wu 122849a9366SRicky Wu #define RTS5228_REG_RREF_CTL_1 0xFF76 123849a9366SRicky Wu 124849a9366SRicky Wu #define RTS5228_REG_RREF_CTL_2 0xFF77 125849a9366SRicky Wu #define RTS5228_TEST_INTL_RREF (0x01<<7) 126849a9366SRicky Wu #define RTS5228_DGLCH_TIME_MASK (0x03<<5) 127849a9366SRicky Wu #define RTS5228_DGLCH_TIME_50 (0x00<<5) 128849a9366SRicky Wu #define RTS5228_DGLCH_TIME_75 (0x01<<5) 129849a9366SRicky Wu #define RTS5228_DGLCH_TIME_100 (0x02<<5) 130849a9366SRicky Wu #define RTS5228_DGLCH_TIME_125 (0x03<<5) 131849a9366SRicky Wu #define RTS5228_REG_REXT_TUNE_MASK (0x1F<<0) 132849a9366SRicky Wu 133849a9366SRicky Wu #define RTS5228_REG_PME_FORCE_CTL 0xFF78 134849a9366SRicky Wu #define FORCE_PM_CONTROL 0x20 135849a9366SRicky Wu #define FORCE_PM_VALUE 0x10 136849a9366SRicky Wu 137849a9366SRicky Wu 138849a9366SRicky Wu /* Single LUN, support SD */ 139849a9366SRicky Wu #define DEFAULT_SINGLE 0 140849a9366SRicky Wu #define SD_LUN 1 141849a9366SRicky Wu 142849a9366SRicky Wu 143849a9366SRicky Wu /* For Change_FPGA_SSCClock Function */ 144849a9366SRicky Wu #define MULTIPLY_BY_1 0x00 145849a9366SRicky Wu #define MULTIPLY_BY_2 0x01 146849a9366SRicky Wu #define MULTIPLY_BY_3 0x02 147849a9366SRicky Wu #define MULTIPLY_BY_4 0x03 148849a9366SRicky Wu #define MULTIPLY_BY_5 0x04 149849a9366SRicky Wu #define MULTIPLY_BY_6 0x05 150849a9366SRicky Wu #define MULTIPLY_BY_7 0x06 151849a9366SRicky Wu #define MULTIPLY_BY_8 0x07 152849a9366SRicky Wu #define MULTIPLY_BY_9 0x08 153849a9366SRicky Wu #define MULTIPLY_BY_10 0x09 154849a9366SRicky Wu 155849a9366SRicky Wu #define DIVIDE_BY_2 0x01 156849a9366SRicky Wu #define DIVIDE_BY_3 0x02 157849a9366SRicky Wu #define DIVIDE_BY_4 0x03 158849a9366SRicky Wu #define DIVIDE_BY_5 0x04 159849a9366SRicky Wu #define DIVIDE_BY_6 0x05 160849a9366SRicky Wu #define DIVIDE_BY_7 0x06 161849a9366SRicky Wu #define DIVIDE_BY_8 0x07 162849a9366SRicky Wu #define DIVIDE_BY_9 0x08 163849a9366SRicky Wu #define DIVIDE_BY_10 0x09 164849a9366SRicky Wu 165849a9366SRicky Wu int rts5228_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, 166849a9366SRicky Wu u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk); 167849a9366SRicky Wu 168849a9366SRicky Wu #endif /* RTS5228_H */ 169