1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Driver for Realtek PCI-Express card reader 3 * 4 * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved. 5 * 6 * Author: 7 * Ricky WU <ricky_wu@realtek.com> 8 * Rui FENG <rui_feng@realsil.com.cn> 9 * Wei WANG <wei_wang@realsil.com.cn> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/delay.h> 14 #include <linux/rtsx_pci.h> 15 16 #include "rts5228.h" 17 #include "rtsx_pcr.h" 18 19 static u8 rts5228_get_ic_version(struct rtsx_pcr *pcr) 20 { 21 u8 val; 22 23 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val); 24 return val & IC_VERSION_MASK; 25 } 26 27 static void rts5228_fill_driving(struct rtsx_pcr *pcr, u8 voltage) 28 { 29 u8 driving_3v3[4][3] = { 30 {0x13, 0x13, 0x13}, 31 {0x96, 0x96, 0x96}, 32 {0x7F, 0x7F, 0x7F}, 33 {0x96, 0x96, 0x96}, 34 }; 35 u8 driving_1v8[4][3] = { 36 {0x99, 0x99, 0x99}, 37 {0xB5, 0xB5, 0xB5}, 38 {0xE6, 0x7E, 0xFE}, 39 {0x6B, 0x6B, 0x6B}, 40 }; 41 u8 (*driving)[3], drive_sel; 42 43 if (voltage == OUTPUT_3V3) { 44 driving = driving_3v3; 45 drive_sel = pcr->sd30_drive_sel_3v3; 46 } else { 47 driving = driving_1v8; 48 drive_sel = pcr->sd30_drive_sel_1v8; 49 } 50 51 rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL, 52 0xFF, driving[drive_sel][0]); 53 54 rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL, 55 0xFF, driving[drive_sel][1]); 56 57 rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL, 58 0xFF, driving[drive_sel][2]); 59 } 60 61 static void rtsx5228_fetch_vendor_settings(struct rtsx_pcr *pcr) 62 { 63 struct pci_dev *pdev = pcr->pci; 64 u32 reg; 65 66 /* 0x724~0x727 */ 67 pci_read_config_dword(pdev, PCR_SETTING_REG1, ®); 68 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg); 69 70 if (!rtsx_vendor_setting_valid(reg)) { 71 pcr_dbg(pcr, "skip fetch vendor setting\n"); 72 return; 73 } 74 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg); 75 pcr->aspm_en = rtsx_reg_to_aspm(reg); 76 77 /* 0x814~0x817 */ 78 pci_read_config_dword(pdev, PCR_SETTING_REG2, ®); 79 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg); 80 81 pcr->rtd3_en = rtsx_reg_to_rtd3(reg); 82 if (rtsx_check_mmc_support(reg)) 83 pcr->extra_caps |= EXTRA_CAPS_NO_MMC; 84 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg); 85 if (rtsx_reg_check_reverse_socket(reg)) 86 pcr->flags |= PCR_REVERSE_SOCKET; 87 } 88 89 static int rts5228_optimize_phy(struct rtsx_pcr *pcr) 90 { 91 return rtsx_pci_write_phy_register(pcr, 0x07, 0x8F40); 92 } 93 94 static void rts5228_force_power_down(struct rtsx_pcr *pcr, u8 pm_state) 95 { 96 /* Set relink_time to 0 */ 97 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0); 98 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0); 99 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 100 RELINK_TIME_MASK, 0); 101 102 if (pm_state == HOST_ENTER_S3) 103 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 104 D3_DELINK_MODE_EN, D3_DELINK_MODE_EN); 105 106 rtsx_pci_write_register(pcr, FPDCTL, 107 SSC_POWER_DOWN, SSC_POWER_DOWN); 108 } 109 110 static int rts5228_enable_auto_blink(struct rtsx_pcr *pcr) 111 { 112 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 113 LED_SHINE_MASK, LED_SHINE_EN); 114 } 115 116 static int rts5228_disable_auto_blink(struct rtsx_pcr *pcr) 117 { 118 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 119 LED_SHINE_MASK, LED_SHINE_DISABLE); 120 } 121 122 static int rts5228_turn_on_led(struct rtsx_pcr *pcr) 123 { 124 return rtsx_pci_write_register(pcr, GPIO_CTL, 125 0x02, 0x02); 126 } 127 128 static int rts5228_turn_off_led(struct rtsx_pcr *pcr) 129 { 130 return rtsx_pci_write_register(pcr, GPIO_CTL, 131 0x02, 0x00); 132 } 133 134 /* SD Pull Control Enable: 135 * SD_DAT[3:0] ==> pull up 136 * SD_CD ==> pull up 137 * SD_WP ==> pull up 138 * SD_CMD ==> pull up 139 * SD_CLK ==> pull down 140 */ 141 static const u32 rts5228_sd_pull_ctl_enable_tbl[] = { 142 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA), 143 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9), 144 0, 145 }; 146 147 /* SD Pull Control Disable: 148 * SD_DAT[3:0] ==> pull down 149 * SD_CD ==> pull up 150 * SD_WP ==> pull down 151 * SD_CMD ==> pull down 152 * SD_CLK ==> pull down 153 */ 154 static const u32 rts5228_sd_pull_ctl_disable_tbl[] = { 155 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 156 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5), 157 0, 158 }; 159 160 static int rts5228_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr) 161 { 162 rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK 163 | SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST); 164 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); 165 rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF, 166 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 167 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); 168 169 return 0; 170 } 171 172 static int rts5228_card_power_on(struct rtsx_pcr *pcr, int card) 173 { 174 struct rtsx_cr_option *option = &pcr->option; 175 176 if (option->ocp_en) 177 rtsx_pci_enable_ocp(pcr); 178 179 rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0, 180 CFG_SD_POW_AUTO_PD, CFG_SD_POW_AUTO_PD); 181 182 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG1, 183 RTS5228_LDO1_TUNE_MASK, RTS5228_LDO1_33); 184 185 rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL, 186 RTS5228_LDO1_POWERON_MASK, RTS5228_LDO1_SOFTSTART); 187 mdelay(2); 188 rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL, 189 RTS5228_LDO1_POWERON_MASK, RTS5228_LDO1_FULLON); 190 191 192 rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL, 193 RTS5228_LDO3318_POWERON, RTS5228_LDO3318_POWERON); 194 195 msleep(20); 196 197 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); 198 199 /* Initialize SD_CFG1 register */ 200 rtsx_pci_write_register(pcr, SD_CFG1, 0xFF, 201 SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1BIT); 202 203 rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL, 204 0xFF, SD20_RX_POS_EDGE); 205 rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0); 206 rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR, 207 SD_STOP | SD_CLR_ERR); 208 209 /* Reset SD_CFG3 register */ 210 rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0); 211 rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG, 212 SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 | 213 SD30_CLK_STOP_CFG0, 0); 214 215 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 || 216 pcr->extra_caps & EXTRA_CAPS_SD_SDR104) 217 rts5228_sd_set_sample_push_timing_sd30(pcr); 218 219 return 0; 220 } 221 222 static int rts5228_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) 223 { 224 int err; 225 u16 val = 0; 226 227 rtsx_pci_write_register(pcr, RTS5228_CARD_PWR_CTL, 228 RTS5228_PUPDC, RTS5228_PUPDC); 229 230 switch (voltage) { 231 case OUTPUT_3V3: 232 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val); 233 val |= PHY_TUNE_SDBUS_33; 234 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val); 235 if (err < 0) 236 return err; 237 238 rtsx_pci_write_register(pcr, RTS5228_DV3318_CFG, 239 RTS5228_DV3318_TUNE_MASK, RTS5228_DV3318_33); 240 rtsx_pci_write_register(pcr, SD_PAD_CTL, 241 SD_IO_USING_1V8, 0); 242 break; 243 case OUTPUT_1V8: 244 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val); 245 val &= ~PHY_TUNE_SDBUS_33; 246 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val); 247 if (err < 0) 248 return err; 249 250 rtsx_pci_write_register(pcr, RTS5228_DV3318_CFG, 251 RTS5228_DV3318_TUNE_MASK, RTS5228_DV3318_18); 252 rtsx_pci_write_register(pcr, SD_PAD_CTL, 253 SD_IO_USING_1V8, SD_IO_USING_1V8); 254 break; 255 default: 256 return -EINVAL; 257 } 258 259 /* set pad drive */ 260 rts5228_fill_driving(pcr, voltage); 261 262 return 0; 263 } 264 265 static void rts5228_stop_cmd(struct rtsx_pcr *pcr) 266 { 267 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD); 268 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA); 269 rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0, 270 RTS5260_DMA_RST | RTS5260_ADMA3_RST, 271 RTS5260_DMA_RST | RTS5260_ADMA3_RST); 272 rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH); 273 } 274 275 static void rts5228_card_before_power_off(struct rtsx_pcr *pcr) 276 { 277 rts5228_stop_cmd(pcr); 278 rts5228_switch_output_voltage(pcr, OUTPUT_3V3); 279 } 280 281 static void rts5228_enable_ocp(struct rtsx_pcr *pcr) 282 { 283 u8 val = 0; 284 285 val = SD_OCP_INT_EN | SD_DETECT_EN; 286 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val); 287 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0, 288 RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN, 289 RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN); 290 } 291 292 static void rts5228_disable_ocp(struct rtsx_pcr *pcr) 293 { 294 u8 mask = 0; 295 296 mask = SD_OCP_INT_EN | SD_DETECT_EN; 297 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); 298 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0, 299 RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN, 0); 300 } 301 302 static int rts5228_card_power_off(struct rtsx_pcr *pcr, int card) 303 { 304 int err = 0; 305 306 rts5228_card_before_power_off(pcr); 307 err = rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL, 308 RTS5228_LDO_POWERON_MASK, 0); 309 rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0, CFG_SD_POW_AUTO_PD, 0); 310 311 if (pcr->option.ocp_en) 312 rtsx_pci_disable_ocp(pcr); 313 314 return err; 315 } 316 317 static void rts5228_init_ocp(struct rtsx_pcr *pcr) 318 { 319 struct rtsx_cr_option *option = &pcr->option; 320 321 if (option->ocp_en) { 322 u8 mask, val; 323 324 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0, 325 RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN, 326 RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN); 327 328 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0, 329 RTS5228_LDO1_OCP_THD_MASK, option->sd_800mA_ocp_thd); 330 331 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0, 332 RTS5228_LDO1_OCP_LMT_THD_MASK, 333 RTS5228_LDO1_LMT_THD_1500); 334 335 rtsx_pci_read_register(pcr, RTS5228_LDO1_CFG0, &val); 336 337 mask = SD_OCP_GLITCH_MASK; 338 val = pcr->hw_param.ocp_glitch; 339 rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val); 340 341 rts5228_enable_ocp(pcr); 342 343 } else { 344 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0, 345 RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN, 0); 346 } 347 } 348 349 static void rts5228_clear_ocpstat(struct rtsx_pcr *pcr) 350 { 351 u8 mask = 0; 352 u8 val = 0; 353 354 mask = SD_OCP_INT_CLR | SD_OC_CLR; 355 val = SD_OCP_INT_CLR | SD_OC_CLR; 356 357 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val); 358 359 udelay(1000); 360 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); 361 362 } 363 364 static void rts5228_process_ocp(struct rtsx_pcr *pcr) 365 { 366 if (!pcr->option.ocp_en) 367 return; 368 369 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat); 370 371 if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) { 372 rts5228_clear_ocpstat(pcr); 373 rts5228_card_power_off(pcr, RTSX_SD_CARD); 374 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0); 375 pcr->ocp_stat = 0; 376 } 377 378 } 379 380 static void rts5228_init_from_cfg(struct rtsx_pcr *pcr) 381 { 382 struct pci_dev *pdev = pcr->pci; 383 int l1ss; 384 u32 lval; 385 struct rtsx_cr_option *option = &pcr->option; 386 387 l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); 388 if (!l1ss) 389 return; 390 391 pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval); 392 393 if (0 == (lval & 0x0F)) 394 rtsx_pci_enable_oobs_polling(pcr); 395 else 396 rtsx_pci_disable_oobs_polling(pcr); 397 398 if (lval & PCI_L1SS_CTL1_ASPM_L1_1) 399 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); 400 else 401 rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN); 402 403 if (lval & PCI_L1SS_CTL1_ASPM_L1_2) 404 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); 405 else 406 rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN); 407 408 if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) 409 rtsx_set_dev_flag(pcr, PM_L1_1_EN); 410 else 411 rtsx_clear_dev_flag(pcr, PM_L1_1_EN); 412 413 if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) 414 rtsx_set_dev_flag(pcr, PM_L1_2_EN); 415 else 416 rtsx_clear_dev_flag(pcr, PM_L1_2_EN); 417 418 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0); 419 if (option->ltr_en) { 420 u16 val; 421 422 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val); 423 if (val & PCI_EXP_DEVCTL2_LTR_EN) { 424 option->ltr_enabled = true; 425 option->ltr_active = true; 426 rtsx_set_ltr_latency(pcr, option->ltr_active_latency); 427 } else { 428 option->ltr_enabled = false; 429 } 430 } 431 432 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN 433 | PM_L1_1_EN | PM_L1_2_EN)) 434 option->force_clkreq_0 = false; 435 else 436 option->force_clkreq_0 = true; 437 } 438 439 static int rts5228_extra_init_hw(struct rtsx_pcr *pcr) 440 { 441 struct rtsx_cr_option *option = &pcr->option; 442 443 rtsx_pci_write_register(pcr, RTS5228_AUTOLOAD_CFG1, 444 CD_RESUME_EN_MASK, CD_RESUME_EN_MASK); 445 446 rts5228_init_from_cfg(pcr); 447 448 rtsx_pci_write_register(pcr, L1SUB_CONFIG1, 449 AUX_CLK_ACTIVE_SEL_MASK, MAC_CKSW_DONE); 450 rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0); 451 452 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, 453 FUNC_FORCE_UPME_XMT_DBG, FUNC_FORCE_UPME_XMT_DBG); 454 455 rtsx_pci_write_register(pcr, PCLK_CTL, 456 PCLK_MODE_SEL, PCLK_MODE_SEL); 457 458 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0); 459 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, CLK_PM_EN, CLK_PM_EN); 460 461 /* LED shine disabled, set initial shine cycle period */ 462 rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02); 463 464 /* Configure driving */ 465 rts5228_fill_driving(pcr, OUTPUT_3V3); 466 467 if (pcr->flags & PCR_REVERSE_SOCKET) 468 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30); 469 else 470 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00); 471 472 /* 473 * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced 474 * to drive low, and we forcibly request clock. 475 */ 476 if (option->force_clkreq_0) 477 rtsx_pci_write_register(pcr, PETXCFG, 478 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); 479 else 480 rtsx_pci_write_register(pcr, PETXCFG, 481 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); 482 483 rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB); 484 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00); 485 rtsx_pci_write_register(pcr, RTS5228_REG_PME_FORCE_CTL, 486 FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL); 487 488 return 0; 489 } 490 491 static void rts5228_enable_aspm(struct rtsx_pcr *pcr, bool enable) 492 { 493 u8 mask, val; 494 495 if (pcr->aspm_enabled == enable) 496 return; 497 498 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1; 499 val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1; 500 val |= (pcr->aspm_en & 0x02); 501 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); 502 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, 503 PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en); 504 pcr->aspm_enabled = enable; 505 } 506 507 static void rts5228_disable_aspm(struct rtsx_pcr *pcr, bool enable) 508 { 509 u8 mask, val; 510 511 if (pcr->aspm_enabled == enable) 512 return; 513 514 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, 515 PCI_EXP_LNKCTL_ASPMC, 0); 516 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1; 517 val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1; 518 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); 519 rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); 520 mdelay(10); 521 pcr->aspm_enabled = enable; 522 } 523 524 static void rts5228_set_aspm(struct rtsx_pcr *pcr, bool enable) 525 { 526 if (enable) 527 rts5228_enable_aspm(pcr, true); 528 else 529 rts5228_disable_aspm(pcr, false); 530 } 531 532 static void rts5228_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active) 533 { 534 struct rtsx_cr_option *option = &pcr->option; 535 int aspm_L1_1, aspm_L1_2; 536 u8 val = 0; 537 538 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN); 539 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN); 540 541 if (active) { 542 /* run, latency: 60us */ 543 if (aspm_L1_1) 544 val = option->ltr_l1off_snooze_sspwrgate; 545 } else { 546 /* l1off, latency: 300us */ 547 if (aspm_L1_2) 548 val = option->ltr_l1off_sspwrgate; 549 } 550 551 rtsx_set_l1off_sub(pcr, val); 552 } 553 554 static const struct pcr_ops rts5228_pcr_ops = { 555 .fetch_vendor_settings = rtsx5228_fetch_vendor_settings, 556 .turn_on_led = rts5228_turn_on_led, 557 .turn_off_led = rts5228_turn_off_led, 558 .extra_init_hw = rts5228_extra_init_hw, 559 .enable_auto_blink = rts5228_enable_auto_blink, 560 .disable_auto_blink = rts5228_disable_auto_blink, 561 .card_power_on = rts5228_card_power_on, 562 .card_power_off = rts5228_card_power_off, 563 .switch_output_voltage = rts5228_switch_output_voltage, 564 .force_power_down = rts5228_force_power_down, 565 .stop_cmd = rts5228_stop_cmd, 566 .set_aspm = rts5228_set_aspm, 567 .set_l1off_cfg_sub_d0 = rts5228_set_l1off_cfg_sub_d0, 568 .enable_ocp = rts5228_enable_ocp, 569 .disable_ocp = rts5228_disable_ocp, 570 .init_ocp = rts5228_init_ocp, 571 .process_ocp = rts5228_process_ocp, 572 .clear_ocpstat = rts5228_clear_ocpstat, 573 .optimize_phy = rts5228_optimize_phy, 574 }; 575 576 577 static inline u8 double_ssc_depth(u8 depth) 578 { 579 return ((depth > 1) ? (depth - 1) : depth); 580 } 581 582 int rts5228_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, 583 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk) 584 { 585 int err, clk; 586 u16 n; 587 u8 clk_divider, mcu_cnt, div; 588 static const u8 depth[] = { 589 [RTSX_SSC_DEPTH_4M] = RTS5228_SSC_DEPTH_4M, 590 [RTSX_SSC_DEPTH_2M] = RTS5228_SSC_DEPTH_2M, 591 [RTSX_SSC_DEPTH_1M] = RTS5228_SSC_DEPTH_1M, 592 [RTSX_SSC_DEPTH_500K] = RTS5228_SSC_DEPTH_512K, 593 }; 594 595 if (initial_mode) { 596 /* We use 250k(around) here, in initial stage */ 597 clk_divider = SD_CLK_DIVIDE_128; 598 card_clock = 30000000; 599 } else { 600 clk_divider = SD_CLK_DIVIDE_0; 601 } 602 err = rtsx_pci_write_register(pcr, SD_CFG1, 603 SD_CLK_DIVIDE_MASK, clk_divider); 604 if (err < 0) 605 return err; 606 607 card_clock /= 1000000; 608 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock); 609 610 clk = card_clock; 611 if (!initial_mode && double_clk) 612 clk = card_clock * 2; 613 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n", 614 clk, pcr->cur_clock); 615 616 if (clk == pcr->cur_clock) 617 return 0; 618 619 if (pcr->ops->conv_clk_and_div_n) 620 n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N); 621 else 622 n = clk - 4; 623 if ((clk <= 4) || (n > 396)) 624 return -EINVAL; 625 626 mcu_cnt = 125/clk + 3; 627 if (mcu_cnt > 15) 628 mcu_cnt = 15; 629 630 div = CLK_DIV_1; 631 while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) { 632 if (pcr->ops->conv_clk_and_div_n) { 633 int dbl_clk = pcr->ops->conv_clk_and_div_n(n, 634 DIV_N_TO_CLK) * 2; 635 n = pcr->ops->conv_clk_and_div_n(dbl_clk, 636 CLK_TO_DIV_N); 637 } else { 638 n = (n + 4) * 2 - 4; 639 } 640 div++; 641 } 642 643 n = (n / 2) - 1; 644 pcr_dbg(pcr, "n = %d, div = %d\n", n, div); 645 646 ssc_depth = depth[ssc_depth]; 647 if (double_clk) 648 ssc_depth = double_ssc_depth(ssc_depth); 649 650 if (ssc_depth) { 651 if (div == CLK_DIV_2) { 652 if (ssc_depth > 1) 653 ssc_depth -= 1; 654 else 655 ssc_depth = RTS5228_SSC_DEPTH_8M; 656 } else if (div == CLK_DIV_4) { 657 if (ssc_depth > 2) 658 ssc_depth -= 2; 659 else 660 ssc_depth = RTS5228_SSC_DEPTH_8M; 661 } else if (div == CLK_DIV_8) { 662 if (ssc_depth > 3) 663 ssc_depth -= 3; 664 else 665 ssc_depth = RTS5228_SSC_DEPTH_8M; 666 } 667 } else { 668 ssc_depth = 0; 669 } 670 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth); 671 672 rtsx_pci_init_cmd(pcr); 673 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 674 CLK_LOW_FREQ, CLK_LOW_FREQ); 675 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 676 0xFF, (div << 4) | mcu_cnt); 677 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); 678 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 679 SSC_DEPTH_MASK, ssc_depth); 680 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n); 681 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB); 682 if (vpclk) { 683 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, 684 PHASE_NOT_RESET, 0); 685 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL, 686 PHASE_NOT_RESET, 0); 687 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, 688 PHASE_NOT_RESET, PHASE_NOT_RESET); 689 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL, 690 PHASE_NOT_RESET, PHASE_NOT_RESET); 691 } 692 693 err = rtsx_pci_send_cmd(pcr, 2000); 694 if (err < 0) 695 return err; 696 697 /* Wait SSC clock stable */ 698 udelay(SSC_CLOCK_STABLE_WAIT); 699 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); 700 if (err < 0) 701 return err; 702 703 pcr->cur_clock = clk; 704 return 0; 705 706 } 707 708 void rts5228_init_params(struct rtsx_pcr *pcr) 709 { 710 struct rtsx_cr_option *option = &pcr->option; 711 struct rtsx_hw_param *hw_param = &pcr->hw_param; 712 713 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104; 714 pcr->num_slots = 1; 715 pcr->ops = &rts5228_pcr_ops; 716 717 pcr->flags = 0; 718 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT; 719 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B; 720 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B; 721 pcr->aspm_en = ASPM_L1_EN; 722 pcr->tx_initial_phase = SET_CLOCK_PHASE(28, 27, 11); 723 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); 724 725 pcr->ic_version = rts5228_get_ic_version(pcr); 726 pcr->sd_pull_ctl_enable_tbl = rts5228_sd_pull_ctl_enable_tbl; 727 pcr->sd_pull_ctl_disable_tbl = rts5228_sd_pull_ctl_disable_tbl; 728 729 pcr->reg_pm_ctrl3 = RTS5228_AUTOLOAD_CFG3; 730 731 option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN 732 | LTR_L1SS_PWR_GATE_EN); 733 option->ltr_en = true; 734 735 /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */ 736 option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF; 737 option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF; 738 option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF; 739 option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF; 740 option->ltr_l1off_sspwrgate = 0x7F; 741 option->ltr_l1off_snooze_sspwrgate = 0x78; 742 743 option->ocp_en = 1; 744 hw_param->interrupt_en |= SD_OC_INT_EN; 745 hw_param->ocp_glitch = SD_OCP_GLITCH_800U; 746 option->sd_800mA_ocp_thd = RTS5228_LDO1_OCP_THD_930; 747 } 748