1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Driver for Realtek PCI-Express card reader
3  *
4  * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.
5  *
6  * Author:
7  *   Ricky WU <ricky_wu@realtek.com>
8  *   Rui FENG <rui_feng@realsil.com.cn>
9  *   Wei WANG <wei_wang@realsil.com.cn>
10  */
11 
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/rtsx_pci.h>
15 
16 #include "rts5228.h"
17 #include "rtsx_pcr.h"
18 
19 static u8 rts5228_get_ic_version(struct rtsx_pcr *pcr)
20 {
21 	u8 val;
22 
23 	rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
24 	return val & IC_VERSION_MASK;
25 }
26 
27 static void rts5228_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
28 {
29 	u8 driving_3v3[4][3] = {
30 		{0x13, 0x13, 0x13},
31 		{0x96, 0x96, 0x96},
32 		{0x7F, 0x7F, 0x7F},
33 		{0x96, 0x96, 0x96},
34 	};
35 	u8 driving_1v8[4][3] = {
36 		{0x99, 0x99, 0x99},
37 		{0xB5, 0xB5, 0xB5},
38 		{0xE6, 0x7E, 0xFE},
39 		{0x6B, 0x6B, 0x6B},
40 	};
41 	u8 (*driving)[3], drive_sel;
42 
43 	if (voltage == OUTPUT_3V3) {
44 		driving = driving_3v3;
45 		drive_sel = pcr->sd30_drive_sel_3v3;
46 	} else {
47 		driving = driving_1v8;
48 		drive_sel = pcr->sd30_drive_sel_1v8;
49 	}
50 
51 	rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
52 			 0xFF, driving[drive_sel][0]);
53 
54 	rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
55 			 0xFF, driving[drive_sel][1]);
56 
57 	rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
58 			 0xFF, driving[drive_sel][2]);
59 }
60 
61 static void rtsx5228_fetch_vendor_settings(struct rtsx_pcr *pcr)
62 {
63 	struct pci_dev *pdev = pcr->pci;
64 	u32 reg;
65 
66 	/* 0x724~0x727 */
67 	pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
68 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
69 
70 	if (!rtsx_vendor_setting_valid(reg)) {
71 		pcr_dbg(pcr, "skip fetch vendor setting\n");
72 		return;
73 	}
74 	pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
75 	pcr->aspm_en = rtsx_reg_to_aspm(reg);
76 
77 	/* 0x814~0x817 */
78 	pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
79 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
80 
81 	pcr->rtd3_en = rtsx_reg_to_rtd3(reg);
82 	if (rtsx_check_mmc_support(reg))
83 		pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
84 	pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
85 	if (rtsx_reg_check_reverse_socket(reg))
86 		pcr->flags |= PCR_REVERSE_SOCKET;
87 }
88 
89 static int rts5228_optimize_phy(struct rtsx_pcr *pcr)
90 {
91 	return rtsx_pci_write_phy_register(pcr, 0x07, 0x8F40);
92 }
93 
94 static void rts5228_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
95 {
96 	/* Set relink_time to 0 */
97 	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
98 	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
99 	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
100 				RELINK_TIME_MASK, 0);
101 
102 	rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
103 			D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
104 
105 	rtsx_pci_write_register(pcr, FPDCTL,
106 		SSC_POWER_DOWN, SSC_POWER_DOWN);
107 }
108 
109 static int rts5228_enable_auto_blink(struct rtsx_pcr *pcr)
110 {
111 	return rtsx_pci_write_register(pcr, OLT_LED_CTL,
112 		LED_SHINE_MASK, LED_SHINE_EN);
113 }
114 
115 static int rts5228_disable_auto_blink(struct rtsx_pcr *pcr)
116 {
117 	return rtsx_pci_write_register(pcr, OLT_LED_CTL,
118 		LED_SHINE_MASK, LED_SHINE_DISABLE);
119 }
120 
121 static int rts5228_turn_on_led(struct rtsx_pcr *pcr)
122 {
123 	return rtsx_pci_write_register(pcr, GPIO_CTL,
124 		0x02, 0x02);
125 }
126 
127 static int rts5228_turn_off_led(struct rtsx_pcr *pcr)
128 {
129 	return rtsx_pci_write_register(pcr, GPIO_CTL,
130 		0x02, 0x00);
131 }
132 
133 /* SD Pull Control Enable:
134  *     SD_DAT[3:0] ==> pull up
135  *     SD_CD       ==> pull up
136  *     SD_WP       ==> pull up
137  *     SD_CMD      ==> pull up
138  *     SD_CLK      ==> pull down
139  */
140 static const u32 rts5228_sd_pull_ctl_enable_tbl[] = {
141 	RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
142 	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
143 	0,
144 };
145 
146 /* SD Pull Control Disable:
147  *     SD_DAT[3:0] ==> pull down
148  *     SD_CD       ==> pull up
149  *     SD_WP       ==> pull down
150  *     SD_CMD      ==> pull down
151  *     SD_CLK      ==> pull down
152  */
153 static const u32 rts5228_sd_pull_ctl_disable_tbl[] = {
154 	RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
155 	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
156 	0,
157 };
158 
159 static int rts5228_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr)
160 {
161 	rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK
162 		| SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
163 	rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
164 	rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,
165 			CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
166 	rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
167 
168 	return 0;
169 }
170 
171 static int rts5228_card_power_on(struct rtsx_pcr *pcr, int card)
172 {
173 	struct rtsx_cr_option *option = &pcr->option;
174 
175 	if (option->ocp_en)
176 		rtsx_pci_enable_ocp(pcr);
177 
178 	rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0,
179 			CFG_SD_POW_AUTO_PD, CFG_SD_POW_AUTO_PD);
180 
181 	rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG1,
182 			RTS5228_LDO1_TUNE_MASK, RTS5228_LDO1_33);
183 
184 	rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
185 			RTS5228_LDO1_POWERON_MASK, RTS5228_LDO1_SOFTSTART);
186 	mdelay(2);
187 	rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
188 			RTS5228_LDO1_POWERON_MASK, RTS5228_LDO1_FULLON);
189 
190 
191 	rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
192 			RTS5228_LDO3318_POWERON, RTS5228_LDO3318_POWERON);
193 
194 	msleep(20);
195 
196 	rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
197 
198 	/* Initialize SD_CFG1 register */
199 	rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,
200 			SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1BIT);
201 
202 	rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL,
203 			0xFF, SD20_RX_POS_EDGE);
204 	rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);
205 	rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR,
206 			SD_STOP | SD_CLR_ERR);
207 
208 	/* Reset SD_CFG3 register */
209 	rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);
210 	rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,
211 			SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 |
212 			SD30_CLK_STOP_CFG0, 0);
213 
214 	if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||
215 	    pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
216 		rts5228_sd_set_sample_push_timing_sd30(pcr);
217 
218 	return 0;
219 }
220 
221 static int rts5228_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
222 {
223 	int err;
224 	u16 val = 0;
225 
226 	rtsx_pci_write_register(pcr, RTS5228_CARD_PWR_CTL,
227 			RTS5228_PUPDC, RTS5228_PUPDC);
228 
229 	switch (voltage) {
230 	case OUTPUT_3V3:
231 		rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
232 		val |= PHY_TUNE_SDBUS_33;
233 		err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
234 		if (err < 0)
235 			return err;
236 
237 		rtsx_pci_write_register(pcr, RTS5228_DV3318_CFG,
238 				RTS5228_DV3318_TUNE_MASK, RTS5228_DV3318_33);
239 		rtsx_pci_write_register(pcr, SD_PAD_CTL,
240 				SD_IO_USING_1V8, 0);
241 		break;
242 	case OUTPUT_1V8:
243 		rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
244 		val &= ~PHY_TUNE_SDBUS_33;
245 		err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
246 		if (err < 0)
247 			return err;
248 
249 		rtsx_pci_write_register(pcr, RTS5228_DV3318_CFG,
250 				RTS5228_DV3318_TUNE_MASK, RTS5228_DV3318_18);
251 		rtsx_pci_write_register(pcr, SD_PAD_CTL,
252 				SD_IO_USING_1V8, SD_IO_USING_1V8);
253 		break;
254 	default:
255 		return -EINVAL;
256 	}
257 
258 	/* set pad drive */
259 	rts5228_fill_driving(pcr, voltage);
260 
261 	return 0;
262 }
263 
264 static void rts5228_stop_cmd(struct rtsx_pcr *pcr)
265 {
266 	rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
267 	rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
268 	rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0,
269 				RTS5260_DMA_RST | RTS5260_ADMA3_RST,
270 				RTS5260_DMA_RST | RTS5260_ADMA3_RST);
271 	rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH);
272 }
273 
274 static void rts5228_card_before_power_off(struct rtsx_pcr *pcr)
275 {
276 	rts5228_stop_cmd(pcr);
277 	rts5228_switch_output_voltage(pcr, OUTPUT_3V3);
278 }
279 
280 static void rts5228_enable_ocp(struct rtsx_pcr *pcr)
281 {
282 	u8 val = 0;
283 
284 	val = SD_OCP_INT_EN | SD_DETECT_EN;
285 	rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
286 	rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
287 			RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN,
288 			RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN);
289 }
290 
291 static void rts5228_disable_ocp(struct rtsx_pcr *pcr)
292 {
293 	u8 mask = 0;
294 
295 	mask = SD_OCP_INT_EN | SD_DETECT_EN;
296 	rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
297 	rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
298 			RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN, 0);
299 }
300 
301 static int rts5228_card_power_off(struct rtsx_pcr *pcr, int card)
302 {
303 	int err = 0;
304 
305 	rts5228_card_before_power_off(pcr);
306 	err = rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
307 				RTS5228_LDO_POWERON_MASK, 0);
308 	rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0, CFG_SD_POW_AUTO_PD, 0);
309 
310 	if (pcr->option.ocp_en)
311 		rtsx_pci_disable_ocp(pcr);
312 
313 	return err;
314 }
315 
316 static void rts5228_init_ocp(struct rtsx_pcr *pcr)
317 {
318 	struct rtsx_cr_option *option = &pcr->option;
319 
320 	if (option->ocp_en) {
321 		u8 mask, val;
322 
323 		rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
324 			RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN,
325 			RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN);
326 
327 		rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
328 			RTS5228_LDO1_OCP_THD_MASK, option->sd_800mA_ocp_thd);
329 
330 		rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
331 			RTS5228_LDO1_OCP_LMT_THD_MASK,
332 			RTS5228_LDO1_LMT_THD_1500);
333 
334 		rtsx_pci_read_register(pcr, RTS5228_LDO1_CFG0, &val);
335 
336 		mask = SD_OCP_GLITCH_MASK;
337 		val = pcr->hw_param.ocp_glitch;
338 		rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
339 
340 		rts5228_enable_ocp(pcr);
341 
342 	} else {
343 		rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
344 			RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN, 0);
345 	}
346 }
347 
348 static void rts5228_clear_ocpstat(struct rtsx_pcr *pcr)
349 {
350 	u8 mask = 0;
351 	u8 val = 0;
352 
353 	mask = SD_OCP_INT_CLR | SD_OC_CLR;
354 	val = SD_OCP_INT_CLR | SD_OC_CLR;
355 
356 	rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
357 
358 	udelay(1000);
359 	rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
360 
361 }
362 
363 static void rts5228_process_ocp(struct rtsx_pcr *pcr)
364 {
365 	if (!pcr->option.ocp_en)
366 		return;
367 
368 	rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
369 
370 	if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
371 		rts5228_clear_ocpstat(pcr);
372 		rts5228_card_power_off(pcr, RTSX_SD_CARD);
373 		rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
374 		pcr->ocp_stat = 0;
375 	}
376 
377 }
378 
379 static void rts5228_init_from_cfg(struct rtsx_pcr *pcr)
380 {
381 	struct pci_dev *pdev = pcr->pci;
382 	int l1ss;
383 	u32 lval;
384 	struct rtsx_cr_option *option = &pcr->option;
385 
386 	l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
387 	if (!l1ss)
388 		return;
389 
390 	pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
391 
392 	if (0 == (lval & 0x0F))
393 		rtsx_pci_enable_oobs_polling(pcr);
394 	else
395 		rtsx_pci_disable_oobs_polling(pcr);
396 
397 	if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
398 		rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
399 	else
400 		rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
401 
402 	if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
403 		rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
404 	else
405 		rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
406 
407 	if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
408 		rtsx_set_dev_flag(pcr, PM_L1_1_EN);
409 	else
410 		rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
411 
412 	if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
413 		rtsx_set_dev_flag(pcr, PM_L1_2_EN);
414 	else
415 		rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
416 
417 	rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
418 	if (option->ltr_en) {
419 		u16 val;
420 
421 		pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);
422 		if (val & PCI_EXP_DEVCTL2_LTR_EN) {
423 			option->ltr_enabled = true;
424 			option->ltr_active = true;
425 			rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
426 		} else {
427 			option->ltr_enabled = false;
428 		}
429 	}
430 
431 	if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
432 				| PM_L1_1_EN | PM_L1_2_EN))
433 		option->force_clkreq_0 = false;
434 	else
435 		option->force_clkreq_0 = true;
436 }
437 
438 static int rts5228_extra_init_hw(struct rtsx_pcr *pcr)
439 {
440 	struct rtsx_cr_option *option = &pcr->option;
441 
442 	rtsx_pci_write_register(pcr, RTS5228_AUTOLOAD_CFG1,
443 			CD_RESUME_EN_MASK, CD_RESUME_EN_MASK);
444 
445 	rts5228_init_from_cfg(pcr);
446 
447 	rtsx_pci_write_register(pcr, L1SUB_CONFIG1,
448 			AUX_CLK_ACTIVE_SEL_MASK, MAC_CKSW_DONE);
449 	rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0);
450 
451 	rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
452 			FUNC_FORCE_UPME_XMT_DBG, FUNC_FORCE_UPME_XMT_DBG);
453 
454 	rtsx_pci_write_register(pcr, PCLK_CTL,
455 			PCLK_MODE_SEL, PCLK_MODE_SEL);
456 
457 	rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
458 	rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, CLK_PM_EN, CLK_PM_EN);
459 
460 	/* LED shine disabled, set initial shine cycle period */
461 	rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02);
462 
463 	/* Configure driving */
464 	rts5228_fill_driving(pcr, OUTPUT_3V3);
465 
466 	if (pcr->flags & PCR_REVERSE_SOCKET)
467 		rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30);
468 	else
469 		rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00);
470 
471 	/*
472 	 * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
473 	 * to drive low, and we forcibly request clock.
474 	 */
475 	if (option->force_clkreq_0)
476 		rtsx_pci_write_register(pcr, PETXCFG,
477 				 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
478 	else
479 		rtsx_pci_write_register(pcr, PETXCFG,
480 				 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
481 
482 	rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB);
483 	rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
484 	rtsx_pci_write_register(pcr, RTS5228_REG_PME_FORCE_CTL,
485 			FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
486 
487 	return 0;
488 }
489 
490 static void rts5228_enable_aspm(struct rtsx_pcr *pcr, bool enable)
491 {
492 	u8 mask, val;
493 
494 	if (pcr->aspm_enabled == enable)
495 		return;
496 
497 	mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
498 	val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
499 	val |= (pcr->aspm_en & 0x02);
500 	rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
501 	pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
502 					   PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en);
503 	pcr->aspm_enabled = enable;
504 }
505 
506 static void rts5228_disable_aspm(struct rtsx_pcr *pcr, bool enable)
507 {
508 	u8 mask, val;
509 
510 	if (pcr->aspm_enabled == enable)
511 		return;
512 
513 	pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
514 					   PCI_EXP_LNKCTL_ASPMC, 0);
515 	mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
516 	val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
517 	rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
518 	rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
519 	mdelay(10);
520 	pcr->aspm_enabled = enable;
521 }
522 
523 static void rts5228_set_aspm(struct rtsx_pcr *pcr, bool enable)
524 {
525 	if (enable)
526 		rts5228_enable_aspm(pcr, true);
527 	else
528 		rts5228_disable_aspm(pcr, false);
529 }
530 
531 static void rts5228_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
532 {
533 	struct rtsx_cr_option *option = &pcr->option;
534 	int aspm_L1_1, aspm_L1_2;
535 	u8 val = 0;
536 
537 	aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
538 	aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
539 
540 	if (active) {
541 		/* run, latency: 60us */
542 		if (aspm_L1_1)
543 			val = option->ltr_l1off_snooze_sspwrgate;
544 	} else {
545 		/* l1off, latency: 300us */
546 		if (aspm_L1_2)
547 			val = option->ltr_l1off_sspwrgate;
548 	}
549 
550 	rtsx_set_l1off_sub(pcr, val);
551 }
552 
553 static const struct pcr_ops rts5228_pcr_ops = {
554 	.fetch_vendor_settings = rtsx5228_fetch_vendor_settings,
555 	.turn_on_led = rts5228_turn_on_led,
556 	.turn_off_led = rts5228_turn_off_led,
557 	.extra_init_hw = rts5228_extra_init_hw,
558 	.enable_auto_blink = rts5228_enable_auto_blink,
559 	.disable_auto_blink = rts5228_disable_auto_blink,
560 	.card_power_on = rts5228_card_power_on,
561 	.card_power_off = rts5228_card_power_off,
562 	.switch_output_voltage = rts5228_switch_output_voltage,
563 	.force_power_down = rts5228_force_power_down,
564 	.stop_cmd = rts5228_stop_cmd,
565 	.set_aspm = rts5228_set_aspm,
566 	.set_l1off_cfg_sub_d0 = rts5228_set_l1off_cfg_sub_d0,
567 	.enable_ocp = rts5228_enable_ocp,
568 	.disable_ocp = rts5228_disable_ocp,
569 	.init_ocp = rts5228_init_ocp,
570 	.process_ocp = rts5228_process_ocp,
571 	.clear_ocpstat = rts5228_clear_ocpstat,
572 	.optimize_phy = rts5228_optimize_phy,
573 };
574 
575 
576 static inline u8 double_ssc_depth(u8 depth)
577 {
578 	return ((depth > 1) ? (depth - 1) : depth);
579 }
580 
581 int rts5228_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
582 		u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
583 {
584 	int err, clk;
585 	u16 n;
586 	u8 clk_divider, mcu_cnt, div;
587 	static const u8 depth[] = {
588 		[RTSX_SSC_DEPTH_4M] = RTS5228_SSC_DEPTH_4M,
589 		[RTSX_SSC_DEPTH_2M] = RTS5228_SSC_DEPTH_2M,
590 		[RTSX_SSC_DEPTH_1M] = RTS5228_SSC_DEPTH_1M,
591 		[RTSX_SSC_DEPTH_500K] = RTS5228_SSC_DEPTH_512K,
592 	};
593 
594 	if (initial_mode) {
595 		/* We use 250k(around) here, in initial stage */
596 		clk_divider = SD_CLK_DIVIDE_128;
597 		card_clock = 30000000;
598 	} else {
599 		clk_divider = SD_CLK_DIVIDE_0;
600 	}
601 	err = rtsx_pci_write_register(pcr, SD_CFG1,
602 			SD_CLK_DIVIDE_MASK, clk_divider);
603 	if (err < 0)
604 		return err;
605 
606 	card_clock /= 1000000;
607 	pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
608 
609 	clk = card_clock;
610 	if (!initial_mode && double_clk)
611 		clk = card_clock * 2;
612 	pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
613 		clk, pcr->cur_clock);
614 
615 	if (clk == pcr->cur_clock)
616 		return 0;
617 
618 	if (pcr->ops->conv_clk_and_div_n)
619 		n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
620 	else
621 		n = clk - 4;
622 	if ((clk <= 4) || (n > 396))
623 		return -EINVAL;
624 
625 	mcu_cnt = 125/clk + 3;
626 	if (mcu_cnt > 15)
627 		mcu_cnt = 15;
628 
629 	div = CLK_DIV_1;
630 	while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) {
631 		if (pcr->ops->conv_clk_and_div_n) {
632 			int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
633 					DIV_N_TO_CLK) * 2;
634 			n = pcr->ops->conv_clk_and_div_n(dbl_clk,
635 					CLK_TO_DIV_N);
636 		} else {
637 			n = (n + 4) * 2 - 4;
638 		}
639 		div++;
640 	}
641 
642 	n = (n / 2) - 1;
643 	pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
644 
645 	ssc_depth = depth[ssc_depth];
646 	if (double_clk)
647 		ssc_depth = double_ssc_depth(ssc_depth);
648 
649 	if (ssc_depth) {
650 		if (div == CLK_DIV_2) {
651 			if (ssc_depth > 1)
652 				ssc_depth -= 1;
653 			else
654 				ssc_depth = RTS5228_SSC_DEPTH_8M;
655 		} else if (div == CLK_DIV_4) {
656 			if (ssc_depth > 2)
657 				ssc_depth -= 2;
658 			else
659 				ssc_depth = RTS5228_SSC_DEPTH_8M;
660 		} else if (div == CLK_DIV_8) {
661 			if (ssc_depth > 3)
662 				ssc_depth -= 3;
663 			else
664 				ssc_depth = RTS5228_SSC_DEPTH_8M;
665 		}
666 	} else {
667 		ssc_depth = 0;
668 	}
669 	pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
670 
671 	rtsx_pci_init_cmd(pcr);
672 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
673 				CLK_LOW_FREQ, CLK_LOW_FREQ);
674 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
675 			0xFF, (div << 4) | mcu_cnt);
676 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
677 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
678 			SSC_DEPTH_MASK, ssc_depth);
679 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
680 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
681 	if (vpclk) {
682 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
683 				PHASE_NOT_RESET, 0);
684 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
685 				PHASE_NOT_RESET, 0);
686 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
687 				PHASE_NOT_RESET, PHASE_NOT_RESET);
688 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
689 				PHASE_NOT_RESET, PHASE_NOT_RESET);
690 	}
691 
692 	err = rtsx_pci_send_cmd(pcr, 2000);
693 	if (err < 0)
694 		return err;
695 
696 	/* Wait SSC clock stable */
697 	udelay(SSC_CLOCK_STABLE_WAIT);
698 	err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
699 	if (err < 0)
700 		return err;
701 
702 	pcr->cur_clock = clk;
703 	return 0;
704 
705 }
706 
707 void rts5228_init_params(struct rtsx_pcr *pcr)
708 {
709 	struct rtsx_cr_option *option = &pcr->option;
710 	struct rtsx_hw_param *hw_param = &pcr->hw_param;
711 
712 	pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
713 	pcr->num_slots = 1;
714 	pcr->ops = &rts5228_pcr_ops;
715 
716 	pcr->flags = 0;
717 	pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
718 	pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
719 	pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
720 	pcr->aspm_en = ASPM_L1_EN;
721 	pcr->aspm_mode = ASPM_MODE_REG;
722 	pcr->tx_initial_phase = SET_CLOCK_PHASE(28, 27, 11);
723 	pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
724 
725 	pcr->ic_version = rts5228_get_ic_version(pcr);
726 	pcr->sd_pull_ctl_enable_tbl = rts5228_sd_pull_ctl_enable_tbl;
727 	pcr->sd_pull_ctl_disable_tbl = rts5228_sd_pull_ctl_disable_tbl;
728 
729 	pcr->reg_pm_ctrl3 = RTS5228_AUTOLOAD_CFG3;
730 
731 	option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
732 				| LTR_L1SS_PWR_GATE_EN);
733 	option->ltr_en = true;
734 
735 	/* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
736 	option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
737 	option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
738 	option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
739 	option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
740 	option->ltr_l1off_sspwrgate = 0x7F;
741 	option->ltr_l1off_snooze_sspwrgate = 0x78;
742 
743 	option->ocp_en = 1;
744 	hw_param->interrupt_en |= SD_OC_INT_EN;
745 	hw_param->ocp_glitch =  SD_OCP_GLITCH_800U;
746 	option->sd_800mA_ocp_thd =  RTS5228_LDO1_OCP_THD_930;
747 }
748