1aaf4989bSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
2e455b69dSRui Feng /* Driver for Realtek PCI-Express card reader
3e455b69dSRui Feng *
4e455b69dSRui Feng * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5e455b69dSRui Feng *
6e455b69dSRui Feng * Author:
7e455b69dSRui Feng * Wei WANG <wei_wang@realsil.com.cn>
8e455b69dSRui Feng */
9e455b69dSRui Feng
10e455b69dSRui Feng #include <linux/module.h>
11e455b69dSRui Feng #include <linux/delay.h>
12e455b69dSRui Feng #include <linux/rtsx_pci.h>
13e455b69dSRui Feng
14e455b69dSRui Feng #include "rtsx_pcr.h"
15e455b69dSRui Feng
rts5209_get_ic_version(struct rtsx_pcr * pcr)16e455b69dSRui Feng static u8 rts5209_get_ic_version(struct rtsx_pcr *pcr)
17e455b69dSRui Feng {
18e455b69dSRui Feng u8 val;
19e455b69dSRui Feng
20e455b69dSRui Feng val = rtsx_pci_readb(pcr, 0x1C);
21e455b69dSRui Feng return val & 0x0F;
22e455b69dSRui Feng }
23e455b69dSRui Feng
rts5209_fetch_vendor_settings(struct rtsx_pcr * pcr)24e455b69dSRui Feng static void rts5209_fetch_vendor_settings(struct rtsx_pcr *pcr)
25e455b69dSRui Feng {
2622bf3251SBjorn Helgaas struct pci_dev *pdev = pcr->pci;
27e455b69dSRui Feng u32 reg;
28e455b69dSRui Feng
2922bf3251SBjorn Helgaas pci_read_config_dword(pdev, PCR_SETTING_REG1, ®);
30e455b69dSRui Feng pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
31e455b69dSRui Feng
32e455b69dSRui Feng if (rts5209_vendor_setting1_valid(reg)) {
33e455b69dSRui Feng if (rts5209_reg_check_ms_pmos(reg))
34e455b69dSRui Feng pcr->flags |= PCR_MS_PMOS;
35e455b69dSRui Feng pcr->aspm_en = rts5209_reg_to_aspm(reg);
36e455b69dSRui Feng }
37e455b69dSRui Feng
3822bf3251SBjorn Helgaas pci_read_config_dword(pdev, PCR_SETTING_REG2, ®);
39e455b69dSRui Feng pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
40e455b69dSRui Feng
41e455b69dSRui Feng if (rts5209_vendor_setting2_valid(reg)) {
42e455b69dSRui Feng pcr->sd30_drive_sel_1v8 =
43e455b69dSRui Feng rts5209_reg_to_sd30_drive_sel_1v8(reg);
44e455b69dSRui Feng pcr->sd30_drive_sel_3v3 =
45e455b69dSRui Feng rts5209_reg_to_sd30_drive_sel_3v3(reg);
46e455b69dSRui Feng pcr->card_drive_sel = rts5209_reg_to_card_drive_sel(reg);
47e455b69dSRui Feng }
48e455b69dSRui Feng }
49e455b69dSRui Feng
rts5209_force_power_down(struct rtsx_pcr * pcr,u8 pm_state,bool runtime)50*71732e24SKai-Heng Feng static void rts5209_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
51e455b69dSRui Feng {
52e455b69dSRui Feng rtsx_pci_write_register(pcr, FPDCTL, 0x07, 0x07);
53e455b69dSRui Feng }
54e455b69dSRui Feng
rts5209_extra_init_hw(struct rtsx_pcr * pcr)55e455b69dSRui Feng static int rts5209_extra_init_hw(struct rtsx_pcr *pcr)
56e455b69dSRui Feng {
57e455b69dSRui Feng rtsx_pci_init_cmd(pcr);
58e455b69dSRui Feng
59e455b69dSRui Feng /* Turn off LED */
60e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_GPIO, 0xFF, 0x03);
61e455b69dSRui Feng /* Reset ASPM state to default value */
62e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
63e455b69dSRui Feng /* Force CLKREQ# PIN to drive 0 to request clock */
64e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08);
65e455b69dSRui Feng /* Configure GPIO as output */
66e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_GPIO_DIR, 0xFF, 0x03);
67e455b69dSRui Feng /* Configure driving */
68e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
69e455b69dSRui Feng 0xFF, pcr->sd30_drive_sel_3v3);
70e455b69dSRui Feng
71e455b69dSRui Feng return rtsx_pci_send_cmd(pcr, 100);
72e455b69dSRui Feng }
73e455b69dSRui Feng
rts5209_optimize_phy(struct rtsx_pcr * pcr)74e455b69dSRui Feng static int rts5209_optimize_phy(struct rtsx_pcr *pcr)
75e455b69dSRui Feng {
76e455b69dSRui Feng return rtsx_pci_write_phy_register(pcr, 0x00, 0xB966);
77e455b69dSRui Feng }
78e455b69dSRui Feng
rts5209_turn_on_led(struct rtsx_pcr * pcr)79e455b69dSRui Feng static int rts5209_turn_on_led(struct rtsx_pcr *pcr)
80e455b69dSRui Feng {
81e455b69dSRui Feng return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x00);
82e455b69dSRui Feng }
83e455b69dSRui Feng
rts5209_turn_off_led(struct rtsx_pcr * pcr)84e455b69dSRui Feng static int rts5209_turn_off_led(struct rtsx_pcr *pcr)
85e455b69dSRui Feng {
86e455b69dSRui Feng return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x01);
87e455b69dSRui Feng }
88e455b69dSRui Feng
rts5209_enable_auto_blink(struct rtsx_pcr * pcr)89e455b69dSRui Feng static int rts5209_enable_auto_blink(struct rtsx_pcr *pcr)
90e455b69dSRui Feng {
91e455b69dSRui Feng return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0xFF, 0x0D);
92e455b69dSRui Feng }
93e455b69dSRui Feng
rts5209_disable_auto_blink(struct rtsx_pcr * pcr)94e455b69dSRui Feng static int rts5209_disable_auto_blink(struct rtsx_pcr *pcr)
95e455b69dSRui Feng {
96e455b69dSRui Feng return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0x08, 0x00);
97e455b69dSRui Feng }
98e455b69dSRui Feng
rts5209_card_power_on(struct rtsx_pcr * pcr,int card)99e455b69dSRui Feng static int rts5209_card_power_on(struct rtsx_pcr *pcr, int card)
100e455b69dSRui Feng {
101e455b69dSRui Feng int err;
102e455b69dSRui Feng u8 pwr_mask, partial_pwr_on, pwr_on;
103e455b69dSRui Feng
104e455b69dSRui Feng pwr_mask = SD_POWER_MASK;
105e455b69dSRui Feng partial_pwr_on = SD_PARTIAL_POWER_ON;
106e455b69dSRui Feng pwr_on = SD_POWER_ON;
107e455b69dSRui Feng
108e455b69dSRui Feng if ((pcr->flags & PCR_MS_PMOS) && (card == RTSX_MS_CARD)) {
109e455b69dSRui Feng pwr_mask = MS_POWER_MASK;
110e455b69dSRui Feng partial_pwr_on = MS_PARTIAL_POWER_ON;
111e455b69dSRui Feng pwr_on = MS_POWER_ON;
112e455b69dSRui Feng }
113e455b69dSRui Feng
114e455b69dSRui Feng rtsx_pci_init_cmd(pcr);
115e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
116e455b69dSRui Feng pwr_mask, partial_pwr_on);
117e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
118e455b69dSRui Feng LDO3318_PWR_MASK, 0x04);
119e455b69dSRui Feng err = rtsx_pci_send_cmd(pcr, 100);
120e455b69dSRui Feng if (err < 0)
121e455b69dSRui Feng return err;
122e455b69dSRui Feng
123e455b69dSRui Feng /* To avoid too large in-rush current */
124e455b69dSRui Feng udelay(150);
125e455b69dSRui Feng
126e455b69dSRui Feng rtsx_pci_init_cmd(pcr);
127e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, pwr_mask, pwr_on);
128e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
129e455b69dSRui Feng LDO3318_PWR_MASK, 0x00);
130e455b69dSRui Feng return rtsx_pci_send_cmd(pcr, 100);
131e455b69dSRui Feng }
132e455b69dSRui Feng
rts5209_card_power_off(struct rtsx_pcr * pcr,int card)133e455b69dSRui Feng static int rts5209_card_power_off(struct rtsx_pcr *pcr, int card)
134e455b69dSRui Feng {
135e455b69dSRui Feng u8 pwr_mask, pwr_off;
136e455b69dSRui Feng
137e455b69dSRui Feng pwr_mask = SD_POWER_MASK;
138e455b69dSRui Feng pwr_off = SD_POWER_OFF;
139e455b69dSRui Feng
140e455b69dSRui Feng if ((pcr->flags & PCR_MS_PMOS) && (card == RTSX_MS_CARD)) {
141e455b69dSRui Feng pwr_mask = MS_POWER_MASK;
142e455b69dSRui Feng pwr_off = MS_POWER_OFF;
143e455b69dSRui Feng }
144e455b69dSRui Feng
145e455b69dSRui Feng rtsx_pci_init_cmd(pcr);
146e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
147e455b69dSRui Feng pwr_mask | PMOS_STRG_MASK, pwr_off | PMOS_STRG_400mA);
148e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
149e455b69dSRui Feng LDO3318_PWR_MASK, 0x06);
150e455b69dSRui Feng return rtsx_pci_send_cmd(pcr, 100);
151e455b69dSRui Feng }
152e455b69dSRui Feng
rts5209_switch_output_voltage(struct rtsx_pcr * pcr,u8 voltage)153e455b69dSRui Feng static int rts5209_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
154e455b69dSRui Feng {
155e455b69dSRui Feng int err;
156e455b69dSRui Feng
157e455b69dSRui Feng if (voltage == OUTPUT_3V3) {
158e455b69dSRui Feng err = rtsx_pci_write_register(pcr,
159e455b69dSRui Feng SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_3v3);
160e455b69dSRui Feng if (err < 0)
161e455b69dSRui Feng return err;
162e455b69dSRui Feng err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
163e455b69dSRui Feng if (err < 0)
164e455b69dSRui Feng return err;
165e455b69dSRui Feng } else if (voltage == OUTPUT_1V8) {
166e455b69dSRui Feng err = rtsx_pci_write_register(pcr,
167e455b69dSRui Feng SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_1v8);
168e455b69dSRui Feng if (err < 0)
169e455b69dSRui Feng return err;
170e455b69dSRui Feng err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C40 | 0x24);
171e455b69dSRui Feng if (err < 0)
172e455b69dSRui Feng return err;
173e455b69dSRui Feng } else {
174e455b69dSRui Feng return -EINVAL;
175e455b69dSRui Feng }
176e455b69dSRui Feng
177e455b69dSRui Feng return 0;
178e455b69dSRui Feng }
179e455b69dSRui Feng
180e455b69dSRui Feng static const struct pcr_ops rts5209_pcr_ops = {
181e455b69dSRui Feng .fetch_vendor_settings = rts5209_fetch_vendor_settings,
182e455b69dSRui Feng .extra_init_hw = rts5209_extra_init_hw,
183e455b69dSRui Feng .optimize_phy = rts5209_optimize_phy,
184e455b69dSRui Feng .turn_on_led = rts5209_turn_on_led,
185e455b69dSRui Feng .turn_off_led = rts5209_turn_off_led,
186e455b69dSRui Feng .enable_auto_blink = rts5209_enable_auto_blink,
187e455b69dSRui Feng .disable_auto_blink = rts5209_disable_auto_blink,
188e455b69dSRui Feng .card_power_on = rts5209_card_power_on,
189e455b69dSRui Feng .card_power_off = rts5209_card_power_off,
190e455b69dSRui Feng .switch_output_voltage = rts5209_switch_output_voltage,
191e455b69dSRui Feng .cd_deglitch = NULL,
192e455b69dSRui Feng .conv_clk_and_div_n = NULL,
193e455b69dSRui Feng .force_power_down = rts5209_force_power_down,
194e455b69dSRui Feng };
195e455b69dSRui Feng
196e455b69dSRui Feng /* SD Pull Control Enable:
197e455b69dSRui Feng * SD_DAT[3:0] ==> pull up
198e455b69dSRui Feng * SD_CD ==> pull up
199e455b69dSRui Feng * SD_WP ==> pull up
200e455b69dSRui Feng * SD_CMD ==> pull up
201e455b69dSRui Feng * SD_CLK ==> pull down
202e455b69dSRui Feng */
203e455b69dSRui Feng static const u32 rts5209_sd_pull_ctl_enable_tbl[] = {
204e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL1, 0xAA),
205e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
206e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
207e455b69dSRui Feng 0,
208e455b69dSRui Feng };
209e455b69dSRui Feng
210e455b69dSRui Feng /* SD Pull Control Disable:
211e455b69dSRui Feng * SD_DAT[3:0] ==> pull down
212e455b69dSRui Feng * SD_CD ==> pull up
213e455b69dSRui Feng * SD_WP ==> pull down
214e455b69dSRui Feng * SD_CMD ==> pull down
215e455b69dSRui Feng * SD_CLK ==> pull down
216e455b69dSRui Feng */
217e455b69dSRui Feng static const u32 rts5209_sd_pull_ctl_disable_tbl[] = {
218e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL1, 0x55),
219e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
220e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
221e455b69dSRui Feng 0,
222e455b69dSRui Feng };
223e455b69dSRui Feng
224e455b69dSRui Feng /* MS Pull Control Enable:
225e455b69dSRui Feng * MS CD ==> pull up
226e455b69dSRui Feng * others ==> pull down
227e455b69dSRui Feng */
228e455b69dSRui Feng static const u32 rts5209_ms_pull_ctl_enable_tbl[] = {
229e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
230e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
231e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
232e455b69dSRui Feng 0,
233e455b69dSRui Feng };
234e455b69dSRui Feng
235e455b69dSRui Feng /* MS Pull Control Disable:
236e455b69dSRui Feng * MS CD ==> pull up
237e455b69dSRui Feng * others ==> pull down
238e455b69dSRui Feng */
239e455b69dSRui Feng static const u32 rts5209_ms_pull_ctl_disable_tbl[] = {
240e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
241e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
242e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
243e455b69dSRui Feng 0,
244e455b69dSRui Feng };
245e455b69dSRui Feng
rts5209_init_params(struct rtsx_pcr * pcr)246e455b69dSRui Feng void rts5209_init_params(struct rtsx_pcr *pcr)
247e455b69dSRui Feng {
248e455b69dSRui Feng pcr->extra_caps = EXTRA_CAPS_SD_SDR50 |
249e455b69dSRui Feng EXTRA_CAPS_SD_SDR104 | EXTRA_CAPS_MMC_8BIT;
250e455b69dSRui Feng pcr->num_slots = 2;
251e455b69dSRui Feng pcr->ops = &rts5209_pcr_ops;
252e455b69dSRui Feng
253e455b69dSRui Feng pcr->flags = 0;
254e455b69dSRui Feng pcr->card_drive_sel = RTS5209_CARD_DRIVE_DEFAULT;
255e455b69dSRui Feng pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B;
256e455b69dSRui Feng pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D;
257e455b69dSRui Feng pcr->aspm_en = ASPM_L1_EN;
2583df4fce7SRicky Wu pcr->aspm_mode = ASPM_MODE_CFG;
259e455b69dSRui Feng pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 16);
260e455b69dSRui Feng pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
261e455b69dSRui Feng
262e455b69dSRui Feng pcr->ic_version = rts5209_get_ic_version(pcr);
263e455b69dSRui Feng pcr->sd_pull_ctl_enable_tbl = rts5209_sd_pull_ctl_enable_tbl;
264e455b69dSRui Feng pcr->sd_pull_ctl_disable_tbl = rts5209_sd_pull_ctl_disable_tbl;
265e455b69dSRui Feng pcr->ms_pull_ctl_enable_tbl = rts5209_ms_pull_ctl_enable_tbl;
266e455b69dSRui Feng pcr->ms_pull_ctl_disable_tbl = rts5209_ms_pull_ctl_disable_tbl;
267e455b69dSRui Feng }
268