1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Driver for Realtek PCI-Express card reader 3 * 4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 5 * 6 * Author: 7 * Wei WANG <wei_wang@realsil.com.cn> 8 * Roger Tseng <rogerable@realtek.com> 9 */ 10 11 #include <linux/module.h> 12 #include <linux/bitops.h> 13 #include <linux/delay.h> 14 #include <linux/rtsx_pci.h> 15 16 #include "rtsx_pcr.h" 17 18 static u8 rtl8411_get_ic_version(struct rtsx_pcr *pcr) 19 { 20 u8 val; 21 22 rtsx_pci_read_register(pcr, SYS_VER, &val); 23 return val & 0x0F; 24 } 25 26 static int rtl8411b_is_qfn48(struct rtsx_pcr *pcr) 27 { 28 u8 val = 0; 29 30 rtsx_pci_read_register(pcr, RTL8411B_PACKAGE_MODE, &val); 31 32 if (val & 0x2) 33 return 1; 34 else 35 return 0; 36 } 37 38 static void rtl8411_fetch_vendor_settings(struct rtsx_pcr *pcr) 39 { 40 u32 reg1 = 0; 41 u8 reg3 = 0; 42 43 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®1); 44 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg1); 45 46 if (!rtsx_vendor_setting_valid(reg1)) 47 return; 48 49 pcr->aspm_en = rtsx_reg_to_aspm(reg1); 50 pcr->sd30_drive_sel_1v8 = 51 map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg1)); 52 pcr->card_drive_sel &= 0x3F; 53 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg1); 54 55 rtsx_pci_read_config_byte(pcr, PCR_SETTING_REG3, ®3); 56 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG3, reg3); 57 pcr->sd30_drive_sel_3v3 = rtl8411_reg_to_sd30_drive_sel_3v3(reg3); 58 } 59 60 static void rtl8411b_fetch_vendor_settings(struct rtsx_pcr *pcr) 61 { 62 u32 reg = 0; 63 64 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®); 65 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg); 66 67 if (!rtsx_vendor_setting_valid(reg)) 68 return; 69 70 pcr->aspm_en = rtsx_reg_to_aspm(reg); 71 pcr->sd30_drive_sel_1v8 = 72 map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg)); 73 pcr->sd30_drive_sel_3v3 = 74 map_sd_drive(rtl8411b_reg_to_sd30_drive_sel_3v3(reg)); 75 } 76 77 static void rtl8411_force_power_down(struct rtsx_pcr *pcr, u8 pm_state) 78 { 79 rtsx_pci_write_register(pcr, FPDCTL, 0x07, 0x07); 80 } 81 82 static int rtl8411_extra_init_hw(struct rtsx_pcr *pcr) 83 { 84 rtsx_pci_init_cmd(pcr); 85 86 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL, 87 0xFF, pcr->sd30_drive_sel_3v3); 88 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CD_PAD_CTL, 89 CD_DISABLE_MASK | CD_AUTO_DISABLE, CD_ENABLE); 90 91 return rtsx_pci_send_cmd(pcr, 100); 92 } 93 94 static int rtl8411b_extra_init_hw(struct rtsx_pcr *pcr) 95 { 96 rtsx_pci_init_cmd(pcr); 97 98 if (rtl8411b_is_qfn48(pcr)) 99 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 100 CARD_PULL_CTL3, 0xFF, 0xF5); 101 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL, 102 0xFF, pcr->sd30_drive_sel_3v3); 103 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CD_PAD_CTL, 104 CD_DISABLE_MASK | CD_AUTO_DISABLE, CD_ENABLE); 105 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, FUNC_FORCE_CTL, 106 0x06, 0x00); 107 108 return rtsx_pci_send_cmd(pcr, 100); 109 } 110 111 static int rtl8411_turn_on_led(struct rtsx_pcr *pcr) 112 { 113 return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x00); 114 } 115 116 static int rtl8411_turn_off_led(struct rtsx_pcr *pcr) 117 { 118 return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x01); 119 } 120 121 static int rtl8411_enable_auto_blink(struct rtsx_pcr *pcr) 122 { 123 return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0xFF, 0x0D); 124 } 125 126 static int rtl8411_disable_auto_blink(struct rtsx_pcr *pcr) 127 { 128 return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0x08, 0x00); 129 } 130 131 static int rtl8411_card_power_on(struct rtsx_pcr *pcr, int card) 132 { 133 int err; 134 135 rtsx_pci_init_cmd(pcr); 136 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, 137 BPP_POWER_MASK, BPP_POWER_5_PERCENT_ON); 138 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_CTL, 139 BPP_LDO_POWB, BPP_LDO_SUSPEND); 140 err = rtsx_pci_send_cmd(pcr, 100); 141 if (err < 0) 142 return err; 143 144 /* To avoid too large in-rush current */ 145 udelay(150); 146 147 err = rtsx_pci_write_register(pcr, CARD_PWR_CTL, 148 BPP_POWER_MASK, BPP_POWER_10_PERCENT_ON); 149 if (err < 0) 150 return err; 151 152 udelay(150); 153 154 err = rtsx_pci_write_register(pcr, CARD_PWR_CTL, 155 BPP_POWER_MASK, BPP_POWER_15_PERCENT_ON); 156 if (err < 0) 157 return err; 158 159 udelay(150); 160 161 err = rtsx_pci_write_register(pcr, CARD_PWR_CTL, 162 BPP_POWER_MASK, BPP_POWER_ON); 163 if (err < 0) 164 return err; 165 166 return rtsx_pci_write_register(pcr, LDO_CTL, BPP_LDO_POWB, BPP_LDO_ON); 167 } 168 169 static int rtl8411_card_power_off(struct rtsx_pcr *pcr, int card) 170 { 171 int err; 172 173 err = rtsx_pci_write_register(pcr, CARD_PWR_CTL, 174 BPP_POWER_MASK, BPP_POWER_OFF); 175 if (err < 0) 176 return err; 177 178 return rtsx_pci_write_register(pcr, LDO_CTL, 179 BPP_LDO_POWB, BPP_LDO_SUSPEND); 180 } 181 182 static int rtl8411_do_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage, 183 int bpp_tuned18_shift, int bpp_asic_1v8) 184 { 185 u8 mask, val; 186 int err; 187 188 mask = (BPP_REG_TUNED18 << bpp_tuned18_shift) | BPP_PAD_MASK; 189 if (voltage == OUTPUT_3V3) { 190 err = rtsx_pci_write_register(pcr, 191 SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_3v3); 192 if (err < 0) 193 return err; 194 val = (BPP_ASIC_3V3 << bpp_tuned18_shift) | BPP_PAD_3V3; 195 } else if (voltage == OUTPUT_1V8) { 196 err = rtsx_pci_write_register(pcr, 197 SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_1v8); 198 if (err < 0) 199 return err; 200 val = (bpp_asic_1v8 << bpp_tuned18_shift) | BPP_PAD_1V8; 201 } else { 202 return -EINVAL; 203 } 204 205 return rtsx_pci_write_register(pcr, LDO_CTL, mask, val); 206 } 207 208 static int rtl8411_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) 209 { 210 return rtl8411_do_switch_output_voltage(pcr, voltage, 211 BPP_TUNED18_SHIFT_8411, BPP_ASIC_1V8); 212 } 213 214 static int rtl8402_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) 215 { 216 return rtl8411_do_switch_output_voltage(pcr, voltage, 217 BPP_TUNED18_SHIFT_8402, BPP_ASIC_2V0); 218 } 219 220 static unsigned int rtl8411_cd_deglitch(struct rtsx_pcr *pcr) 221 { 222 unsigned int card_exist; 223 224 card_exist = rtsx_pci_readl(pcr, RTSX_BIPR); 225 card_exist &= CARD_EXIST; 226 if (!card_exist) { 227 /* Enable card CD */ 228 rtsx_pci_write_register(pcr, CD_PAD_CTL, 229 CD_DISABLE_MASK, CD_ENABLE); 230 /* Enable card interrupt */ 231 rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x00); 232 return 0; 233 } 234 235 if (hweight32(card_exist) > 1) { 236 rtsx_pci_write_register(pcr, CARD_PWR_CTL, 237 BPP_POWER_MASK, BPP_POWER_5_PERCENT_ON); 238 msleep(100); 239 240 card_exist = rtsx_pci_readl(pcr, RTSX_BIPR); 241 if (card_exist & MS_EXIST) 242 card_exist = MS_EXIST; 243 else if (card_exist & SD_EXIST) 244 card_exist = SD_EXIST; 245 else 246 card_exist = 0; 247 248 rtsx_pci_write_register(pcr, CARD_PWR_CTL, 249 BPP_POWER_MASK, BPP_POWER_OFF); 250 251 pcr_dbg(pcr, "After CD deglitch, card_exist = 0x%x\n", 252 card_exist); 253 } 254 255 if (card_exist & MS_EXIST) { 256 /* Disable SD interrupt */ 257 rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x40); 258 rtsx_pci_write_register(pcr, CD_PAD_CTL, 259 CD_DISABLE_MASK, MS_CD_EN_ONLY); 260 } else if (card_exist & SD_EXIST) { 261 /* Disable MS interrupt */ 262 rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x80); 263 rtsx_pci_write_register(pcr, CD_PAD_CTL, 264 CD_DISABLE_MASK, SD_CD_EN_ONLY); 265 } 266 267 return card_exist; 268 } 269 270 static int rtl8411_conv_clk_and_div_n(int input, int dir) 271 { 272 int output; 273 274 if (dir == CLK_TO_DIV_N) 275 output = input * 4 / 5 - 2; 276 else 277 output = (input + 2) * 5 / 4; 278 279 return output; 280 } 281 282 static const struct pcr_ops rtl8411_pcr_ops = { 283 .fetch_vendor_settings = rtl8411_fetch_vendor_settings, 284 .extra_init_hw = rtl8411_extra_init_hw, 285 .optimize_phy = NULL, 286 .turn_on_led = rtl8411_turn_on_led, 287 .turn_off_led = rtl8411_turn_off_led, 288 .enable_auto_blink = rtl8411_enable_auto_blink, 289 .disable_auto_blink = rtl8411_disable_auto_blink, 290 .card_power_on = rtl8411_card_power_on, 291 .card_power_off = rtl8411_card_power_off, 292 .switch_output_voltage = rtl8411_switch_output_voltage, 293 .cd_deglitch = rtl8411_cd_deglitch, 294 .conv_clk_and_div_n = rtl8411_conv_clk_and_div_n, 295 .force_power_down = rtl8411_force_power_down, 296 }; 297 298 static const struct pcr_ops rtl8402_pcr_ops = { 299 .fetch_vendor_settings = rtl8411_fetch_vendor_settings, 300 .extra_init_hw = rtl8411_extra_init_hw, 301 .optimize_phy = NULL, 302 .turn_on_led = rtl8411_turn_on_led, 303 .turn_off_led = rtl8411_turn_off_led, 304 .enable_auto_blink = rtl8411_enable_auto_blink, 305 .disable_auto_blink = rtl8411_disable_auto_blink, 306 .card_power_on = rtl8411_card_power_on, 307 .card_power_off = rtl8411_card_power_off, 308 .switch_output_voltage = rtl8402_switch_output_voltage, 309 .cd_deglitch = rtl8411_cd_deglitch, 310 .conv_clk_and_div_n = rtl8411_conv_clk_and_div_n, 311 .force_power_down = rtl8411_force_power_down, 312 }; 313 314 static const struct pcr_ops rtl8411b_pcr_ops = { 315 .fetch_vendor_settings = rtl8411b_fetch_vendor_settings, 316 .extra_init_hw = rtl8411b_extra_init_hw, 317 .optimize_phy = NULL, 318 .turn_on_led = rtl8411_turn_on_led, 319 .turn_off_led = rtl8411_turn_off_led, 320 .enable_auto_blink = rtl8411_enable_auto_blink, 321 .disable_auto_blink = rtl8411_disable_auto_blink, 322 .card_power_on = rtl8411_card_power_on, 323 .card_power_off = rtl8411_card_power_off, 324 .switch_output_voltage = rtl8411_switch_output_voltage, 325 .cd_deglitch = rtl8411_cd_deglitch, 326 .conv_clk_and_div_n = rtl8411_conv_clk_and_div_n, 327 .force_power_down = rtl8411_force_power_down, 328 }; 329 330 /* SD Pull Control Enable: 331 * SD_DAT[3:0] ==> pull up 332 * SD_CD ==> pull up 333 * SD_WP ==> pull up 334 * SD_CMD ==> pull up 335 * SD_CLK ==> pull down 336 */ 337 static const u32 rtl8411_sd_pull_ctl_enable_tbl[] = { 338 RTSX_REG_PAIR(CARD_PULL_CTL1, 0xAA), 339 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA), 340 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xA9), 341 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09), 342 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x09), 343 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04), 344 0, 345 }; 346 347 /* SD Pull Control Disable: 348 * SD_DAT[3:0] ==> pull down 349 * SD_CD ==> pull up 350 * SD_WP ==> pull down 351 * SD_CMD ==> pull down 352 * SD_CLK ==> pull down 353 */ 354 static const u32 rtl8411_sd_pull_ctl_disable_tbl[] = { 355 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65), 356 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 357 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95), 358 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09), 359 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05), 360 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04), 361 0, 362 }; 363 364 /* MS Pull Control Enable: 365 * MS CD ==> pull up 366 * others ==> pull down 367 */ 368 static const u32 rtl8411_ms_pull_ctl_enable_tbl[] = { 369 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65), 370 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 371 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95), 372 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x05), 373 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05), 374 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04), 375 0, 376 }; 377 378 /* MS Pull Control Disable: 379 * MS CD ==> pull up 380 * others ==> pull down 381 */ 382 static const u32 rtl8411_ms_pull_ctl_disable_tbl[] = { 383 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65), 384 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 385 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95), 386 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09), 387 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05), 388 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04), 389 0, 390 }; 391 392 static const u32 rtl8411b_qfn64_sd_pull_ctl_enable_tbl[] = { 393 RTSX_REG_PAIR(CARD_PULL_CTL1, 0xAA), 394 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA), 395 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x09 | 0xD0), 396 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09 | 0x50), 397 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50), 398 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11), 399 0, 400 }; 401 402 static const u32 rtl8411b_qfn48_sd_pull_ctl_enable_tbl[] = { 403 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA), 404 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x69 | 0x90), 405 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x08 | 0x11), 406 0, 407 }; 408 409 static const u32 rtl8411b_qfn64_sd_pull_ctl_disable_tbl[] = { 410 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65), 411 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 412 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x05 | 0xD0), 413 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09 | 0x50), 414 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50), 415 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11), 416 0, 417 }; 418 419 static const u32 rtl8411b_qfn48_sd_pull_ctl_disable_tbl[] = { 420 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 421 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x65 | 0x90), 422 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11), 423 0, 424 }; 425 426 static const u32 rtl8411b_qfn64_ms_pull_ctl_enable_tbl[] = { 427 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65), 428 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 429 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x05 | 0xD0), 430 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x05 | 0x50), 431 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50), 432 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11), 433 0, 434 }; 435 436 static const u32 rtl8411b_qfn48_ms_pull_ctl_enable_tbl[] = { 437 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 438 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x65 | 0x90), 439 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11), 440 0, 441 }; 442 443 static const u32 rtl8411b_qfn64_ms_pull_ctl_disable_tbl[] = { 444 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65), 445 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 446 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x05 | 0xD0), 447 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09 | 0x50), 448 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50), 449 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11), 450 0, 451 }; 452 453 static const u32 rtl8411b_qfn48_ms_pull_ctl_disable_tbl[] = { 454 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 455 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x65 | 0x90), 456 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11), 457 0, 458 }; 459 460 static void rtl8411_init_common_params(struct rtsx_pcr *pcr) 461 { 462 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104; 463 pcr->num_slots = 2; 464 pcr->flags = 0; 465 pcr->card_drive_sel = RTL8411_CARD_DRIVE_DEFAULT; 466 pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B; 467 pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D; 468 pcr->aspm_en = ASPM_L1_EN; 469 pcr->tx_initial_phase = SET_CLOCK_PHASE(23, 7, 14); 470 pcr->rx_initial_phase = SET_CLOCK_PHASE(4, 3, 10); 471 pcr->ic_version = rtl8411_get_ic_version(pcr); 472 } 473 474 void rtl8411_init_params(struct rtsx_pcr *pcr) 475 { 476 rtl8411_init_common_params(pcr); 477 pcr->ops = &rtl8411_pcr_ops; 478 set_pull_ctrl_tables(pcr, rtl8411); 479 } 480 481 void rtl8411b_init_params(struct rtsx_pcr *pcr) 482 { 483 rtl8411_init_common_params(pcr); 484 pcr->ops = &rtl8411b_pcr_ops; 485 if (rtl8411b_is_qfn48(pcr)) 486 set_pull_ctrl_tables(pcr, rtl8411b_qfn48); 487 else 488 set_pull_ctrl_tables(pcr, rtl8411b_qfn64); 489 } 490 491 void rtl8402_init_params(struct rtsx_pcr *pcr) 492 { 493 rtl8411_init_common_params(pcr); 494 pcr->ops = &rtl8402_pcr_ops; 495 set_pull_ctrl_tables(pcr, rtl8411); 496 } 497