xref: /openbmc/linux/drivers/misc/apds990x.c (revision f050bb8f)
12b27bdccSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
292b1f84dSSamu Onkalo /*
392b1f84dSSamu Onkalo  * This file is part of the APDS990x sensor driver.
492b1f84dSSamu Onkalo  * Chip is combined proximity and ambient light sensor.
592b1f84dSSamu Onkalo  *
692b1f84dSSamu Onkalo  * Copyright (C) 2010 Nokia Corporation and/or its subsidiary(-ies).
792b1f84dSSamu Onkalo  *
892b1f84dSSamu Onkalo  * Contact: Samu Onkalo <samu.p.onkalo@nokia.com>
992b1f84dSSamu Onkalo  */
1092b1f84dSSamu Onkalo 
1192b1f84dSSamu Onkalo #include <linux/kernel.h>
1292b1f84dSSamu Onkalo #include <linux/module.h>
1392b1f84dSSamu Onkalo #include <linux/i2c.h>
1492b1f84dSSamu Onkalo #include <linux/interrupt.h>
1592b1f84dSSamu Onkalo #include <linux/mutex.h>
1692b1f84dSSamu Onkalo #include <linux/regulator/consumer.h>
1792b1f84dSSamu Onkalo #include <linux/pm_runtime.h>
1892b1f84dSSamu Onkalo #include <linux/delay.h>
1992b1f84dSSamu Onkalo #include <linux/wait.h>
2092b1f84dSSamu Onkalo #include <linux/slab.h>
21610387d1SWolfram Sang #include <linux/platform_data/apds990x.h>
2292b1f84dSSamu Onkalo 
2392b1f84dSSamu Onkalo /* Register map */
2492b1f84dSSamu Onkalo #define APDS990X_ENABLE	 0x00 /* Enable of states and interrupts */
2592b1f84dSSamu Onkalo #define APDS990X_ATIME	 0x01 /* ALS ADC time  */
2692b1f84dSSamu Onkalo #define APDS990X_PTIME	 0x02 /* Proximity ADC time  */
2792b1f84dSSamu Onkalo #define APDS990X_WTIME	 0x03 /* Wait time  */
2892b1f84dSSamu Onkalo #define APDS990X_AILTL	 0x04 /* ALS interrupt low threshold low byte */
2992b1f84dSSamu Onkalo #define APDS990X_AILTH	 0x05 /* ALS interrupt low threshold hi byte */
3092b1f84dSSamu Onkalo #define APDS990X_AIHTL	 0x06 /* ALS interrupt hi threshold low byte */
3192b1f84dSSamu Onkalo #define APDS990X_AIHTH	 0x07 /* ALS interrupt hi threshold hi byte */
3292b1f84dSSamu Onkalo #define APDS990X_PILTL	 0x08 /* Proximity interrupt low threshold low byte */
3392b1f84dSSamu Onkalo #define APDS990X_PILTH	 0x09 /* Proximity interrupt low threshold hi byte */
3492b1f84dSSamu Onkalo #define APDS990X_PIHTL	 0x0a /* Proximity interrupt hi threshold low byte */
3592b1f84dSSamu Onkalo #define APDS990X_PIHTH	 0x0b /* Proximity interrupt hi threshold hi byte */
3692b1f84dSSamu Onkalo #define APDS990X_PERS	 0x0c /* Interrupt persistence filters */
3792b1f84dSSamu Onkalo #define APDS990X_CONFIG	 0x0d /* Configuration */
3892b1f84dSSamu Onkalo #define APDS990X_PPCOUNT 0x0e /* Proximity pulse count */
3992b1f84dSSamu Onkalo #define APDS990X_CONTROL 0x0f /* Gain control register */
4092b1f84dSSamu Onkalo #define APDS990X_REV	 0x11 /* Revision Number */
4192b1f84dSSamu Onkalo #define APDS990X_ID	 0x12 /* Device ID */
4292b1f84dSSamu Onkalo #define APDS990X_STATUS	 0x13 /* Device status */
4392b1f84dSSamu Onkalo #define APDS990X_CDATAL	 0x14 /* Clear ADC low data register */
4492b1f84dSSamu Onkalo #define APDS990X_CDATAH	 0x15 /* Clear ADC high data register */
4592b1f84dSSamu Onkalo #define APDS990X_IRDATAL 0x16 /* IR ADC low data register */
4692b1f84dSSamu Onkalo #define APDS990X_IRDATAH 0x17 /* IR ADC high data register */
4792b1f84dSSamu Onkalo #define APDS990X_PDATAL	 0x18 /* Proximity ADC low data register */
4892b1f84dSSamu Onkalo #define APDS990X_PDATAH	 0x19 /* Proximity ADC high data register */
4992b1f84dSSamu Onkalo 
5092b1f84dSSamu Onkalo /* Control */
5192b1f84dSSamu Onkalo #define APDS990X_MAX_AGAIN	3
5292b1f84dSSamu Onkalo 
5392b1f84dSSamu Onkalo /* Enable register */
5492b1f84dSSamu Onkalo #define APDS990X_EN_PIEN	(0x1 << 5)
5592b1f84dSSamu Onkalo #define APDS990X_EN_AIEN	(0x1 << 4)
5692b1f84dSSamu Onkalo #define APDS990X_EN_WEN		(0x1 << 3)
5792b1f84dSSamu Onkalo #define APDS990X_EN_PEN		(0x1 << 2)
5892b1f84dSSamu Onkalo #define APDS990X_EN_AEN		(0x1 << 1)
5992b1f84dSSamu Onkalo #define APDS990X_EN_PON		(0x1 << 0)
6092b1f84dSSamu Onkalo #define APDS990X_EN_DISABLE_ALL 0
6192b1f84dSSamu Onkalo 
6292b1f84dSSamu Onkalo /* Status register */
6392b1f84dSSamu Onkalo #define APDS990X_ST_PINT	(0x1 << 5)
6492b1f84dSSamu Onkalo #define APDS990X_ST_AINT	(0x1 << 4)
6592b1f84dSSamu Onkalo 
6692b1f84dSSamu Onkalo /* I2C access types */
6792b1f84dSSamu Onkalo #define APDS990x_CMD_TYPE_MASK	(0x03 << 5)
6892b1f84dSSamu Onkalo #define APDS990x_CMD_TYPE_RB	(0x00 << 5) /* Repeated byte */
6992b1f84dSSamu Onkalo #define APDS990x_CMD_TYPE_INC	(0x01 << 5) /* Auto increment */
7092b1f84dSSamu Onkalo #define APDS990x_CMD_TYPE_SPE	(0x03 << 5) /* Special function */
7192b1f84dSSamu Onkalo 
7292b1f84dSSamu Onkalo #define APDS990x_ADDR_SHIFT	0
7392b1f84dSSamu Onkalo #define APDS990x_CMD		0x80
7492b1f84dSSamu Onkalo 
7592b1f84dSSamu Onkalo /* Interrupt ack commands */
7692b1f84dSSamu Onkalo #define APDS990X_INT_ACK_ALS	0x6
7792b1f84dSSamu Onkalo #define APDS990X_INT_ACK_PS	0x5
7892b1f84dSSamu Onkalo #define APDS990X_INT_ACK_BOTH	0x7
7992b1f84dSSamu Onkalo 
8092b1f84dSSamu Onkalo /* ptime */
8192b1f84dSSamu Onkalo #define APDS990X_PTIME_DEFAULT	0xff /* Recommended conversion time 2.7ms*/
8292b1f84dSSamu Onkalo 
8392b1f84dSSamu Onkalo /* wtime */
8492b1f84dSSamu Onkalo #define APDS990X_WTIME_DEFAULT	0xee /* ~50ms wait time */
8592b1f84dSSamu Onkalo 
8692b1f84dSSamu Onkalo #define APDS990X_TIME_TO_ADC	1024 /* One timetick as ADC count value */
8792b1f84dSSamu Onkalo 
8892b1f84dSSamu Onkalo /* Persistence */
8992b1f84dSSamu Onkalo #define APDS990X_APERS_SHIFT	0
9092b1f84dSSamu Onkalo #define APDS990X_PPERS_SHIFT	4
9192b1f84dSSamu Onkalo 
9292b1f84dSSamu Onkalo /* Supported ID:s */
9392b1f84dSSamu Onkalo #define APDS990X_ID_0		0x0
9492b1f84dSSamu Onkalo #define APDS990X_ID_4		0x4
9592b1f84dSSamu Onkalo #define APDS990X_ID_29		0x29
9692b1f84dSSamu Onkalo 
9792b1f84dSSamu Onkalo /* pgain and pdiode settings */
9892b1f84dSSamu Onkalo #define APDS_PGAIN_1X	       0x0
9992b1f84dSSamu Onkalo #define APDS_PDIODE_IR	       0x2
10092b1f84dSSamu Onkalo 
10192b1f84dSSamu Onkalo #define APDS990X_LUX_OUTPUT_SCALE 10
10292b1f84dSSamu Onkalo 
10392b1f84dSSamu Onkalo /* Reverse chip factors for threshold calculation */
10492b1f84dSSamu Onkalo struct reverse_factors {
10592b1f84dSSamu Onkalo 	u32 afactor;
10692b1f84dSSamu Onkalo 	int cf1;
10792b1f84dSSamu Onkalo 	int irf1;
10892b1f84dSSamu Onkalo 	int cf2;
10992b1f84dSSamu Onkalo 	int irf2;
11092b1f84dSSamu Onkalo };
11192b1f84dSSamu Onkalo 
11292b1f84dSSamu Onkalo struct apds990x_chip {
11392b1f84dSSamu Onkalo 	struct apds990x_platform_data	*pdata;
11492b1f84dSSamu Onkalo 	struct i2c_client		*client;
11592b1f84dSSamu Onkalo 	struct mutex			mutex; /* avoid parallel access */
11692b1f84dSSamu Onkalo 	struct regulator_bulk_data	regs[2];
11792b1f84dSSamu Onkalo 	wait_queue_head_t		wait;
11892b1f84dSSamu Onkalo 
11992b1f84dSSamu Onkalo 	int	prox_en;
12092b1f84dSSamu Onkalo 	bool	prox_continuous_mode;
12192b1f84dSSamu Onkalo 	bool	lux_wait_fresh_res;
12292b1f84dSSamu Onkalo 
12392b1f84dSSamu Onkalo 	/* Chip parameters */
12492b1f84dSSamu Onkalo 	struct	apds990x_chip_factors	cf;
12592b1f84dSSamu Onkalo 	struct	reverse_factors		rcf;
12692b1f84dSSamu Onkalo 	u16	atime;		/* als integration time */
12792b1f84dSSamu Onkalo 	u16	arate;		/* als reporting rate */
12892b1f84dSSamu Onkalo 	u16	a_max_result;	/* Max possible ADC value with current atime */
12992b1f84dSSamu Onkalo 	u8	again_meas;	/* Gain used in last measurement */
13092b1f84dSSamu Onkalo 	u8	again_next;	/* Next calculated gain */
13192b1f84dSSamu Onkalo 	u8	pgain;
13292b1f84dSSamu Onkalo 	u8	pdiode;
13392b1f84dSSamu Onkalo 	u8	pdrive;
13492b1f84dSSamu Onkalo 	u8	lux_persistence;
13592b1f84dSSamu Onkalo 	u8	prox_persistence;
13692b1f84dSSamu Onkalo 
13792b1f84dSSamu Onkalo 	u32	lux_raw;
13892b1f84dSSamu Onkalo 	u32	lux;
13992b1f84dSSamu Onkalo 	u16	lux_clear;
14092b1f84dSSamu Onkalo 	u16	lux_ir;
14192b1f84dSSamu Onkalo 	u16	lux_calib;
14292b1f84dSSamu Onkalo 	u32	lux_thres_hi;
14392b1f84dSSamu Onkalo 	u32	lux_thres_lo;
14492b1f84dSSamu Onkalo 
14592b1f84dSSamu Onkalo 	u32	prox_thres;
14692b1f84dSSamu Onkalo 	u16	prox_data;
14792b1f84dSSamu Onkalo 	u16	prox_calib;
14892b1f84dSSamu Onkalo 
14992b1f84dSSamu Onkalo 	char	chipname[10];
15092b1f84dSSamu Onkalo 	u8	revision;
15192b1f84dSSamu Onkalo };
15292b1f84dSSamu Onkalo 
15392b1f84dSSamu Onkalo #define APDS_CALIB_SCALER		8192
15492b1f84dSSamu Onkalo #define APDS_LUX_NEUTRAL_CALIB_VALUE	(1 * APDS_CALIB_SCALER)
15592b1f84dSSamu Onkalo #define APDS_PROX_NEUTRAL_CALIB_VALUE	(1 * APDS_CALIB_SCALER)
15692b1f84dSSamu Onkalo 
15792b1f84dSSamu Onkalo #define APDS_PROX_DEF_THRES		600
15892b1f84dSSamu Onkalo #define APDS_PROX_HYSTERESIS		50
15992b1f84dSSamu Onkalo #define APDS_LUX_DEF_THRES_HI		101
16092b1f84dSSamu Onkalo #define APDS_LUX_DEF_THRES_LO		100
16192b1f84dSSamu Onkalo #define APDS_DEFAULT_PROX_PERS		1
16292b1f84dSSamu Onkalo 
16392b1f84dSSamu Onkalo #define APDS_TIMEOUT			2000
16492b1f84dSSamu Onkalo #define APDS_STARTUP_DELAY		25000 /* us */
16592b1f84dSSamu Onkalo #define APDS_RANGE			65535
16692b1f84dSSamu Onkalo #define APDS_PROX_RANGE			1023
16792b1f84dSSamu Onkalo #define APDS_LUX_GAIN_LO_LIMIT		100
16892b1f84dSSamu Onkalo #define APDS_LUX_GAIN_LO_LIMIT_STRICT	25
16992b1f84dSSamu Onkalo 
17092b1f84dSSamu Onkalo #define TIMESTEP			87 /* 2.7ms is about 87 / 32 */
17192b1f84dSSamu Onkalo #define TIME_STEP_SCALER		32
17292b1f84dSSamu Onkalo 
17392b1f84dSSamu Onkalo #define APDS_LUX_AVERAGING_TIME		50 /* tolerates 50/60Hz ripple */
17492b1f84dSSamu Onkalo #define APDS_LUX_DEFAULT_RATE		200
17592b1f84dSSamu Onkalo 
17692b1f84dSSamu Onkalo static const u8 again[]	= {1, 8, 16, 120}; /* ALS gain steps */
17792b1f84dSSamu Onkalo 
17892b1f84dSSamu Onkalo /* Following two tables must match i.e 10Hz rate means 1 as persistence value */
17992b1f84dSSamu Onkalo static const u16 arates_hz[] = {10, 5, 2, 1};
18092b1f84dSSamu Onkalo static const u8 apersis[] = {1, 2, 4, 5};
18192b1f84dSSamu Onkalo 
18292b1f84dSSamu Onkalo /* Regulators */
18392b1f84dSSamu Onkalo static const char reg_vcc[] = "Vdd";
18492b1f84dSSamu Onkalo static const char reg_vled[] = "Vled";
18592b1f84dSSamu Onkalo 
apds990x_read_byte(struct apds990x_chip * chip,u8 reg,u8 * data)18692b1f84dSSamu Onkalo static int apds990x_read_byte(struct apds990x_chip *chip, u8 reg, u8 *data)
18792b1f84dSSamu Onkalo {
18892b1f84dSSamu Onkalo 	struct i2c_client *client = chip->client;
18992b1f84dSSamu Onkalo 	s32 ret;
19092b1f84dSSamu Onkalo 
19192b1f84dSSamu Onkalo 	reg &= ~APDS990x_CMD_TYPE_MASK;
19292b1f84dSSamu Onkalo 	reg |= APDS990x_CMD | APDS990x_CMD_TYPE_RB;
19392b1f84dSSamu Onkalo 
19492b1f84dSSamu Onkalo 	ret = i2c_smbus_read_byte_data(client, reg);
19592b1f84dSSamu Onkalo 	*data = ret;
19692b1f84dSSamu Onkalo 	return (int)ret;
19792b1f84dSSamu Onkalo }
19892b1f84dSSamu Onkalo 
apds990x_read_word(struct apds990x_chip * chip,u8 reg,u16 * data)19992b1f84dSSamu Onkalo static int apds990x_read_word(struct apds990x_chip *chip, u8 reg, u16 *data)
20092b1f84dSSamu Onkalo {
20192b1f84dSSamu Onkalo 	struct i2c_client *client = chip->client;
20292b1f84dSSamu Onkalo 	s32 ret;
20392b1f84dSSamu Onkalo 
20492b1f84dSSamu Onkalo 	reg &= ~APDS990x_CMD_TYPE_MASK;
20592b1f84dSSamu Onkalo 	reg |= APDS990x_CMD | APDS990x_CMD_TYPE_INC;
20692b1f84dSSamu Onkalo 
20792b1f84dSSamu Onkalo 	ret = i2c_smbus_read_word_data(client, reg);
20892b1f84dSSamu Onkalo 	*data = ret;
20992b1f84dSSamu Onkalo 	return (int)ret;
21092b1f84dSSamu Onkalo }
21192b1f84dSSamu Onkalo 
apds990x_write_byte(struct apds990x_chip * chip,u8 reg,u8 data)21292b1f84dSSamu Onkalo static int apds990x_write_byte(struct apds990x_chip *chip, u8 reg, u8 data)
21392b1f84dSSamu Onkalo {
21492b1f84dSSamu Onkalo 	struct i2c_client *client = chip->client;
21592b1f84dSSamu Onkalo 	s32 ret;
21692b1f84dSSamu Onkalo 
21792b1f84dSSamu Onkalo 	reg &= ~APDS990x_CMD_TYPE_MASK;
21892b1f84dSSamu Onkalo 	reg |= APDS990x_CMD | APDS990x_CMD_TYPE_RB;
21992b1f84dSSamu Onkalo 
22092b1f84dSSamu Onkalo 	ret = i2c_smbus_write_byte_data(client, reg, data);
22192b1f84dSSamu Onkalo 	return (int)ret;
22292b1f84dSSamu Onkalo }
22392b1f84dSSamu Onkalo 
apds990x_write_word(struct apds990x_chip * chip,u8 reg,u16 data)22492b1f84dSSamu Onkalo static int apds990x_write_word(struct apds990x_chip *chip, u8 reg, u16 data)
22592b1f84dSSamu Onkalo {
22692b1f84dSSamu Onkalo 	struct i2c_client *client = chip->client;
22792b1f84dSSamu Onkalo 	s32 ret;
22892b1f84dSSamu Onkalo 
22992b1f84dSSamu Onkalo 	reg &= ~APDS990x_CMD_TYPE_MASK;
23092b1f84dSSamu Onkalo 	reg |= APDS990x_CMD | APDS990x_CMD_TYPE_INC;
23192b1f84dSSamu Onkalo 
23292b1f84dSSamu Onkalo 	ret = i2c_smbus_write_word_data(client, reg, data);
23392b1f84dSSamu Onkalo 	return (int)ret;
23492b1f84dSSamu Onkalo }
23592b1f84dSSamu Onkalo 
apds990x_mode_on(struct apds990x_chip * chip)23692b1f84dSSamu Onkalo static int apds990x_mode_on(struct apds990x_chip *chip)
23792b1f84dSSamu Onkalo {
23892b1f84dSSamu Onkalo 	/* ALS is mandatory, proximity optional */
23992b1f84dSSamu Onkalo 	u8 reg = APDS990X_EN_AIEN | APDS990X_EN_PON | APDS990X_EN_AEN |
24092b1f84dSSamu Onkalo 		APDS990X_EN_WEN;
24192b1f84dSSamu Onkalo 
24292b1f84dSSamu Onkalo 	if (chip->prox_en)
24392b1f84dSSamu Onkalo 		reg |= APDS990X_EN_PIEN | APDS990X_EN_PEN;
24492b1f84dSSamu Onkalo 
24592b1f84dSSamu Onkalo 	return apds990x_write_byte(chip, APDS990X_ENABLE, reg);
24692b1f84dSSamu Onkalo }
24792b1f84dSSamu Onkalo 
apds990x_lux_to_threshold(struct apds990x_chip * chip,u32 lux)24892b1f84dSSamu Onkalo static u16 apds990x_lux_to_threshold(struct apds990x_chip *chip, u32 lux)
24992b1f84dSSamu Onkalo {
25092b1f84dSSamu Onkalo 	u32 thres;
25192b1f84dSSamu Onkalo 	u32 cpl;
25292b1f84dSSamu Onkalo 	u32 ir;
25392b1f84dSSamu Onkalo 
25492b1f84dSSamu Onkalo 	if (lux == 0)
25592b1f84dSSamu Onkalo 		return 0;
25692b1f84dSSamu Onkalo 	else if (lux == APDS_RANGE)
25792b1f84dSSamu Onkalo 		return APDS_RANGE;
25892b1f84dSSamu Onkalo 
25992b1f84dSSamu Onkalo 	/*
26092b1f84dSSamu Onkalo 	 * Reported LUX value is a combination of the IR and CLEAR channel
26192b1f84dSSamu Onkalo 	 * values. However, interrupt threshold is only for clear channel.
26292b1f84dSSamu Onkalo 	 * This function approximates needed HW threshold value for a given
26392b1f84dSSamu Onkalo 	 * LUX value in the current lightning type.
26492b1f84dSSamu Onkalo 	 * IR level compared to visible light varies heavily depending on the
26592b1f84dSSamu Onkalo 	 * source of the light
26692b1f84dSSamu Onkalo 	 *
26792b1f84dSSamu Onkalo 	 * Calculate threshold value for the next measurement period.
26892b1f84dSSamu Onkalo 	 * Math: threshold = lux * cpl where
26992b1f84dSSamu Onkalo 	 * cpl = atime * again / (glass_attenuation * device_factor)
27092b1f84dSSamu Onkalo 	 * (count-per-lux)
27192b1f84dSSamu Onkalo 	 *
27292b1f84dSSamu Onkalo 	 * First remove calibration. Division by four is to avoid overflow
27392b1f84dSSamu Onkalo 	 */
27492b1f84dSSamu Onkalo 	lux = lux * (APDS_CALIB_SCALER / 4) / (chip->lux_calib / 4);
27592b1f84dSSamu Onkalo 
27692b1f84dSSamu Onkalo 	/* Multiplication by 64 is to increase accuracy */
27792b1f84dSSamu Onkalo 	cpl = ((u32)chip->atime * (u32)again[chip->again_next] *
27892b1f84dSSamu Onkalo 		APDS_PARAM_SCALE * 64) / (chip->cf.ga * chip->cf.df);
27992b1f84dSSamu Onkalo 
28092b1f84dSSamu Onkalo 	thres = lux * cpl / 64;
28192b1f84dSSamu Onkalo 	/*
28292b1f84dSSamu Onkalo 	 * Convert IR light from the latest result to match with
28392b1f84dSSamu Onkalo 	 * new gain step. This helps to adapt with the current
28492b1f84dSSamu Onkalo 	 * source of light.
28592b1f84dSSamu Onkalo 	 */
28692b1f84dSSamu Onkalo 	ir = (u32)chip->lux_ir * (u32)again[chip->again_next] /
28792b1f84dSSamu Onkalo 		(u32)again[chip->again_meas];
28892b1f84dSSamu Onkalo 
28992b1f84dSSamu Onkalo 	/*
29092b1f84dSSamu Onkalo 	 * Compensate count with IR light impact
29192b1f84dSSamu Onkalo 	 * IAC1 > IAC2 (see apds990x_get_lux for formulas)
29292b1f84dSSamu Onkalo 	 */
29392b1f84dSSamu Onkalo 	if (chip->lux_clear * APDS_PARAM_SCALE >=
29492b1f84dSSamu Onkalo 		chip->rcf.afactor * chip->lux_ir)
29592b1f84dSSamu Onkalo 		thres = (chip->rcf.cf1 * thres + chip->rcf.irf1 * ir) /
29692b1f84dSSamu Onkalo 			APDS_PARAM_SCALE;
29792b1f84dSSamu Onkalo 	else
29892b1f84dSSamu Onkalo 		thres = (chip->rcf.cf2 * thres + chip->rcf.irf2 * ir) /
29992b1f84dSSamu Onkalo 			APDS_PARAM_SCALE;
30092b1f84dSSamu Onkalo 
30192b1f84dSSamu Onkalo 	if (thres >= chip->a_max_result)
30292b1f84dSSamu Onkalo 		thres = chip->a_max_result - 1;
30392b1f84dSSamu Onkalo 	return thres;
30492b1f84dSSamu Onkalo }
30592b1f84dSSamu Onkalo 
apds990x_set_atime(struct apds990x_chip * chip,u32 time_ms)30692b1f84dSSamu Onkalo static inline int apds990x_set_atime(struct apds990x_chip *chip, u32 time_ms)
30792b1f84dSSamu Onkalo {
30892b1f84dSSamu Onkalo 	u8 reg_value;
30992b1f84dSSamu Onkalo 
31092b1f84dSSamu Onkalo 	chip->atime = time_ms;
31192b1f84dSSamu Onkalo 	/* Formula is specified in the data sheet */
31292b1f84dSSamu Onkalo 	reg_value = 256 - ((time_ms * TIME_STEP_SCALER) / TIMESTEP);
31392b1f84dSSamu Onkalo 	/* Calculate max ADC value for given integration time */
31492b1f84dSSamu Onkalo 	chip->a_max_result = (u16)(256 - reg_value) * APDS990X_TIME_TO_ADC;
31592b1f84dSSamu Onkalo 	return apds990x_write_byte(chip, APDS990X_ATIME, reg_value);
31692b1f84dSSamu Onkalo }
31792b1f84dSSamu Onkalo 
31892b1f84dSSamu Onkalo /* Called always with mutex locked */
apds990x_refresh_pthres(struct apds990x_chip * chip,int data)31992b1f84dSSamu Onkalo static int apds990x_refresh_pthres(struct apds990x_chip *chip, int data)
32092b1f84dSSamu Onkalo {
32192b1f84dSSamu Onkalo 	int ret, lo, hi;
32292b1f84dSSamu Onkalo 
32392b1f84dSSamu Onkalo 	/* If the chip is not in use, don't try to access it */
32492b1f84dSSamu Onkalo 	if (pm_runtime_suspended(&chip->client->dev))
32592b1f84dSSamu Onkalo 		return 0;
32692b1f84dSSamu Onkalo 
32792b1f84dSSamu Onkalo 	if (data < chip->prox_thres) {
32892b1f84dSSamu Onkalo 		lo = 0;
32992b1f84dSSamu Onkalo 		hi = chip->prox_thres;
33092b1f84dSSamu Onkalo 	} else {
33192b1f84dSSamu Onkalo 		lo = chip->prox_thres - APDS_PROX_HYSTERESIS;
33292b1f84dSSamu Onkalo 		if (chip->prox_continuous_mode)
33392b1f84dSSamu Onkalo 			hi = chip->prox_thres;
33492b1f84dSSamu Onkalo 		else
33592b1f84dSSamu Onkalo 			hi = APDS_RANGE;
33692b1f84dSSamu Onkalo 	}
33792b1f84dSSamu Onkalo 
33892b1f84dSSamu Onkalo 	ret = apds990x_write_word(chip, APDS990X_PILTL, lo);
33992b1f84dSSamu Onkalo 	ret |= apds990x_write_word(chip, APDS990X_PIHTL, hi);
34092b1f84dSSamu Onkalo 	return ret;
34192b1f84dSSamu Onkalo }
34292b1f84dSSamu Onkalo 
34392b1f84dSSamu Onkalo /* Called always with mutex locked */
apds990x_refresh_athres(struct apds990x_chip * chip)34492b1f84dSSamu Onkalo static int apds990x_refresh_athres(struct apds990x_chip *chip)
34592b1f84dSSamu Onkalo {
34692b1f84dSSamu Onkalo 	int ret;
34792b1f84dSSamu Onkalo 	/* If the chip is not in use, don't try to access it */
34892b1f84dSSamu Onkalo 	if (pm_runtime_suspended(&chip->client->dev))
34992b1f84dSSamu Onkalo 		return 0;
35092b1f84dSSamu Onkalo 
35192b1f84dSSamu Onkalo 	ret = apds990x_write_word(chip, APDS990X_AILTL,
35292b1f84dSSamu Onkalo 			apds990x_lux_to_threshold(chip, chip->lux_thres_lo));
35392b1f84dSSamu Onkalo 	ret |= apds990x_write_word(chip, APDS990X_AIHTL,
35492b1f84dSSamu Onkalo 			apds990x_lux_to_threshold(chip, chip->lux_thres_hi));
35592b1f84dSSamu Onkalo 
35692b1f84dSSamu Onkalo 	return ret;
35792b1f84dSSamu Onkalo }
35892b1f84dSSamu Onkalo 
35992b1f84dSSamu Onkalo /* Called always with mutex locked */
apds990x_force_a_refresh(struct apds990x_chip * chip)36092b1f84dSSamu Onkalo static void apds990x_force_a_refresh(struct apds990x_chip *chip)
36192b1f84dSSamu Onkalo {
36292b1f84dSSamu Onkalo 	/* This will force ALS interrupt after the next measurement. */
36392b1f84dSSamu Onkalo 	apds990x_write_word(chip, APDS990X_AILTL, APDS_LUX_DEF_THRES_LO);
36492b1f84dSSamu Onkalo 	apds990x_write_word(chip, APDS990X_AIHTL, APDS_LUX_DEF_THRES_HI);
36592b1f84dSSamu Onkalo }
36692b1f84dSSamu Onkalo 
36792b1f84dSSamu Onkalo /* Called always with mutex locked */
apds990x_force_p_refresh(struct apds990x_chip * chip)36892b1f84dSSamu Onkalo static void apds990x_force_p_refresh(struct apds990x_chip *chip)
36992b1f84dSSamu Onkalo {
37092b1f84dSSamu Onkalo 	/* This will force proximity interrupt after the next measurement. */
37192b1f84dSSamu Onkalo 	apds990x_write_word(chip, APDS990X_PILTL, APDS_PROX_DEF_THRES - 1);
37292b1f84dSSamu Onkalo 	apds990x_write_word(chip, APDS990X_PIHTL, APDS_PROX_DEF_THRES);
37392b1f84dSSamu Onkalo }
37492b1f84dSSamu Onkalo 
37592b1f84dSSamu Onkalo /* Called always with mutex locked */
apds990x_calc_again(struct apds990x_chip * chip)37692b1f84dSSamu Onkalo static int apds990x_calc_again(struct apds990x_chip *chip)
37792b1f84dSSamu Onkalo {
37892b1f84dSSamu Onkalo 	int curr_again = chip->again_meas;
37992b1f84dSSamu Onkalo 	int next_again = chip->again_meas;
38092b1f84dSSamu Onkalo 	int ret = 0;
38192b1f84dSSamu Onkalo 
38292b1f84dSSamu Onkalo 	/* Calculate suitable als gain */
38392b1f84dSSamu Onkalo 	if (chip->lux_clear == chip->a_max_result)
38492b1f84dSSamu Onkalo 		next_again -= 2; /* ALS saturated. Decrease gain by 2 steps */
38592b1f84dSSamu Onkalo 	else if (chip->lux_clear > chip->a_max_result / 2)
38692b1f84dSSamu Onkalo 		next_again--;
38792b1f84dSSamu Onkalo 	else if (chip->lux_clear < APDS_LUX_GAIN_LO_LIMIT_STRICT)
38892b1f84dSSamu Onkalo 		next_again += 2; /* Too dark. Increase gain by 2 steps */
38992b1f84dSSamu Onkalo 	else if (chip->lux_clear < APDS_LUX_GAIN_LO_LIMIT)
39092b1f84dSSamu Onkalo 		next_again++;
39192b1f84dSSamu Onkalo 
39292b1f84dSSamu Onkalo 	/* Limit gain to available range */
39392b1f84dSSamu Onkalo 	if (next_again < 0)
39492b1f84dSSamu Onkalo 		next_again = 0;
39592b1f84dSSamu Onkalo 	else if (next_again > APDS990X_MAX_AGAIN)
39692b1f84dSSamu Onkalo 		next_again = APDS990X_MAX_AGAIN;
39792b1f84dSSamu Onkalo 
39892b1f84dSSamu Onkalo 	/* Let's check can we trust the measured result */
39992b1f84dSSamu Onkalo 	if (chip->lux_clear == chip->a_max_result)
40092b1f84dSSamu Onkalo 		/* Result can be totally garbage due to saturation */
40192b1f84dSSamu Onkalo 		ret = -ERANGE;
40292b1f84dSSamu Onkalo 	else if (next_again != curr_again &&
40392b1f84dSSamu Onkalo 		chip->lux_clear < APDS_LUX_GAIN_LO_LIMIT_STRICT)
40492b1f84dSSamu Onkalo 		/*
40592b1f84dSSamu Onkalo 		 * Gain is changed and measurement result is very small.
40692b1f84dSSamu Onkalo 		 * Result can be totally garbage due to underflow
40792b1f84dSSamu Onkalo 		 */
40892b1f84dSSamu Onkalo 		ret = -ERANGE;
40992b1f84dSSamu Onkalo 
41092b1f84dSSamu Onkalo 	chip->again_next = next_again;
41192b1f84dSSamu Onkalo 	apds990x_write_byte(chip, APDS990X_CONTROL,
41292b1f84dSSamu Onkalo 			(chip->pdrive << 6) |
41392b1f84dSSamu Onkalo 			(chip->pdiode << 4) |
41492b1f84dSSamu Onkalo 			(chip->pgain << 2) |
41592b1f84dSSamu Onkalo 			(chip->again_next << 0));
41692b1f84dSSamu Onkalo 
41792b1f84dSSamu Onkalo 	/*
41892b1f84dSSamu Onkalo 	 * Error means bad result -> re-measurement is needed. The forced
41992b1f84dSSamu Onkalo 	 * refresh uses fastest possible persistence setting to get result
42092b1f84dSSamu Onkalo 	 * as soon as possible.
42192b1f84dSSamu Onkalo 	 */
42292b1f84dSSamu Onkalo 	if (ret < 0)
42392b1f84dSSamu Onkalo 		apds990x_force_a_refresh(chip);
42492b1f84dSSamu Onkalo 	else
42592b1f84dSSamu Onkalo 		apds990x_refresh_athres(chip);
42692b1f84dSSamu Onkalo 
42792b1f84dSSamu Onkalo 	return ret;
42892b1f84dSSamu Onkalo }
42992b1f84dSSamu Onkalo 
43092b1f84dSSamu Onkalo /* Called always with mutex locked */
apds990x_get_lux(struct apds990x_chip * chip,int clear,int ir)43192b1f84dSSamu Onkalo static int apds990x_get_lux(struct apds990x_chip *chip, int clear, int ir)
43292b1f84dSSamu Onkalo {
43392b1f84dSSamu Onkalo 	int iac, iac1, iac2; /* IR adjusted counts */
43492b1f84dSSamu Onkalo 	u32 lpc; /* Lux per count */
43592b1f84dSSamu Onkalo 
43692b1f84dSSamu Onkalo 	/* Formulas:
43792b1f84dSSamu Onkalo 	 * iac1 = CF1 * CLEAR_CH - IRF1 * IR_CH
43892b1f84dSSamu Onkalo 	 * iac2 = CF2 * CLEAR_CH - IRF2 * IR_CH
43992b1f84dSSamu Onkalo 	 */
44092b1f84dSSamu Onkalo 	iac1 = (chip->cf.cf1 * clear - chip->cf.irf1 * ir) / APDS_PARAM_SCALE;
44192b1f84dSSamu Onkalo 	iac2 = (chip->cf.cf2 * clear - chip->cf.irf2 * ir) / APDS_PARAM_SCALE;
44292b1f84dSSamu Onkalo 
44392b1f84dSSamu Onkalo 	iac = max(iac1, iac2);
44492b1f84dSSamu Onkalo 	iac = max(iac, 0);
44592b1f84dSSamu Onkalo 
44692b1f84dSSamu Onkalo 	lpc = APDS990X_LUX_OUTPUT_SCALE * (chip->cf.df * chip->cf.ga) /
44792b1f84dSSamu Onkalo 		(u32)(again[chip->again_meas] * (u32)chip->atime);
44892b1f84dSSamu Onkalo 
44992b1f84dSSamu Onkalo 	return (iac * lpc) / APDS_PARAM_SCALE;
45092b1f84dSSamu Onkalo }
45192b1f84dSSamu Onkalo 
apds990x_ack_int(struct apds990x_chip * chip,u8 mode)45292b1f84dSSamu Onkalo static int apds990x_ack_int(struct apds990x_chip *chip, u8 mode)
45392b1f84dSSamu Onkalo {
45492b1f84dSSamu Onkalo 	struct i2c_client *client = chip->client;
45592b1f84dSSamu Onkalo 	s32 ret;
45692b1f84dSSamu Onkalo 	u8 reg = APDS990x_CMD | APDS990x_CMD_TYPE_SPE;
45792b1f84dSSamu Onkalo 
45892b1f84dSSamu Onkalo 	switch (mode & (APDS990X_ST_AINT | APDS990X_ST_PINT)) {
45992b1f84dSSamu Onkalo 	case APDS990X_ST_AINT:
46092b1f84dSSamu Onkalo 		reg |= APDS990X_INT_ACK_ALS;
46192b1f84dSSamu Onkalo 		break;
46292b1f84dSSamu Onkalo 	case APDS990X_ST_PINT:
46392b1f84dSSamu Onkalo 		reg |= APDS990X_INT_ACK_PS;
46492b1f84dSSamu Onkalo 		break;
46592b1f84dSSamu Onkalo 	default:
46692b1f84dSSamu Onkalo 		reg |= APDS990X_INT_ACK_BOTH;
46792b1f84dSSamu Onkalo 		break;
46892b1f84dSSamu Onkalo 	}
46992b1f84dSSamu Onkalo 
47092b1f84dSSamu Onkalo 	ret = i2c_smbus_read_byte_data(client, reg);
47192b1f84dSSamu Onkalo 	return (int)ret;
47292b1f84dSSamu Onkalo }
47392b1f84dSSamu Onkalo 
apds990x_irq(int irq,void * data)47492b1f84dSSamu Onkalo static irqreturn_t apds990x_irq(int irq, void *data)
47592b1f84dSSamu Onkalo {
47692b1f84dSSamu Onkalo 	struct apds990x_chip *chip = data;
47792b1f84dSSamu Onkalo 	u8 status;
47892b1f84dSSamu Onkalo 
47992b1f84dSSamu Onkalo 	apds990x_read_byte(chip, APDS990X_STATUS, &status);
48092b1f84dSSamu Onkalo 	apds990x_ack_int(chip, status);
48192b1f84dSSamu Onkalo 
48292b1f84dSSamu Onkalo 	mutex_lock(&chip->mutex);
48392b1f84dSSamu Onkalo 	if (!pm_runtime_suspended(&chip->client->dev)) {
48492b1f84dSSamu Onkalo 		if (status & APDS990X_ST_AINT) {
48592b1f84dSSamu Onkalo 			apds990x_read_word(chip, APDS990X_CDATAL,
48692b1f84dSSamu Onkalo 					&chip->lux_clear);
48792b1f84dSSamu Onkalo 			apds990x_read_word(chip, APDS990X_IRDATAL,
48892b1f84dSSamu Onkalo 					&chip->lux_ir);
48992b1f84dSSamu Onkalo 			/* Store used gain for calculations */
49092b1f84dSSamu Onkalo 			chip->again_meas = chip->again_next;
49192b1f84dSSamu Onkalo 
49292b1f84dSSamu Onkalo 			chip->lux_raw = apds990x_get_lux(chip,
49392b1f84dSSamu Onkalo 							chip->lux_clear,
49492b1f84dSSamu Onkalo 							chip->lux_ir);
49592b1f84dSSamu Onkalo 
49692b1f84dSSamu Onkalo 			if (apds990x_calc_again(chip) == 0) {
49792b1f84dSSamu Onkalo 				/* Result is valid */
49892b1f84dSSamu Onkalo 				chip->lux = chip->lux_raw;
49992b1f84dSSamu Onkalo 				chip->lux_wait_fresh_res = false;
50092b1f84dSSamu Onkalo 				wake_up(&chip->wait);
50192b1f84dSSamu Onkalo 				sysfs_notify(&chip->client->dev.kobj,
50292b1f84dSSamu Onkalo 					NULL, "lux0_input");
50392b1f84dSSamu Onkalo 			}
50492b1f84dSSamu Onkalo 		}
50592b1f84dSSamu Onkalo 
50692b1f84dSSamu Onkalo 		if ((status & APDS990X_ST_PINT) && chip->prox_en) {
50792b1f84dSSamu Onkalo 			u16 clr_ch;
50892b1f84dSSamu Onkalo 
50992b1f84dSSamu Onkalo 			apds990x_read_word(chip, APDS990X_CDATAL, &clr_ch);
51092b1f84dSSamu Onkalo 			/*
51192b1f84dSSamu Onkalo 			 * If ALS channel is saturated at min gain,
51292b1f84dSSamu Onkalo 			 * proximity gives false posivite values.
51392b1f84dSSamu Onkalo 			 * Just ignore them.
51492b1f84dSSamu Onkalo 			 */
51592b1f84dSSamu Onkalo 			if (chip->again_meas == 0 &&
51692b1f84dSSamu Onkalo 				clr_ch == chip->a_max_result)
51792b1f84dSSamu Onkalo 				chip->prox_data = 0;
51892b1f84dSSamu Onkalo 			else
51992b1f84dSSamu Onkalo 				apds990x_read_word(chip,
52092b1f84dSSamu Onkalo 						APDS990X_PDATAL,
52192b1f84dSSamu Onkalo 						&chip->prox_data);
52292b1f84dSSamu Onkalo 
52392b1f84dSSamu Onkalo 			apds990x_refresh_pthres(chip, chip->prox_data);
52492b1f84dSSamu Onkalo 			if (chip->prox_data < chip->prox_thres)
52592b1f84dSSamu Onkalo 				chip->prox_data = 0;
52692b1f84dSSamu Onkalo 			else if (!chip->prox_continuous_mode)
52792b1f84dSSamu Onkalo 				chip->prox_data = APDS_PROX_RANGE;
52892b1f84dSSamu Onkalo 			sysfs_notify(&chip->client->dev.kobj,
52992b1f84dSSamu Onkalo 				NULL, "prox0_raw");
53092b1f84dSSamu Onkalo 		}
53192b1f84dSSamu Onkalo 	}
53292b1f84dSSamu Onkalo 	mutex_unlock(&chip->mutex);
53392b1f84dSSamu Onkalo 	return IRQ_HANDLED;
53492b1f84dSSamu Onkalo }
53592b1f84dSSamu Onkalo 
apds990x_configure(struct apds990x_chip * chip)53692b1f84dSSamu Onkalo static int apds990x_configure(struct apds990x_chip *chip)
53792b1f84dSSamu Onkalo {
53892b1f84dSSamu Onkalo 	/* It is recommended to use disabled mode during these operations */
53992b1f84dSSamu Onkalo 	apds990x_write_byte(chip, APDS990X_ENABLE, APDS990X_EN_DISABLE_ALL);
54092b1f84dSSamu Onkalo 
54192b1f84dSSamu Onkalo 	/* conversion and wait times for different state machince states */
54292b1f84dSSamu Onkalo 	apds990x_write_byte(chip, APDS990X_PTIME, APDS990X_PTIME_DEFAULT);
54392b1f84dSSamu Onkalo 	apds990x_write_byte(chip, APDS990X_WTIME, APDS990X_WTIME_DEFAULT);
54492b1f84dSSamu Onkalo 	apds990x_set_atime(chip, APDS_LUX_AVERAGING_TIME);
54592b1f84dSSamu Onkalo 
54692b1f84dSSamu Onkalo 	apds990x_write_byte(chip, APDS990X_CONFIG, 0);
54792b1f84dSSamu Onkalo 
54892b1f84dSSamu Onkalo 	/* Persistence levels */
54992b1f84dSSamu Onkalo 	apds990x_write_byte(chip, APDS990X_PERS,
55092b1f84dSSamu Onkalo 			(chip->lux_persistence << APDS990X_APERS_SHIFT) |
55192b1f84dSSamu Onkalo 			(chip->prox_persistence << APDS990X_PPERS_SHIFT));
55292b1f84dSSamu Onkalo 
55392b1f84dSSamu Onkalo 	apds990x_write_byte(chip, APDS990X_PPCOUNT, chip->pdata->ppcount);
55492b1f84dSSamu Onkalo 
55592b1f84dSSamu Onkalo 	/* Start with relatively small gain */
55692b1f84dSSamu Onkalo 	chip->again_meas = 1;
55792b1f84dSSamu Onkalo 	chip->again_next = 1;
55892b1f84dSSamu Onkalo 	apds990x_write_byte(chip, APDS990X_CONTROL,
55992b1f84dSSamu Onkalo 			(chip->pdrive << 6) |
56092b1f84dSSamu Onkalo 			(chip->pdiode << 4) |
56192b1f84dSSamu Onkalo 			(chip->pgain << 2) |
56292b1f84dSSamu Onkalo 			(chip->again_next << 0));
56392b1f84dSSamu Onkalo 	return 0;
56492b1f84dSSamu Onkalo }
56592b1f84dSSamu Onkalo 
apds990x_detect(struct apds990x_chip * chip)56692b1f84dSSamu Onkalo static int apds990x_detect(struct apds990x_chip *chip)
56792b1f84dSSamu Onkalo {
56892b1f84dSSamu Onkalo 	struct i2c_client *client = chip->client;
56992b1f84dSSamu Onkalo 	int ret;
57092b1f84dSSamu Onkalo 	u8 id;
57192b1f84dSSamu Onkalo 
57292b1f84dSSamu Onkalo 	ret = apds990x_read_byte(chip, APDS990X_ID, &id);
57392b1f84dSSamu Onkalo 	if (ret < 0) {
57492b1f84dSSamu Onkalo 		dev_err(&client->dev, "ID read failed\n");
57592b1f84dSSamu Onkalo 		return ret;
57692b1f84dSSamu Onkalo 	}
57792b1f84dSSamu Onkalo 
57892b1f84dSSamu Onkalo 	ret = apds990x_read_byte(chip, APDS990X_REV, &chip->revision);
57992b1f84dSSamu Onkalo 	if (ret < 0) {
58092b1f84dSSamu Onkalo 		dev_err(&client->dev, "REV read failed\n");
58192b1f84dSSamu Onkalo 		return ret;
58292b1f84dSSamu Onkalo 	}
58392b1f84dSSamu Onkalo 
58492b1f84dSSamu Onkalo 	switch (id) {
58592b1f84dSSamu Onkalo 	case APDS990X_ID_0:
58692b1f84dSSamu Onkalo 	case APDS990X_ID_4:
58792b1f84dSSamu Onkalo 	case APDS990X_ID_29:
58892b1f84dSSamu Onkalo 		snprintf(chip->chipname, sizeof(chip->chipname), "APDS-990x");
58992b1f84dSSamu Onkalo 		break;
59092b1f84dSSamu Onkalo 	default:
59192b1f84dSSamu Onkalo 		ret = -ENODEV;
59292b1f84dSSamu Onkalo 		break;
59392b1f84dSSamu Onkalo 	}
59492b1f84dSSamu Onkalo 	return ret;
59592b1f84dSSamu Onkalo }
59692b1f84dSSamu Onkalo 
597bbd6d050SRafael J. Wysocki #ifdef CONFIG_PM
apds990x_chip_on(struct apds990x_chip * chip)59892b1f84dSSamu Onkalo static int apds990x_chip_on(struct apds990x_chip *chip)
59992b1f84dSSamu Onkalo {
60092b1f84dSSamu Onkalo 	int err	 = regulator_bulk_enable(ARRAY_SIZE(chip->regs),
60192b1f84dSSamu Onkalo 					chip->regs);
60292b1f84dSSamu Onkalo 	if (err < 0)
60392b1f84dSSamu Onkalo 		return err;
60492b1f84dSSamu Onkalo 
60592b1f84dSSamu Onkalo 	usleep_range(APDS_STARTUP_DELAY, 2 * APDS_STARTUP_DELAY);
60692b1f84dSSamu Onkalo 
60792b1f84dSSamu Onkalo 	/* Refresh all configs in case of regulators were off */
60892b1f84dSSamu Onkalo 	chip->prox_data = 0;
60992b1f84dSSamu Onkalo 	apds990x_configure(chip);
61092b1f84dSSamu Onkalo 	apds990x_mode_on(chip);
61192b1f84dSSamu Onkalo 	return 0;
61292b1f84dSSamu Onkalo }
613ec8f9ceaSGeert Uytterhoeven #endif
61492b1f84dSSamu Onkalo 
apds990x_chip_off(struct apds990x_chip * chip)61592b1f84dSSamu Onkalo static int apds990x_chip_off(struct apds990x_chip *chip)
61692b1f84dSSamu Onkalo {
61792b1f84dSSamu Onkalo 	apds990x_write_byte(chip, APDS990X_ENABLE, APDS990X_EN_DISABLE_ALL);
61892b1f84dSSamu Onkalo 	regulator_bulk_disable(ARRAY_SIZE(chip->regs), chip->regs);
61992b1f84dSSamu Onkalo 	return 0;
62092b1f84dSSamu Onkalo }
62192b1f84dSSamu Onkalo 
apds990x_lux_show(struct device * dev,struct device_attribute * attr,char * buf)62292b1f84dSSamu Onkalo static ssize_t apds990x_lux_show(struct device *dev,
62392b1f84dSSamu Onkalo 				 struct device_attribute *attr, char *buf)
62492b1f84dSSamu Onkalo {
62592b1f84dSSamu Onkalo 	struct apds990x_chip *chip = dev_get_drvdata(dev);
62692b1f84dSSamu Onkalo 	ssize_t ret;
62792b1f84dSSamu Onkalo 	u32 result;
62892b1f84dSSamu Onkalo 	long timeout;
62992b1f84dSSamu Onkalo 
63092b1f84dSSamu Onkalo 	if (pm_runtime_suspended(dev))
63192b1f84dSSamu Onkalo 		return -EIO;
63292b1f84dSSamu Onkalo 
63392b1f84dSSamu Onkalo 	timeout = wait_event_interruptible_timeout(chip->wait,
63492b1f84dSSamu Onkalo 						!chip->lux_wait_fresh_res,
63592b1f84dSSamu Onkalo 						msecs_to_jiffies(APDS_TIMEOUT));
63692b1f84dSSamu Onkalo 	if (!timeout)
63792b1f84dSSamu Onkalo 		return -EIO;
63892b1f84dSSamu Onkalo 
63992b1f84dSSamu Onkalo 	mutex_lock(&chip->mutex);
64092b1f84dSSamu Onkalo 	result = (chip->lux * chip->lux_calib) / APDS_CALIB_SCALER;
64192b1f84dSSamu Onkalo 	if (result > (APDS_RANGE * APDS990X_LUX_OUTPUT_SCALE))
64292b1f84dSSamu Onkalo 		result = APDS_RANGE * APDS990X_LUX_OUTPUT_SCALE;
64392b1f84dSSamu Onkalo 
64492b1f84dSSamu Onkalo 	ret = sprintf(buf, "%d.%d\n",
64592b1f84dSSamu Onkalo 		result / APDS990X_LUX_OUTPUT_SCALE,
64692b1f84dSSamu Onkalo 		result % APDS990X_LUX_OUTPUT_SCALE);
64792b1f84dSSamu Onkalo 	mutex_unlock(&chip->mutex);
64892b1f84dSSamu Onkalo 	return ret;
64992b1f84dSSamu Onkalo }
65092b1f84dSSamu Onkalo 
65192b1f84dSSamu Onkalo static DEVICE_ATTR(lux0_input, S_IRUGO, apds990x_lux_show, NULL);
65292b1f84dSSamu Onkalo 
apds990x_lux_range_show(struct device * dev,struct device_attribute * attr,char * buf)65392b1f84dSSamu Onkalo static ssize_t apds990x_lux_range_show(struct device *dev,
65492b1f84dSSamu Onkalo 				 struct device_attribute *attr, char *buf)
65592b1f84dSSamu Onkalo {
65692b1f84dSSamu Onkalo 	return sprintf(buf, "%u\n", APDS_RANGE);
65792b1f84dSSamu Onkalo }
65892b1f84dSSamu Onkalo 
65992b1f84dSSamu Onkalo static DEVICE_ATTR(lux0_sensor_range, S_IRUGO, apds990x_lux_range_show, NULL);
66092b1f84dSSamu Onkalo 
apds990x_lux_calib_format_show(struct device * dev,struct device_attribute * attr,char * buf)66192b1f84dSSamu Onkalo static ssize_t apds990x_lux_calib_format_show(struct device *dev,
66292b1f84dSSamu Onkalo 				 struct device_attribute *attr, char *buf)
66392b1f84dSSamu Onkalo {
66492b1f84dSSamu Onkalo 	return sprintf(buf, "%u\n", APDS_CALIB_SCALER);
66592b1f84dSSamu Onkalo }
66692b1f84dSSamu Onkalo 
66792b1f84dSSamu Onkalo static DEVICE_ATTR(lux0_calibscale_default, S_IRUGO,
66892b1f84dSSamu Onkalo 		apds990x_lux_calib_format_show, NULL);
66992b1f84dSSamu Onkalo 
apds990x_lux_calib_show(struct device * dev,struct device_attribute * attr,char * buf)67092b1f84dSSamu Onkalo static ssize_t apds990x_lux_calib_show(struct device *dev,
67192b1f84dSSamu Onkalo 				 struct device_attribute *attr, char *buf)
67292b1f84dSSamu Onkalo {
67392b1f84dSSamu Onkalo 	struct apds990x_chip *chip = dev_get_drvdata(dev);
67492b1f84dSSamu Onkalo 
67592b1f84dSSamu Onkalo 	return sprintf(buf, "%u\n", chip->lux_calib);
67692b1f84dSSamu Onkalo }
67792b1f84dSSamu Onkalo 
apds990x_lux_calib_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)67892b1f84dSSamu Onkalo static ssize_t apds990x_lux_calib_store(struct device *dev,
67992b1f84dSSamu Onkalo 				  struct device_attribute *attr,
68092b1f84dSSamu Onkalo 				  const char *buf, size_t len)
68192b1f84dSSamu Onkalo {
68292b1f84dSSamu Onkalo 	struct apds990x_chip *chip = dev_get_drvdata(dev);
68392b1f84dSSamu Onkalo 	unsigned long value;
684f7b41276SJingoo Han 	int ret;
68592b1f84dSSamu Onkalo 
686f7b41276SJingoo Han 	ret = kstrtoul(buf, 0, &value);
687f7b41276SJingoo Han 	if (ret)
688f7b41276SJingoo Han 		return ret;
68992b1f84dSSamu Onkalo 
69092b1f84dSSamu Onkalo 	chip->lux_calib = value;
69192b1f84dSSamu Onkalo 
69292b1f84dSSamu Onkalo 	return len;
69392b1f84dSSamu Onkalo }
69492b1f84dSSamu Onkalo 
69592b1f84dSSamu Onkalo static DEVICE_ATTR(lux0_calibscale, S_IRUGO | S_IWUSR, apds990x_lux_calib_show,
69692b1f84dSSamu Onkalo 		apds990x_lux_calib_store);
69792b1f84dSSamu Onkalo 
apds990x_rate_avail(struct device * dev,struct device_attribute * attr,char * buf)69892b1f84dSSamu Onkalo static ssize_t apds990x_rate_avail(struct device *dev,
69992b1f84dSSamu Onkalo 				   struct device_attribute *attr, char *buf)
70092b1f84dSSamu Onkalo {
70192b1f84dSSamu Onkalo 	int i;
70292b1f84dSSamu Onkalo 	int pos = 0;
703ef7e69fcSDhaval Shah 
70492b1f84dSSamu Onkalo 	for (i = 0; i < ARRAY_SIZE(arates_hz); i++)
70592b1f84dSSamu Onkalo 		pos += sprintf(buf + pos, "%d ", arates_hz[i]);
70692b1f84dSSamu Onkalo 	sprintf(buf + pos - 1, "\n");
70792b1f84dSSamu Onkalo 	return pos;
70892b1f84dSSamu Onkalo }
70992b1f84dSSamu Onkalo 
apds990x_rate_show(struct device * dev,struct device_attribute * attr,char * buf)71092b1f84dSSamu Onkalo static ssize_t apds990x_rate_show(struct device *dev,
71192b1f84dSSamu Onkalo 				   struct device_attribute *attr, char *buf)
71292b1f84dSSamu Onkalo {
71392b1f84dSSamu Onkalo 	struct apds990x_chip *chip =  dev_get_drvdata(dev);
714ef7e69fcSDhaval Shah 
71592b1f84dSSamu Onkalo 	return sprintf(buf, "%d\n", chip->arate);
71692b1f84dSSamu Onkalo }
71792b1f84dSSamu Onkalo 
apds990x_set_arate(struct apds990x_chip * chip,int rate)71892b1f84dSSamu Onkalo static int apds990x_set_arate(struct apds990x_chip *chip, int rate)
71992b1f84dSSamu Onkalo {
72092b1f84dSSamu Onkalo 	int i;
72192b1f84dSSamu Onkalo 
72292b1f84dSSamu Onkalo 	for (i = 0; i < ARRAY_SIZE(arates_hz); i++)
72392b1f84dSSamu Onkalo 		if (rate >= arates_hz[i])
72492b1f84dSSamu Onkalo 			break;
72592b1f84dSSamu Onkalo 
72692b1f84dSSamu Onkalo 	if (i == ARRAY_SIZE(arates_hz))
72792b1f84dSSamu Onkalo 		return -EINVAL;
72892b1f84dSSamu Onkalo 
72992b1f84dSSamu Onkalo 	/* Pick up corresponding persistence value */
73092b1f84dSSamu Onkalo 	chip->lux_persistence = apersis[i];
73192b1f84dSSamu Onkalo 	chip->arate = arates_hz[i];
73292b1f84dSSamu Onkalo 
73392b1f84dSSamu Onkalo 	/* If the chip is not in use, don't try to access it */
73492b1f84dSSamu Onkalo 	if (pm_runtime_suspended(&chip->client->dev))
73592b1f84dSSamu Onkalo 		return 0;
73692b1f84dSSamu Onkalo 
73792b1f84dSSamu Onkalo 	/* Persistence levels */
73892b1f84dSSamu Onkalo 	return apds990x_write_byte(chip, APDS990X_PERS,
73992b1f84dSSamu Onkalo 			(chip->lux_persistence << APDS990X_APERS_SHIFT) |
74092b1f84dSSamu Onkalo 			(chip->prox_persistence << APDS990X_PPERS_SHIFT));
74192b1f84dSSamu Onkalo }
74292b1f84dSSamu Onkalo 
apds990x_rate_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)74392b1f84dSSamu Onkalo static ssize_t apds990x_rate_store(struct device *dev,
74492b1f84dSSamu Onkalo 				  struct device_attribute *attr,
74592b1f84dSSamu Onkalo 				  const char *buf, size_t len)
74692b1f84dSSamu Onkalo {
74792b1f84dSSamu Onkalo 	struct apds990x_chip *chip =  dev_get_drvdata(dev);
74892b1f84dSSamu Onkalo 	unsigned long value;
74992b1f84dSSamu Onkalo 	int ret;
75092b1f84dSSamu Onkalo 
751f7b41276SJingoo Han 	ret = kstrtoul(buf, 0, &value);
752f7b41276SJingoo Han 	if (ret)
753f7b41276SJingoo Han 		return ret;
75492b1f84dSSamu Onkalo 
75592b1f84dSSamu Onkalo 	mutex_lock(&chip->mutex);
75692b1f84dSSamu Onkalo 	ret = apds990x_set_arate(chip, value);
75792b1f84dSSamu Onkalo 	mutex_unlock(&chip->mutex);
75892b1f84dSSamu Onkalo 
75992b1f84dSSamu Onkalo 	if (ret < 0)
76092b1f84dSSamu Onkalo 		return ret;
76192b1f84dSSamu Onkalo 	return len;
76292b1f84dSSamu Onkalo }
76392b1f84dSSamu Onkalo 
76492b1f84dSSamu Onkalo static DEVICE_ATTR(lux0_rate_avail, S_IRUGO, apds990x_rate_avail, NULL);
76592b1f84dSSamu Onkalo 
76692b1f84dSSamu Onkalo static DEVICE_ATTR(lux0_rate, S_IRUGO | S_IWUSR, apds990x_rate_show,
76792b1f84dSSamu Onkalo 						 apds990x_rate_store);
76892b1f84dSSamu Onkalo 
apds990x_prox_show(struct device * dev,struct device_attribute * attr,char * buf)76992b1f84dSSamu Onkalo static ssize_t apds990x_prox_show(struct device *dev,
77092b1f84dSSamu Onkalo 				 struct device_attribute *attr, char *buf)
77192b1f84dSSamu Onkalo {
77292b1f84dSSamu Onkalo 	ssize_t ret;
77392b1f84dSSamu Onkalo 	struct apds990x_chip *chip =  dev_get_drvdata(dev);
774ef7e69fcSDhaval Shah 
77592b1f84dSSamu Onkalo 	if (pm_runtime_suspended(dev) || !chip->prox_en)
77692b1f84dSSamu Onkalo 		return -EIO;
77792b1f84dSSamu Onkalo 
77892b1f84dSSamu Onkalo 	mutex_lock(&chip->mutex);
77992b1f84dSSamu Onkalo 	ret = sprintf(buf, "%d\n", chip->prox_data);
78092b1f84dSSamu Onkalo 	mutex_unlock(&chip->mutex);
78192b1f84dSSamu Onkalo 	return ret;
78292b1f84dSSamu Onkalo }
78392b1f84dSSamu Onkalo 
78492b1f84dSSamu Onkalo static DEVICE_ATTR(prox0_raw, S_IRUGO, apds990x_prox_show, NULL);
78592b1f84dSSamu Onkalo 
apds990x_prox_range_show(struct device * dev,struct device_attribute * attr,char * buf)78692b1f84dSSamu Onkalo static ssize_t apds990x_prox_range_show(struct device *dev,
78792b1f84dSSamu Onkalo 				 struct device_attribute *attr, char *buf)
78892b1f84dSSamu Onkalo {
78992b1f84dSSamu Onkalo 	return sprintf(buf, "%u\n", APDS_PROX_RANGE);
79092b1f84dSSamu Onkalo }
79192b1f84dSSamu Onkalo 
79292b1f84dSSamu Onkalo static DEVICE_ATTR(prox0_sensor_range, S_IRUGO, apds990x_prox_range_show, NULL);
79392b1f84dSSamu Onkalo 
apds990x_prox_enable_show(struct device * dev,struct device_attribute * attr,char * buf)79492b1f84dSSamu Onkalo static ssize_t apds990x_prox_enable_show(struct device *dev,
79592b1f84dSSamu Onkalo 				   struct device_attribute *attr, char *buf)
79692b1f84dSSamu Onkalo {
79792b1f84dSSamu Onkalo 	struct apds990x_chip *chip =  dev_get_drvdata(dev);
798ef7e69fcSDhaval Shah 
79992b1f84dSSamu Onkalo 	return sprintf(buf, "%d\n", chip->prox_en);
80092b1f84dSSamu Onkalo }
80192b1f84dSSamu Onkalo 
apds990x_prox_enable_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)80292b1f84dSSamu Onkalo static ssize_t apds990x_prox_enable_store(struct device *dev,
80392b1f84dSSamu Onkalo 				  struct device_attribute *attr,
80492b1f84dSSamu Onkalo 				  const char *buf, size_t len)
80592b1f84dSSamu Onkalo {
80692b1f84dSSamu Onkalo 	struct apds990x_chip *chip =  dev_get_drvdata(dev);
80792b1f84dSSamu Onkalo 	unsigned long value;
808f7b41276SJingoo Han 	int ret;
80992b1f84dSSamu Onkalo 
810f7b41276SJingoo Han 	ret = kstrtoul(buf, 0, &value);
811f7b41276SJingoo Han 	if (ret)
812f7b41276SJingoo Han 		return ret;
81392b1f84dSSamu Onkalo 
81492b1f84dSSamu Onkalo 	mutex_lock(&chip->mutex);
81592b1f84dSSamu Onkalo 
81692b1f84dSSamu Onkalo 	if (!chip->prox_en)
81792b1f84dSSamu Onkalo 		chip->prox_data = 0;
81892b1f84dSSamu Onkalo 
81992b1f84dSSamu Onkalo 	if (value)
82092b1f84dSSamu Onkalo 		chip->prox_en++;
82192b1f84dSSamu Onkalo 	else if (chip->prox_en > 0)
82292b1f84dSSamu Onkalo 		chip->prox_en--;
82392b1f84dSSamu Onkalo 
82492b1f84dSSamu Onkalo 	if (!pm_runtime_suspended(dev))
82592b1f84dSSamu Onkalo 		apds990x_mode_on(chip);
82692b1f84dSSamu Onkalo 	mutex_unlock(&chip->mutex);
82792b1f84dSSamu Onkalo 	return len;
82892b1f84dSSamu Onkalo }
82992b1f84dSSamu Onkalo 
83092b1f84dSSamu Onkalo static DEVICE_ATTR(prox0_raw_en, S_IRUGO | S_IWUSR, apds990x_prox_enable_show,
83192b1f84dSSamu Onkalo 						   apds990x_prox_enable_store);
83292b1f84dSSamu Onkalo 
833cbbdc608SAndy Shevchenko static const char *reporting_modes[] = {"trigger", "periodic"};
83492b1f84dSSamu Onkalo 
apds990x_prox_reporting_mode_show(struct device * dev,struct device_attribute * attr,char * buf)83592b1f84dSSamu Onkalo static ssize_t apds990x_prox_reporting_mode_show(struct device *dev,
83692b1f84dSSamu Onkalo 				   struct device_attribute *attr, char *buf)
83792b1f84dSSamu Onkalo {
83892b1f84dSSamu Onkalo 	struct apds990x_chip *chip =  dev_get_drvdata(dev);
839ef7e69fcSDhaval Shah 
84092b1f84dSSamu Onkalo 	return sprintf(buf, "%s\n",
84192b1f84dSSamu Onkalo 		reporting_modes[!!chip->prox_continuous_mode]);
84292b1f84dSSamu Onkalo }
84392b1f84dSSamu Onkalo 
apds990x_prox_reporting_mode_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)84492b1f84dSSamu Onkalo static ssize_t apds990x_prox_reporting_mode_store(struct device *dev,
84592b1f84dSSamu Onkalo 				  struct device_attribute *attr,
84692b1f84dSSamu Onkalo 				  const char *buf, size_t len)
84792b1f84dSSamu Onkalo {
84892b1f84dSSamu Onkalo 	struct apds990x_chip *chip =  dev_get_drvdata(dev);
849cbbdc608SAndy Shevchenko 	int ret;
85092b1f84dSSamu Onkalo 
851cbbdc608SAndy Shevchenko 	ret = sysfs_match_string(reporting_modes, buf);
852cbbdc608SAndy Shevchenko 	if (ret < 0)
853cbbdc608SAndy Shevchenko 		return ret;
854cbbdc608SAndy Shevchenko 
855cbbdc608SAndy Shevchenko 	chip->prox_continuous_mode = ret;
85692b1f84dSSamu Onkalo 	return len;
85792b1f84dSSamu Onkalo }
85892b1f84dSSamu Onkalo 
85992b1f84dSSamu Onkalo static DEVICE_ATTR(prox0_reporting_mode, S_IRUGO | S_IWUSR,
86092b1f84dSSamu Onkalo 		apds990x_prox_reporting_mode_show,
86192b1f84dSSamu Onkalo 		apds990x_prox_reporting_mode_store);
86292b1f84dSSamu Onkalo 
apds990x_prox_reporting_avail_show(struct device * dev,struct device_attribute * attr,char * buf)86392b1f84dSSamu Onkalo static ssize_t apds990x_prox_reporting_avail_show(struct device *dev,
86492b1f84dSSamu Onkalo 				   struct device_attribute *attr, char *buf)
86592b1f84dSSamu Onkalo {
86692b1f84dSSamu Onkalo 	return sprintf(buf, "%s %s\n", reporting_modes[0], reporting_modes[1]);
86792b1f84dSSamu Onkalo }
86892b1f84dSSamu Onkalo 
86992b1f84dSSamu Onkalo static DEVICE_ATTR(prox0_reporting_mode_avail, S_IRUGO | S_IWUSR,
87092b1f84dSSamu Onkalo 		apds990x_prox_reporting_avail_show, NULL);
87192b1f84dSSamu Onkalo 
87292b1f84dSSamu Onkalo 
apds990x_lux_thresh_above_show(struct device * dev,struct device_attribute * attr,char * buf)87392b1f84dSSamu Onkalo static ssize_t apds990x_lux_thresh_above_show(struct device *dev,
87492b1f84dSSamu Onkalo 				   struct device_attribute *attr, char *buf)
87592b1f84dSSamu Onkalo {
87692b1f84dSSamu Onkalo 	struct apds990x_chip *chip =  dev_get_drvdata(dev);
877ef7e69fcSDhaval Shah 
87892b1f84dSSamu Onkalo 	return sprintf(buf, "%d\n", chip->lux_thres_hi);
87992b1f84dSSamu Onkalo }
88092b1f84dSSamu Onkalo 
apds990x_lux_thresh_below_show(struct device * dev,struct device_attribute * attr,char * buf)88192b1f84dSSamu Onkalo static ssize_t apds990x_lux_thresh_below_show(struct device *dev,
88292b1f84dSSamu Onkalo 				   struct device_attribute *attr, char *buf)
88392b1f84dSSamu Onkalo {
88492b1f84dSSamu Onkalo 	struct apds990x_chip *chip =  dev_get_drvdata(dev);
885ef7e69fcSDhaval Shah 
88692b1f84dSSamu Onkalo 	return sprintf(buf, "%d\n", chip->lux_thres_lo);
88792b1f84dSSamu Onkalo }
88892b1f84dSSamu Onkalo 
apds990x_set_lux_thresh(struct apds990x_chip * chip,u32 * target,const char * buf)88992b1f84dSSamu Onkalo static ssize_t apds990x_set_lux_thresh(struct apds990x_chip *chip, u32 *target,
89092b1f84dSSamu Onkalo 				const char *buf)
89192b1f84dSSamu Onkalo {
89292b1f84dSSamu Onkalo 	unsigned long thresh;
893f7b41276SJingoo Han 	int ret;
89492b1f84dSSamu Onkalo 
895f7b41276SJingoo Han 	ret = kstrtoul(buf, 0, &thresh);
896f7b41276SJingoo Han 	if (ret)
897f7b41276SJingoo Han 		return ret;
89892b1f84dSSamu Onkalo 
89992b1f84dSSamu Onkalo 	if (thresh > APDS_RANGE)
90092b1f84dSSamu Onkalo 		return -EINVAL;
90192b1f84dSSamu Onkalo 
90292b1f84dSSamu Onkalo 	mutex_lock(&chip->mutex);
90392b1f84dSSamu Onkalo 	*target = thresh;
90492b1f84dSSamu Onkalo 	/*
90592b1f84dSSamu Onkalo 	 * Don't update values in HW if we are still waiting for
90692b1f84dSSamu Onkalo 	 * first interrupt to come after device handle open call.
90792b1f84dSSamu Onkalo 	 */
90892b1f84dSSamu Onkalo 	if (!chip->lux_wait_fresh_res)
90992b1f84dSSamu Onkalo 		apds990x_refresh_athres(chip);
91092b1f84dSSamu Onkalo 	mutex_unlock(&chip->mutex);
91192b1f84dSSamu Onkalo 	return ret;
91292b1f84dSSamu Onkalo 
91392b1f84dSSamu Onkalo }
91492b1f84dSSamu Onkalo 
apds990x_lux_thresh_above_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)91592b1f84dSSamu Onkalo static ssize_t apds990x_lux_thresh_above_store(struct device *dev,
91692b1f84dSSamu Onkalo 				  struct device_attribute *attr,
91792b1f84dSSamu Onkalo 				  const char *buf, size_t len)
91892b1f84dSSamu Onkalo {
91992b1f84dSSamu Onkalo 	struct apds990x_chip *chip =  dev_get_drvdata(dev);
92092b1f84dSSamu Onkalo 	int ret = apds990x_set_lux_thresh(chip, &chip->lux_thres_hi, buf);
921ef7e69fcSDhaval Shah 
92292b1f84dSSamu Onkalo 	if (ret < 0)
92392b1f84dSSamu Onkalo 		return ret;
92492b1f84dSSamu Onkalo 	return len;
92592b1f84dSSamu Onkalo }
92692b1f84dSSamu Onkalo 
apds990x_lux_thresh_below_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)92792b1f84dSSamu Onkalo static ssize_t apds990x_lux_thresh_below_store(struct device *dev,
92892b1f84dSSamu Onkalo 				  struct device_attribute *attr,
92992b1f84dSSamu Onkalo 				  const char *buf, size_t len)
93092b1f84dSSamu Onkalo {
93192b1f84dSSamu Onkalo 	struct apds990x_chip *chip =  dev_get_drvdata(dev);
93292b1f84dSSamu Onkalo 	int ret = apds990x_set_lux_thresh(chip, &chip->lux_thres_lo, buf);
933ef7e69fcSDhaval Shah 
93492b1f84dSSamu Onkalo 	if (ret < 0)
93592b1f84dSSamu Onkalo 		return ret;
93692b1f84dSSamu Onkalo 	return len;
93792b1f84dSSamu Onkalo }
93892b1f84dSSamu Onkalo 
93992b1f84dSSamu Onkalo static DEVICE_ATTR(lux0_thresh_above_value, S_IRUGO | S_IWUSR,
94092b1f84dSSamu Onkalo 		apds990x_lux_thresh_above_show,
94192b1f84dSSamu Onkalo 		apds990x_lux_thresh_above_store);
94292b1f84dSSamu Onkalo 
94392b1f84dSSamu Onkalo static DEVICE_ATTR(lux0_thresh_below_value, S_IRUGO | S_IWUSR,
94492b1f84dSSamu Onkalo 		apds990x_lux_thresh_below_show,
94592b1f84dSSamu Onkalo 		apds990x_lux_thresh_below_store);
94692b1f84dSSamu Onkalo 
apds990x_prox_threshold_show(struct device * dev,struct device_attribute * attr,char * buf)94792b1f84dSSamu Onkalo static ssize_t apds990x_prox_threshold_show(struct device *dev,
94892b1f84dSSamu Onkalo 				   struct device_attribute *attr, char *buf)
94992b1f84dSSamu Onkalo {
95092b1f84dSSamu Onkalo 	struct apds990x_chip *chip =  dev_get_drvdata(dev);
951ef7e69fcSDhaval Shah 
95292b1f84dSSamu Onkalo 	return sprintf(buf, "%d\n", chip->prox_thres);
95392b1f84dSSamu Onkalo }
95492b1f84dSSamu Onkalo 
apds990x_prox_threshold_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)95592b1f84dSSamu Onkalo static ssize_t apds990x_prox_threshold_store(struct device *dev,
95692b1f84dSSamu Onkalo 				  struct device_attribute *attr,
95792b1f84dSSamu Onkalo 				  const char *buf, size_t len)
95892b1f84dSSamu Onkalo {
95992b1f84dSSamu Onkalo 	struct apds990x_chip *chip =  dev_get_drvdata(dev);
96092b1f84dSSamu Onkalo 	unsigned long value;
961f7b41276SJingoo Han 	int ret;
96292b1f84dSSamu Onkalo 
963f7b41276SJingoo Han 	ret = kstrtoul(buf, 0, &value);
964f7b41276SJingoo Han 	if (ret)
965f7b41276SJingoo Han 		return ret;
96692b1f84dSSamu Onkalo 
96792b1f84dSSamu Onkalo 	if ((value > APDS_RANGE) || (value == 0) ||
96892b1f84dSSamu Onkalo 		(value < APDS_PROX_HYSTERESIS))
96992b1f84dSSamu Onkalo 		return -EINVAL;
97092b1f84dSSamu Onkalo 
97192b1f84dSSamu Onkalo 	mutex_lock(&chip->mutex);
97292b1f84dSSamu Onkalo 	chip->prox_thres = value;
97392b1f84dSSamu Onkalo 
97492b1f84dSSamu Onkalo 	apds990x_force_p_refresh(chip);
97592b1f84dSSamu Onkalo 	mutex_unlock(&chip->mutex);
97692b1f84dSSamu Onkalo 	return len;
97792b1f84dSSamu Onkalo }
97892b1f84dSSamu Onkalo 
97992b1f84dSSamu Onkalo static DEVICE_ATTR(prox0_thresh_above_value, S_IRUGO | S_IWUSR,
98092b1f84dSSamu Onkalo 		apds990x_prox_threshold_show,
98192b1f84dSSamu Onkalo 		apds990x_prox_threshold_store);
98292b1f84dSSamu Onkalo 
apds990x_power_state_show(struct device * dev,struct device_attribute * attr,char * buf)98392b1f84dSSamu Onkalo static ssize_t apds990x_power_state_show(struct device *dev,
98492b1f84dSSamu Onkalo 				   struct device_attribute *attr, char *buf)
98592b1f84dSSamu Onkalo {
98692b1f84dSSamu Onkalo 	return sprintf(buf, "%d\n", !pm_runtime_suspended(dev));
98792b1f84dSSamu Onkalo 	return 0;
98892b1f84dSSamu Onkalo }
98992b1f84dSSamu Onkalo 
apds990x_power_state_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)99092b1f84dSSamu Onkalo static ssize_t apds990x_power_state_store(struct device *dev,
99192b1f84dSSamu Onkalo 				  struct device_attribute *attr,
99292b1f84dSSamu Onkalo 				  const char *buf, size_t len)
99392b1f84dSSamu Onkalo {
99492b1f84dSSamu Onkalo 	struct apds990x_chip *chip =  dev_get_drvdata(dev);
99592b1f84dSSamu Onkalo 	unsigned long value;
996f7b41276SJingoo Han 	int ret;
99792b1f84dSSamu Onkalo 
998f7b41276SJingoo Han 	ret = kstrtoul(buf, 0, &value);
999f7b41276SJingoo Han 	if (ret)
1000f7b41276SJingoo Han 		return ret;
1001f7b41276SJingoo Han 
100292b1f84dSSamu Onkalo 	if (value) {
100392b1f84dSSamu Onkalo 		pm_runtime_get_sync(dev);
100492b1f84dSSamu Onkalo 		mutex_lock(&chip->mutex);
100592b1f84dSSamu Onkalo 		chip->lux_wait_fresh_res = true;
100692b1f84dSSamu Onkalo 		apds990x_force_a_refresh(chip);
100792b1f84dSSamu Onkalo 		apds990x_force_p_refresh(chip);
100892b1f84dSSamu Onkalo 		mutex_unlock(&chip->mutex);
100992b1f84dSSamu Onkalo 	} else {
101092b1f84dSSamu Onkalo 		if (!pm_runtime_suspended(dev))
101192b1f84dSSamu Onkalo 			pm_runtime_put(dev);
101292b1f84dSSamu Onkalo 	}
101392b1f84dSSamu Onkalo 	return len;
101492b1f84dSSamu Onkalo }
101592b1f84dSSamu Onkalo 
101692b1f84dSSamu Onkalo static DEVICE_ATTR(power_state, S_IRUGO | S_IWUSR,
101792b1f84dSSamu Onkalo 		apds990x_power_state_show,
101892b1f84dSSamu Onkalo 		apds990x_power_state_store);
101992b1f84dSSamu Onkalo 
apds990x_chip_id_show(struct device * dev,struct device_attribute * attr,char * buf)102092b1f84dSSamu Onkalo static ssize_t apds990x_chip_id_show(struct device *dev,
102192b1f84dSSamu Onkalo 				   struct device_attribute *attr, char *buf)
102292b1f84dSSamu Onkalo {
102392b1f84dSSamu Onkalo 	struct apds990x_chip *chip =  dev_get_drvdata(dev);
1024ef7e69fcSDhaval Shah 
102592b1f84dSSamu Onkalo 	return sprintf(buf, "%s %d\n", chip->chipname, chip->revision);
102692b1f84dSSamu Onkalo }
102792b1f84dSSamu Onkalo 
102892b1f84dSSamu Onkalo static DEVICE_ATTR(chip_id, S_IRUGO, apds990x_chip_id_show, NULL);
102992b1f84dSSamu Onkalo 
103092b1f84dSSamu Onkalo static struct attribute *sysfs_attrs_ctrl[] = {
103192b1f84dSSamu Onkalo 	&dev_attr_lux0_calibscale.attr,
103292b1f84dSSamu Onkalo 	&dev_attr_lux0_calibscale_default.attr,
103392b1f84dSSamu Onkalo 	&dev_attr_lux0_input.attr,
103492b1f84dSSamu Onkalo 	&dev_attr_lux0_sensor_range.attr,
103592b1f84dSSamu Onkalo 	&dev_attr_lux0_rate.attr,
103692b1f84dSSamu Onkalo 	&dev_attr_lux0_rate_avail.attr,
103792b1f84dSSamu Onkalo 	&dev_attr_lux0_thresh_above_value.attr,
103892b1f84dSSamu Onkalo 	&dev_attr_lux0_thresh_below_value.attr,
103992b1f84dSSamu Onkalo 	&dev_attr_prox0_raw_en.attr,
104092b1f84dSSamu Onkalo 	&dev_attr_prox0_raw.attr,
104192b1f84dSSamu Onkalo 	&dev_attr_prox0_sensor_range.attr,
104292b1f84dSSamu Onkalo 	&dev_attr_prox0_thresh_above_value.attr,
104392b1f84dSSamu Onkalo 	&dev_attr_prox0_reporting_mode.attr,
104492b1f84dSSamu Onkalo 	&dev_attr_prox0_reporting_mode_avail.attr,
104592b1f84dSSamu Onkalo 	&dev_attr_chip_id.attr,
104692b1f84dSSamu Onkalo 	&dev_attr_power_state.attr,
104792b1f84dSSamu Onkalo 	NULL
104892b1f84dSSamu Onkalo };
104992b1f84dSSamu Onkalo 
105068b9e993SArvind Yadav static const struct attribute_group apds990x_attribute_group[] = {
105192b1f84dSSamu Onkalo 	{.attrs = sysfs_attrs_ctrl },
105292b1f84dSSamu Onkalo };
105392b1f84dSSamu Onkalo 
apds990x_probe(struct i2c_client * client)10546757c648SUwe Kleine-König static int apds990x_probe(struct i2c_client *client)
105592b1f84dSSamu Onkalo {
105692b1f84dSSamu Onkalo 	struct apds990x_chip *chip;
105792b1f84dSSamu Onkalo 	int err;
105892b1f84dSSamu Onkalo 
105992b1f84dSSamu Onkalo 	chip = kzalloc(sizeof *chip, GFP_KERNEL);
106092b1f84dSSamu Onkalo 	if (!chip)
106192b1f84dSSamu Onkalo 		return -ENOMEM;
106292b1f84dSSamu Onkalo 
106392b1f84dSSamu Onkalo 	i2c_set_clientdata(client, chip);
106492b1f84dSSamu Onkalo 	chip->client  = client;
106592b1f84dSSamu Onkalo 
106692b1f84dSSamu Onkalo 	init_waitqueue_head(&chip->wait);
106792b1f84dSSamu Onkalo 	mutex_init(&chip->mutex);
106892b1f84dSSamu Onkalo 	chip->pdata	= client->dev.platform_data;
106992b1f84dSSamu Onkalo 
107092b1f84dSSamu Onkalo 	if (chip->pdata == NULL) {
107192b1f84dSSamu Onkalo 		dev_err(&client->dev, "platform data is mandatory\n");
107292b1f84dSSamu Onkalo 		err = -EINVAL;
107392b1f84dSSamu Onkalo 		goto fail1;
107492b1f84dSSamu Onkalo 	}
107592b1f84dSSamu Onkalo 
107692b1f84dSSamu Onkalo 	if (chip->pdata->cf.ga == 0) {
107792b1f84dSSamu Onkalo 		/* set uncovered sensor default parameters */
107892b1f84dSSamu Onkalo 		chip->cf.ga = 1966; /* 0.48 * APDS_PARAM_SCALE */
107992b1f84dSSamu Onkalo 		chip->cf.cf1 = 4096; /* 1.00 * APDS_PARAM_SCALE */
108092b1f84dSSamu Onkalo 		chip->cf.irf1 = 9134; /* 2.23 * APDS_PARAM_SCALE */
108192b1f84dSSamu Onkalo 		chip->cf.cf2 = 2867; /* 0.70 * APDS_PARAM_SCALE */
108292b1f84dSSamu Onkalo 		chip->cf.irf2 = 5816; /* 1.42 * APDS_PARAM_SCALE */
108392b1f84dSSamu Onkalo 		chip->cf.df = 52;
108492b1f84dSSamu Onkalo 	} else {
108592b1f84dSSamu Onkalo 		chip->cf = chip->pdata->cf;
108692b1f84dSSamu Onkalo 	}
108792b1f84dSSamu Onkalo 
108892b1f84dSSamu Onkalo 	/* precalculate inverse chip factors for threshold control */
108992b1f84dSSamu Onkalo 	chip->rcf.afactor =
109092b1f84dSSamu Onkalo 		(chip->cf.irf1 - chip->cf.irf2) * APDS_PARAM_SCALE /
109192b1f84dSSamu Onkalo 		(chip->cf.cf1 - chip->cf.cf2);
109292b1f84dSSamu Onkalo 	chip->rcf.cf1 = APDS_PARAM_SCALE * APDS_PARAM_SCALE /
109392b1f84dSSamu Onkalo 		chip->cf.cf1;
109492b1f84dSSamu Onkalo 	chip->rcf.irf1 = chip->cf.irf1 * APDS_PARAM_SCALE /
109592b1f84dSSamu Onkalo 		chip->cf.cf1;
109692b1f84dSSamu Onkalo 	chip->rcf.cf2 = APDS_PARAM_SCALE * APDS_PARAM_SCALE /
109792b1f84dSSamu Onkalo 		chip->cf.cf2;
109892b1f84dSSamu Onkalo 	chip->rcf.irf2 = chip->cf.irf2 * APDS_PARAM_SCALE /
109992b1f84dSSamu Onkalo 		chip->cf.cf2;
110092b1f84dSSamu Onkalo 
110192b1f84dSSamu Onkalo 	/* Set something to start with */
110292b1f84dSSamu Onkalo 	chip->lux_thres_hi = APDS_LUX_DEF_THRES_HI;
110392b1f84dSSamu Onkalo 	chip->lux_thres_lo = APDS_LUX_DEF_THRES_LO;
110492b1f84dSSamu Onkalo 	chip->lux_calib = APDS_LUX_NEUTRAL_CALIB_VALUE;
110592b1f84dSSamu Onkalo 
110692b1f84dSSamu Onkalo 	chip->prox_thres = APDS_PROX_DEF_THRES;
110792b1f84dSSamu Onkalo 	chip->pdrive = chip->pdata->pdrive;
110892b1f84dSSamu Onkalo 	chip->pdiode = APDS_PDIODE_IR;
110992b1f84dSSamu Onkalo 	chip->pgain = APDS_PGAIN_1X;
111092b1f84dSSamu Onkalo 	chip->prox_calib = APDS_PROX_NEUTRAL_CALIB_VALUE;
111192b1f84dSSamu Onkalo 	chip->prox_persistence = APDS_DEFAULT_PROX_PERS;
111292b1f84dSSamu Onkalo 	chip->prox_continuous_mode = false;
111392b1f84dSSamu Onkalo 
111492b1f84dSSamu Onkalo 	chip->regs[0].supply = reg_vcc;
111592b1f84dSSamu Onkalo 	chip->regs[1].supply = reg_vled;
111692b1f84dSSamu Onkalo 
111792b1f84dSSamu Onkalo 	err = regulator_bulk_get(&client->dev,
111892b1f84dSSamu Onkalo 				 ARRAY_SIZE(chip->regs), chip->regs);
111992b1f84dSSamu Onkalo 	if (err < 0) {
112092b1f84dSSamu Onkalo 		dev_err(&client->dev, "Cannot get regulators\n");
112192b1f84dSSamu Onkalo 		goto fail1;
112292b1f84dSSamu Onkalo 	}
112392b1f84dSSamu Onkalo 
112492b1f84dSSamu Onkalo 	err = regulator_bulk_enable(ARRAY_SIZE(chip->regs), chip->regs);
112592b1f84dSSamu Onkalo 	if (err < 0) {
112692b1f84dSSamu Onkalo 		dev_err(&client->dev, "Cannot enable regulators\n");
112792b1f84dSSamu Onkalo 		goto fail2;
112892b1f84dSSamu Onkalo 	}
112992b1f84dSSamu Onkalo 
113092b1f84dSSamu Onkalo 	usleep_range(APDS_STARTUP_DELAY, 2 * APDS_STARTUP_DELAY);
113192b1f84dSSamu Onkalo 
113292b1f84dSSamu Onkalo 	err = apds990x_detect(chip);
113392b1f84dSSamu Onkalo 	if (err < 0) {
113492b1f84dSSamu Onkalo 		dev_err(&client->dev, "APDS990X not found\n");
113592b1f84dSSamu Onkalo 		goto fail3;
113692b1f84dSSamu Onkalo 	}
113792b1f84dSSamu Onkalo 
113892b1f84dSSamu Onkalo 	pm_runtime_set_active(&client->dev);
113992b1f84dSSamu Onkalo 
114092b1f84dSSamu Onkalo 	apds990x_configure(chip);
114192b1f84dSSamu Onkalo 	apds990x_set_arate(chip, APDS_LUX_DEFAULT_RATE);
114292b1f84dSSamu Onkalo 	apds990x_mode_on(chip);
114392b1f84dSSamu Onkalo 
114492b1f84dSSamu Onkalo 	pm_runtime_enable(&client->dev);
114592b1f84dSSamu Onkalo 
114692b1f84dSSamu Onkalo 	if (chip->pdata->setup_resources) {
114792b1f84dSSamu Onkalo 		err = chip->pdata->setup_resources();
114892b1f84dSSamu Onkalo 		if (err) {
114992b1f84dSSamu Onkalo 			err = -EINVAL;
115092b1f84dSSamu Onkalo 			goto fail3;
115192b1f84dSSamu Onkalo 		}
115292b1f84dSSamu Onkalo 	}
115392b1f84dSSamu Onkalo 
115492b1f84dSSamu Onkalo 	err = sysfs_create_group(&chip->client->dev.kobj,
115592b1f84dSSamu Onkalo 				apds990x_attribute_group);
115692b1f84dSSamu Onkalo 	if (err < 0) {
115792b1f84dSSamu Onkalo 		dev_err(&chip->client->dev, "Sysfs registration failed\n");
115892b1f84dSSamu Onkalo 		goto fail4;
115992b1f84dSSamu Onkalo 	}
116092b1f84dSSamu Onkalo 
116192b1f84dSSamu Onkalo 	err = request_threaded_irq(client->irq, NULL,
116292b1f84dSSamu Onkalo 				apds990x_irq,
116392b1f84dSSamu Onkalo 				IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW |
116492b1f84dSSamu Onkalo 				IRQF_ONESHOT,
116592b1f84dSSamu Onkalo 				"apds990x", chip);
116692b1f84dSSamu Onkalo 	if (err) {
116792b1f84dSSamu Onkalo 		dev_err(&client->dev, "could not get IRQ %d\n",
116892b1f84dSSamu Onkalo 			client->irq);
116992b1f84dSSamu Onkalo 		goto fail5;
117092b1f84dSSamu Onkalo 	}
117192b1f84dSSamu Onkalo 	return err;
117292b1f84dSSamu Onkalo fail5:
117392b1f84dSSamu Onkalo 	sysfs_remove_group(&chip->client->dev.kobj,
117492b1f84dSSamu Onkalo 			&apds990x_attribute_group[0]);
117592b1f84dSSamu Onkalo fail4:
117692b1f84dSSamu Onkalo 	if (chip->pdata && chip->pdata->release_resources)
117792b1f84dSSamu Onkalo 		chip->pdata->release_resources();
117892b1f84dSSamu Onkalo fail3:
117992b1f84dSSamu Onkalo 	regulator_bulk_disable(ARRAY_SIZE(chip->regs), chip->regs);
118092b1f84dSSamu Onkalo fail2:
118192b1f84dSSamu Onkalo 	regulator_bulk_free(ARRAY_SIZE(chip->regs), chip->regs);
118292b1f84dSSamu Onkalo fail1:
118392b1f84dSSamu Onkalo 	kfree(chip);
118492b1f84dSSamu Onkalo 	return err;
118592b1f84dSSamu Onkalo }
118692b1f84dSSamu Onkalo 
apds990x_remove(struct i2c_client * client)1187ed5c2f5fSUwe Kleine-König static void apds990x_remove(struct i2c_client *client)
118892b1f84dSSamu Onkalo {
118992b1f84dSSamu Onkalo 	struct apds990x_chip *chip = i2c_get_clientdata(client);
119092b1f84dSSamu Onkalo 
119192b1f84dSSamu Onkalo 	free_irq(client->irq, chip);
119292b1f84dSSamu Onkalo 	sysfs_remove_group(&chip->client->dev.kobj,
119392b1f84dSSamu Onkalo 			apds990x_attribute_group);
119492b1f84dSSamu Onkalo 
119592b1f84dSSamu Onkalo 	if (chip->pdata && chip->pdata->release_resources)
119692b1f84dSSamu Onkalo 		chip->pdata->release_resources();
119792b1f84dSSamu Onkalo 
119892b1f84dSSamu Onkalo 	if (!pm_runtime_suspended(&client->dev))
119992b1f84dSSamu Onkalo 		apds990x_chip_off(chip);
120092b1f84dSSamu Onkalo 
120192b1f84dSSamu Onkalo 	pm_runtime_disable(&client->dev);
120292b1f84dSSamu Onkalo 	pm_runtime_set_suspended(&client->dev);
120392b1f84dSSamu Onkalo 
120492b1f84dSSamu Onkalo 	regulator_bulk_free(ARRAY_SIZE(chip->regs), chip->regs);
120592b1f84dSSamu Onkalo 
120692b1f84dSSamu Onkalo 	kfree(chip);
120792b1f84dSSamu Onkalo }
120892b1f84dSSamu Onkalo 
120939d79164SJingoo Han #ifdef CONFIG_PM_SLEEP
apds990x_suspend(struct device * dev)121092b1f84dSSamu Onkalo static int apds990x_suspend(struct device *dev)
121192b1f84dSSamu Onkalo {
12128c99d8e6SGeliang Tang 	struct i2c_client *client = to_i2c_client(dev);
121392b1f84dSSamu Onkalo 	struct apds990x_chip *chip = i2c_get_clientdata(client);
121492b1f84dSSamu Onkalo 
121592b1f84dSSamu Onkalo 	apds990x_chip_off(chip);
121692b1f84dSSamu Onkalo 	return 0;
121792b1f84dSSamu Onkalo }
121892b1f84dSSamu Onkalo 
apds990x_resume(struct device * dev)121992b1f84dSSamu Onkalo static int apds990x_resume(struct device *dev)
122092b1f84dSSamu Onkalo {
12218c99d8e6SGeliang Tang 	struct i2c_client *client = to_i2c_client(dev);
122292b1f84dSSamu Onkalo 	struct apds990x_chip *chip = i2c_get_clientdata(client);
122392b1f84dSSamu Onkalo 
122492b1f84dSSamu Onkalo 	/*
122592b1f84dSSamu Onkalo 	 * If we were enabled at suspend time, it is expected
122692b1f84dSSamu Onkalo 	 * everything works nice and smoothly. Chip_on is enough
122792b1f84dSSamu Onkalo 	 */
122892b1f84dSSamu Onkalo 	apds990x_chip_on(chip);
122992b1f84dSSamu Onkalo 
123092b1f84dSSamu Onkalo 	return 0;
123192b1f84dSSamu Onkalo }
123292b1f84dSSamu Onkalo #endif
123392b1f84dSSamu Onkalo 
1234bbd6d050SRafael J. Wysocki #ifdef CONFIG_PM
apds990x_runtime_suspend(struct device * dev)123592b1f84dSSamu Onkalo static int apds990x_runtime_suspend(struct device *dev)
123692b1f84dSSamu Onkalo {
12378c99d8e6SGeliang Tang 	struct i2c_client *client = to_i2c_client(dev);
123892b1f84dSSamu Onkalo 	struct apds990x_chip *chip = i2c_get_clientdata(client);
123992b1f84dSSamu Onkalo 
124092b1f84dSSamu Onkalo 	apds990x_chip_off(chip);
124192b1f84dSSamu Onkalo 	return 0;
124292b1f84dSSamu Onkalo }
124392b1f84dSSamu Onkalo 
apds990x_runtime_resume(struct device * dev)124492b1f84dSSamu Onkalo static int apds990x_runtime_resume(struct device *dev)
124592b1f84dSSamu Onkalo {
12468c99d8e6SGeliang Tang 	struct i2c_client *client = to_i2c_client(dev);
124792b1f84dSSamu Onkalo 	struct apds990x_chip *chip = i2c_get_clientdata(client);
124892b1f84dSSamu Onkalo 
124992b1f84dSSamu Onkalo 	apds990x_chip_on(chip);
125092b1f84dSSamu Onkalo 	return 0;
125192b1f84dSSamu Onkalo }
125292b1f84dSSamu Onkalo 
125392b1f84dSSamu Onkalo #endif
125492b1f84dSSamu Onkalo 
125592b1f84dSSamu Onkalo static const struct i2c_device_id apds990x_id[] = {
125692b1f84dSSamu Onkalo 	{"apds990x", 0 },
125792b1f84dSSamu Onkalo 	{}
125892b1f84dSSamu Onkalo };
125992b1f84dSSamu Onkalo 
126092b1f84dSSamu Onkalo MODULE_DEVICE_TABLE(i2c, apds990x_id);
126192b1f84dSSamu Onkalo 
126292b1f84dSSamu Onkalo static const struct dev_pm_ops apds990x_pm_ops = {
126392b1f84dSSamu Onkalo 	SET_SYSTEM_SLEEP_PM_OPS(apds990x_suspend, apds990x_resume)
126492b1f84dSSamu Onkalo 	SET_RUNTIME_PM_OPS(apds990x_runtime_suspend,
126592b1f84dSSamu Onkalo 			apds990x_runtime_resume,
126692b1f84dSSamu Onkalo 			NULL)
126792b1f84dSSamu Onkalo };
126892b1f84dSSamu Onkalo 
126992b1f84dSSamu Onkalo static struct i2c_driver apds990x_driver = {
127092b1f84dSSamu Onkalo 	.driver	  = {
127192b1f84dSSamu Onkalo 		.name	= "apds990x",
127292b1f84dSSamu Onkalo 		.pm	= &apds990x_pm_ops,
127392b1f84dSSamu Onkalo 	},
1274*f050bb8fSUwe Kleine-König 	.probe    = apds990x_probe,
12752d6bed9cSBill Pemberton 	.remove	  = apds990x_remove,
127692b1f84dSSamu Onkalo 	.id_table = apds990x_id,
127792b1f84dSSamu Onkalo };
127892b1f84dSSamu Onkalo 
1279a64fe2edSAxel Lin module_i2c_driver(apds990x_driver);
128092b1f84dSSamu Onkalo 
128192b1f84dSSamu Onkalo MODULE_DESCRIPTION("APDS990X combined ALS and proximity sensor");
128292b1f84dSSamu Onkalo MODULE_AUTHOR("Samu Onkalo, Nokia Corporation");
128392b1f84dSSamu Onkalo MODULE_LICENSE("GPL v2");
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