1 /* 2 * wm8350-core.c -- Device access for Wolfson WM8350 3 * 4 * Copyright 2007, 2008 Wolfson Microelectronics PLC. 5 * 6 * Author: Liam Girdwood, Mark Brown 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/init.h> 18 #include <linux/bug.h> 19 #include <linux/device.h> 20 #include <linux/delay.h> 21 #include <linux/interrupt.h> 22 #include <linux/workqueue.h> 23 24 #include <linux/mfd/wm8350/core.h> 25 #include <linux/mfd/wm8350/audio.h> 26 #include <linux/mfd/wm8350/comparator.h> 27 #include <linux/mfd/wm8350/gpio.h> 28 #include <linux/mfd/wm8350/pmic.h> 29 #include <linux/mfd/wm8350/rtc.h> 30 #include <linux/mfd/wm8350/supply.h> 31 #include <linux/mfd/wm8350/wdt.h> 32 33 #define WM8350_UNLOCK_KEY 0x0013 34 #define WM8350_LOCK_KEY 0x0000 35 36 #define WM8350_CLOCK_CONTROL_1 0x28 37 #define WM8350_AIF_TEST 0x74 38 39 /* debug */ 40 #define WM8350_BUS_DEBUG 0 41 #if WM8350_BUS_DEBUG 42 #define dump(regs, src) do { \ 43 int i_; \ 44 u16 *src_ = src; \ 45 printk(KERN_DEBUG); \ 46 for (i_ = 0; i_ < regs; i_++) \ 47 printk(" 0x%4.4x", *src_++); \ 48 printk("\n"); \ 49 } while (0); 50 #else 51 #define dump(bytes, src) 52 #endif 53 54 #define WM8350_LOCK_DEBUG 0 55 #if WM8350_LOCK_DEBUG 56 #define ldbg(format, arg...) printk(format, ## arg) 57 #else 58 #define ldbg(format, arg...) 59 #endif 60 61 /* 62 * WM8350 Device IO 63 */ 64 static DEFINE_MUTEX(io_mutex); 65 static DEFINE_MUTEX(reg_lock_mutex); 66 static DEFINE_MUTEX(auxadc_mutex); 67 68 /* Perform a physical read from the device. 69 */ 70 static int wm8350_phys_read(struct wm8350 *wm8350, u8 reg, int num_regs, 71 u16 *dest) 72 { 73 int i, ret; 74 int bytes = num_regs * 2; 75 76 dev_dbg(wm8350->dev, "volatile read\n"); 77 ret = wm8350->read_dev(wm8350, reg, bytes, (char *)dest); 78 79 for (i = reg; i < reg + num_regs; i++) { 80 /* Cache is CPU endian */ 81 dest[i - reg] = be16_to_cpu(dest[i - reg]); 82 83 /* Satisfy non-volatile bits from cache */ 84 dest[i - reg] &= wm8350_reg_io_map[i].vol; 85 dest[i - reg] |= wm8350->reg_cache[i]; 86 87 /* Mask out non-readable bits */ 88 dest[i - reg] &= wm8350_reg_io_map[i].readable; 89 } 90 91 dump(num_regs, dest); 92 93 return ret; 94 } 95 96 static int wm8350_read(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *dest) 97 { 98 int i; 99 int end = reg + num_regs; 100 int ret = 0; 101 int bytes = num_regs * 2; 102 103 if (wm8350->read_dev == NULL) 104 return -ENODEV; 105 106 if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) { 107 dev_err(wm8350->dev, "invalid reg %x\n", 108 reg + num_regs - 1); 109 return -EINVAL; 110 } 111 112 dev_dbg(wm8350->dev, 113 "%s R%d(0x%2.2x) %d regs\n", __func__, reg, reg, num_regs); 114 115 #if WM8350_BUS_DEBUG 116 /* we can _safely_ read any register, but warn if read not supported */ 117 for (i = reg; i < end; i++) { 118 if (!wm8350_reg_io_map[i].readable) 119 dev_warn(wm8350->dev, 120 "reg R%d is not readable\n", i); 121 } 122 #endif 123 124 /* if any volatile registers are required, then read back all */ 125 for (i = reg; i < end; i++) 126 if (wm8350_reg_io_map[i].vol) 127 return wm8350_phys_read(wm8350, reg, num_regs, dest); 128 129 /* no volatiles, then cache is good */ 130 dev_dbg(wm8350->dev, "cache read\n"); 131 memcpy(dest, &wm8350->reg_cache[reg], bytes); 132 dump(num_regs, dest); 133 return ret; 134 } 135 136 static inline int is_reg_locked(struct wm8350 *wm8350, u8 reg) 137 { 138 if (reg == WM8350_SECURITY || 139 wm8350->reg_cache[WM8350_SECURITY] == WM8350_UNLOCK_KEY) 140 return 0; 141 142 if ((reg == WM8350_GPIO_CONFIGURATION_I_O) || 143 (reg >= WM8350_GPIO_FUNCTION_SELECT_1 && 144 reg <= WM8350_GPIO_FUNCTION_SELECT_4) || 145 (reg >= WM8350_BATTERY_CHARGER_CONTROL_1 && 146 reg <= WM8350_BATTERY_CHARGER_CONTROL_3)) 147 return 1; 148 return 0; 149 } 150 151 static int wm8350_write(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *src) 152 { 153 int i; 154 int end = reg + num_regs; 155 int bytes = num_regs * 2; 156 157 if (wm8350->write_dev == NULL) 158 return -ENODEV; 159 160 if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) { 161 dev_err(wm8350->dev, "invalid reg %x\n", 162 reg + num_regs - 1); 163 return -EINVAL; 164 } 165 166 /* it's generally not a good idea to write to RO or locked registers */ 167 for (i = reg; i < end; i++) { 168 if (!wm8350_reg_io_map[i].writable) { 169 dev_err(wm8350->dev, 170 "attempted write to read only reg R%d\n", i); 171 return -EINVAL; 172 } 173 174 if (is_reg_locked(wm8350, i)) { 175 dev_err(wm8350->dev, 176 "attempted write to locked reg R%d\n", i); 177 return -EINVAL; 178 } 179 180 src[i - reg] &= wm8350_reg_io_map[i].writable; 181 182 wm8350->reg_cache[i] = 183 (wm8350->reg_cache[i] & ~wm8350_reg_io_map[i].writable) 184 | src[i - reg]; 185 186 /* Don't store volatile bits */ 187 wm8350->reg_cache[i] &= ~wm8350_reg_io_map[i].vol; 188 189 src[i - reg] = cpu_to_be16(src[i - reg]); 190 } 191 192 /* Actually write it out */ 193 return wm8350->write_dev(wm8350, reg, bytes, (char *)src); 194 } 195 196 /* 197 * Safe read, modify, write methods 198 */ 199 int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask) 200 { 201 u16 data; 202 int err; 203 204 mutex_lock(&io_mutex); 205 err = wm8350_read(wm8350, reg, 1, &data); 206 if (err) { 207 dev_err(wm8350->dev, "read from reg R%d failed\n", reg); 208 goto out; 209 } 210 211 data &= ~mask; 212 err = wm8350_write(wm8350, reg, 1, &data); 213 if (err) 214 dev_err(wm8350->dev, "write to reg R%d failed\n", reg); 215 out: 216 mutex_unlock(&io_mutex); 217 return err; 218 } 219 EXPORT_SYMBOL_GPL(wm8350_clear_bits); 220 221 int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask) 222 { 223 u16 data; 224 int err; 225 226 mutex_lock(&io_mutex); 227 err = wm8350_read(wm8350, reg, 1, &data); 228 if (err) { 229 dev_err(wm8350->dev, "read from reg R%d failed\n", reg); 230 goto out; 231 } 232 233 data |= mask; 234 err = wm8350_write(wm8350, reg, 1, &data); 235 if (err) 236 dev_err(wm8350->dev, "write to reg R%d failed\n", reg); 237 out: 238 mutex_unlock(&io_mutex); 239 return err; 240 } 241 EXPORT_SYMBOL_GPL(wm8350_set_bits); 242 243 u16 wm8350_reg_read(struct wm8350 *wm8350, int reg) 244 { 245 u16 data; 246 int err; 247 248 mutex_lock(&io_mutex); 249 err = wm8350_read(wm8350, reg, 1, &data); 250 if (err) 251 dev_err(wm8350->dev, "read from reg R%d failed\n", reg); 252 253 mutex_unlock(&io_mutex); 254 return data; 255 } 256 EXPORT_SYMBOL_GPL(wm8350_reg_read); 257 258 int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val) 259 { 260 int ret; 261 u16 data = val; 262 263 mutex_lock(&io_mutex); 264 ret = wm8350_write(wm8350, reg, 1, &data); 265 if (ret) 266 dev_err(wm8350->dev, "write to reg R%d failed\n", reg); 267 mutex_unlock(&io_mutex); 268 return ret; 269 } 270 EXPORT_SYMBOL_GPL(wm8350_reg_write); 271 272 int wm8350_block_read(struct wm8350 *wm8350, int start_reg, int regs, 273 u16 *dest) 274 { 275 int err = 0; 276 277 mutex_lock(&io_mutex); 278 err = wm8350_read(wm8350, start_reg, regs, dest); 279 if (err) 280 dev_err(wm8350->dev, "block read starting from R%d failed\n", 281 start_reg); 282 mutex_unlock(&io_mutex); 283 return err; 284 } 285 EXPORT_SYMBOL_GPL(wm8350_block_read); 286 287 int wm8350_block_write(struct wm8350 *wm8350, int start_reg, int regs, 288 u16 *src) 289 { 290 int ret = 0; 291 292 mutex_lock(&io_mutex); 293 ret = wm8350_write(wm8350, start_reg, regs, src); 294 if (ret) 295 dev_err(wm8350->dev, "block write starting at R%d failed\n", 296 start_reg); 297 mutex_unlock(&io_mutex); 298 return ret; 299 } 300 EXPORT_SYMBOL_GPL(wm8350_block_write); 301 302 int wm8350_reg_lock(struct wm8350 *wm8350) 303 { 304 u16 key = WM8350_LOCK_KEY; 305 int ret; 306 307 ldbg(__func__); 308 mutex_lock(&io_mutex); 309 ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key); 310 if (ret) 311 dev_err(wm8350->dev, "lock failed\n"); 312 mutex_unlock(&io_mutex); 313 return ret; 314 } 315 EXPORT_SYMBOL_GPL(wm8350_reg_lock); 316 317 int wm8350_reg_unlock(struct wm8350 *wm8350) 318 { 319 u16 key = WM8350_UNLOCK_KEY; 320 int ret; 321 322 ldbg(__func__); 323 mutex_lock(&io_mutex); 324 ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key); 325 if (ret) 326 dev_err(wm8350->dev, "unlock failed\n"); 327 mutex_unlock(&io_mutex); 328 return ret; 329 } 330 EXPORT_SYMBOL_GPL(wm8350_reg_unlock); 331 332 static void wm8350_irq_call_handler(struct wm8350 *wm8350, int irq) 333 { 334 mutex_lock(&wm8350->irq_mutex); 335 336 if (wm8350->irq[irq].handler) 337 wm8350->irq[irq].handler(wm8350, irq, wm8350->irq[irq].data); 338 else { 339 dev_err(wm8350->dev, "irq %d nobody cared. now masked.\n", 340 irq); 341 wm8350_mask_irq(wm8350, irq); 342 } 343 344 mutex_unlock(&wm8350->irq_mutex); 345 } 346 347 /* 348 * wm8350_irq_worker actually handles the interrupts. Since all 349 * interrupts are clear on read the IRQ line will be reasserted and 350 * the physical IRQ will be handled again if another interrupt is 351 * asserted while we run - in the normal course of events this is a 352 * rare occurrence so we save I2C/SPI reads. 353 */ 354 static void wm8350_irq_worker(struct work_struct *work) 355 { 356 struct wm8350 *wm8350 = container_of(work, struct wm8350, irq_work); 357 u16 level_one, status1, status2, comp; 358 359 /* TODO: Use block reads to improve performance? */ 360 level_one = wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS) 361 & ~wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK); 362 status1 = wm8350_reg_read(wm8350, WM8350_INT_STATUS_1) 363 & ~wm8350_reg_read(wm8350, WM8350_INT_STATUS_1_MASK); 364 status2 = wm8350_reg_read(wm8350, WM8350_INT_STATUS_2) 365 & ~wm8350_reg_read(wm8350, WM8350_INT_STATUS_2_MASK); 366 comp = wm8350_reg_read(wm8350, WM8350_COMPARATOR_INT_STATUS) 367 & ~wm8350_reg_read(wm8350, WM8350_COMPARATOR_INT_STATUS_MASK); 368 369 /* over current */ 370 if (level_one & WM8350_OC_INT) { 371 u16 oc; 372 373 oc = wm8350_reg_read(wm8350, WM8350_OVER_CURRENT_INT_STATUS); 374 oc &= ~wm8350_reg_read(wm8350, 375 WM8350_OVER_CURRENT_INT_STATUS_MASK); 376 377 if (oc & WM8350_OC_LS_EINT) /* limit switch */ 378 wm8350_irq_call_handler(wm8350, WM8350_IRQ_OC_LS); 379 } 380 381 /* under voltage */ 382 if (level_one & WM8350_UV_INT) { 383 u16 uv; 384 385 uv = wm8350_reg_read(wm8350, WM8350_UNDER_VOLTAGE_INT_STATUS); 386 uv &= ~wm8350_reg_read(wm8350, 387 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK); 388 389 if (uv & WM8350_UV_DC1_EINT) 390 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC1); 391 if (uv & WM8350_UV_DC2_EINT) 392 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC2); 393 if (uv & WM8350_UV_DC3_EINT) 394 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC3); 395 if (uv & WM8350_UV_DC4_EINT) 396 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC4); 397 if (uv & WM8350_UV_DC5_EINT) 398 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC5); 399 if (uv & WM8350_UV_DC6_EINT) 400 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC6); 401 if (uv & WM8350_UV_LDO1_EINT) 402 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO1); 403 if (uv & WM8350_UV_LDO2_EINT) 404 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO2); 405 if (uv & WM8350_UV_LDO3_EINT) 406 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO3); 407 if (uv & WM8350_UV_LDO4_EINT) 408 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO4); 409 } 410 411 /* charger, RTC */ 412 if (status1) { 413 if (status1 & WM8350_CHG_BAT_HOT_EINT) 414 wm8350_irq_call_handler(wm8350, 415 WM8350_IRQ_CHG_BAT_HOT); 416 if (status1 & WM8350_CHG_BAT_COLD_EINT) 417 wm8350_irq_call_handler(wm8350, 418 WM8350_IRQ_CHG_BAT_COLD); 419 if (status1 & WM8350_CHG_BAT_FAIL_EINT) 420 wm8350_irq_call_handler(wm8350, 421 WM8350_IRQ_CHG_BAT_FAIL); 422 if (status1 & WM8350_CHG_TO_EINT) 423 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_TO); 424 if (status1 & WM8350_CHG_END_EINT) 425 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_END); 426 if (status1 & WM8350_CHG_START_EINT) 427 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_START); 428 if (status1 & WM8350_CHG_FAST_RDY_EINT) 429 wm8350_irq_call_handler(wm8350, 430 WM8350_IRQ_CHG_FAST_RDY); 431 if (status1 & WM8350_CHG_VBATT_LT_3P9_EINT) 432 wm8350_irq_call_handler(wm8350, 433 WM8350_IRQ_CHG_VBATT_LT_3P9); 434 if (status1 & WM8350_CHG_VBATT_LT_3P1_EINT) 435 wm8350_irq_call_handler(wm8350, 436 WM8350_IRQ_CHG_VBATT_LT_3P1); 437 if (status1 & WM8350_CHG_VBATT_LT_2P85_EINT) 438 wm8350_irq_call_handler(wm8350, 439 WM8350_IRQ_CHG_VBATT_LT_2P85); 440 if (status1 & WM8350_RTC_ALM_EINT) 441 wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_ALM); 442 if (status1 & WM8350_RTC_SEC_EINT) 443 wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_SEC); 444 if (status1 & WM8350_RTC_PER_EINT) 445 wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_PER); 446 } 447 448 /* current sink, system, aux adc */ 449 if (status2) { 450 if (status2 & WM8350_CS1_EINT) 451 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CS1); 452 if (status2 & WM8350_CS2_EINT) 453 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CS2); 454 455 if (status2 & WM8350_SYS_HYST_COMP_FAIL_EINT) 456 wm8350_irq_call_handler(wm8350, 457 WM8350_IRQ_SYS_HYST_COMP_FAIL); 458 if (status2 & WM8350_SYS_CHIP_GT115_EINT) 459 wm8350_irq_call_handler(wm8350, 460 WM8350_IRQ_SYS_CHIP_GT115); 461 if (status2 & WM8350_SYS_CHIP_GT140_EINT) 462 wm8350_irq_call_handler(wm8350, 463 WM8350_IRQ_SYS_CHIP_GT140); 464 if (status2 & WM8350_SYS_WDOG_TO_EINT) 465 wm8350_irq_call_handler(wm8350, 466 WM8350_IRQ_SYS_WDOG_TO); 467 468 if (status2 & WM8350_AUXADC_DATARDY_EINT) 469 wm8350_irq_call_handler(wm8350, 470 WM8350_IRQ_AUXADC_DATARDY); 471 if (status2 & WM8350_AUXADC_DCOMP4_EINT) 472 wm8350_irq_call_handler(wm8350, 473 WM8350_IRQ_AUXADC_DCOMP4); 474 if (status2 & WM8350_AUXADC_DCOMP3_EINT) 475 wm8350_irq_call_handler(wm8350, 476 WM8350_IRQ_AUXADC_DCOMP3); 477 if (status2 & WM8350_AUXADC_DCOMP2_EINT) 478 wm8350_irq_call_handler(wm8350, 479 WM8350_IRQ_AUXADC_DCOMP2); 480 if (status2 & WM8350_AUXADC_DCOMP1_EINT) 481 wm8350_irq_call_handler(wm8350, 482 WM8350_IRQ_AUXADC_DCOMP1); 483 484 if (status2 & WM8350_USB_LIMIT_EINT) 485 wm8350_irq_call_handler(wm8350, WM8350_IRQ_USB_LIMIT); 486 } 487 488 /* wake, codec, ext */ 489 if (comp) { 490 if (comp & WM8350_WKUP_OFF_STATE_EINT) 491 wm8350_irq_call_handler(wm8350, 492 WM8350_IRQ_WKUP_OFF_STATE); 493 if (comp & WM8350_WKUP_HIB_STATE_EINT) 494 wm8350_irq_call_handler(wm8350, 495 WM8350_IRQ_WKUP_HIB_STATE); 496 if (comp & WM8350_WKUP_CONV_FAULT_EINT) 497 wm8350_irq_call_handler(wm8350, 498 WM8350_IRQ_WKUP_CONV_FAULT); 499 if (comp & WM8350_WKUP_WDOG_RST_EINT) 500 wm8350_irq_call_handler(wm8350, 501 WM8350_IRQ_WKUP_WDOG_RST); 502 if (comp & WM8350_WKUP_GP_PWR_ON_EINT) 503 wm8350_irq_call_handler(wm8350, 504 WM8350_IRQ_WKUP_GP_PWR_ON); 505 if (comp & WM8350_WKUP_ONKEY_EINT) 506 wm8350_irq_call_handler(wm8350, WM8350_IRQ_WKUP_ONKEY); 507 if (comp & WM8350_WKUP_GP_WAKEUP_EINT) 508 wm8350_irq_call_handler(wm8350, 509 WM8350_IRQ_WKUP_GP_WAKEUP); 510 511 if (comp & WM8350_CODEC_JCK_DET_L_EINT) 512 wm8350_irq_call_handler(wm8350, 513 WM8350_IRQ_CODEC_JCK_DET_L); 514 if (comp & WM8350_CODEC_JCK_DET_R_EINT) 515 wm8350_irq_call_handler(wm8350, 516 WM8350_IRQ_CODEC_JCK_DET_R); 517 if (comp & WM8350_CODEC_MICSCD_EINT) 518 wm8350_irq_call_handler(wm8350, 519 WM8350_IRQ_CODEC_MICSCD); 520 if (comp & WM8350_CODEC_MICD_EINT) 521 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CODEC_MICD); 522 523 if (comp & WM8350_EXT_USB_FB_EINT) 524 wm8350_irq_call_handler(wm8350, WM8350_IRQ_EXT_USB_FB); 525 if (comp & WM8350_EXT_WALL_FB_EINT) 526 wm8350_irq_call_handler(wm8350, 527 WM8350_IRQ_EXT_WALL_FB); 528 if (comp & WM8350_EXT_BAT_FB_EINT) 529 wm8350_irq_call_handler(wm8350, WM8350_IRQ_EXT_BAT_FB); 530 } 531 532 if (level_one & WM8350_GP_INT) { 533 int i; 534 u16 gpio; 535 536 gpio = wm8350_reg_read(wm8350, WM8350_GPIO_INT_STATUS); 537 gpio &= ~wm8350_reg_read(wm8350, 538 WM8350_GPIO_INT_STATUS_MASK); 539 540 for (i = 0; i < 12; i++) { 541 if (gpio & (1 << i)) 542 wm8350_irq_call_handler(wm8350, 543 WM8350_IRQ_GPIO(i)); 544 } 545 } 546 547 enable_irq(wm8350->chip_irq); 548 } 549 550 static irqreturn_t wm8350_irq(int irq, void *data) 551 { 552 struct wm8350 *wm8350 = data; 553 554 disable_irq_nosync(irq); 555 schedule_work(&wm8350->irq_work); 556 557 return IRQ_HANDLED; 558 } 559 560 int wm8350_register_irq(struct wm8350 *wm8350, int irq, 561 void (*handler) (struct wm8350 *, int, void *), 562 void *data) 563 { 564 if (irq < 0 || irq > WM8350_NUM_IRQ || !handler) 565 return -EINVAL; 566 567 if (wm8350->irq[irq].handler) 568 return -EBUSY; 569 570 mutex_lock(&wm8350->irq_mutex); 571 wm8350->irq[irq].handler = handler; 572 wm8350->irq[irq].data = data; 573 mutex_unlock(&wm8350->irq_mutex); 574 575 return 0; 576 } 577 EXPORT_SYMBOL_GPL(wm8350_register_irq); 578 579 int wm8350_free_irq(struct wm8350 *wm8350, int irq) 580 { 581 if (irq < 0 || irq > WM8350_NUM_IRQ) 582 return -EINVAL; 583 584 mutex_lock(&wm8350->irq_mutex); 585 wm8350->irq[irq].handler = NULL; 586 mutex_unlock(&wm8350->irq_mutex); 587 return 0; 588 } 589 EXPORT_SYMBOL_GPL(wm8350_free_irq); 590 591 int wm8350_mask_irq(struct wm8350 *wm8350, int irq) 592 { 593 switch (irq) { 594 case WM8350_IRQ_CHG_BAT_HOT: 595 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK, 596 WM8350_IM_CHG_BAT_HOT_EINT); 597 case WM8350_IRQ_CHG_BAT_COLD: 598 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK, 599 WM8350_IM_CHG_BAT_COLD_EINT); 600 case WM8350_IRQ_CHG_BAT_FAIL: 601 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK, 602 WM8350_IM_CHG_BAT_FAIL_EINT); 603 case WM8350_IRQ_CHG_TO: 604 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK, 605 WM8350_IM_CHG_TO_EINT); 606 case WM8350_IRQ_CHG_END: 607 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK, 608 WM8350_IM_CHG_END_EINT); 609 case WM8350_IRQ_CHG_START: 610 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK, 611 WM8350_IM_CHG_START_EINT); 612 case WM8350_IRQ_CHG_FAST_RDY: 613 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK, 614 WM8350_IM_CHG_FAST_RDY_EINT); 615 case WM8350_IRQ_RTC_PER: 616 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK, 617 WM8350_IM_RTC_PER_EINT); 618 case WM8350_IRQ_RTC_SEC: 619 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK, 620 WM8350_IM_RTC_SEC_EINT); 621 case WM8350_IRQ_RTC_ALM: 622 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK, 623 WM8350_IM_RTC_ALM_EINT); 624 case WM8350_IRQ_CHG_VBATT_LT_3P9: 625 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK, 626 WM8350_IM_CHG_VBATT_LT_3P9_EINT); 627 case WM8350_IRQ_CHG_VBATT_LT_3P1: 628 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK, 629 WM8350_IM_CHG_VBATT_LT_3P1_EINT); 630 case WM8350_IRQ_CHG_VBATT_LT_2P85: 631 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK, 632 WM8350_IM_CHG_VBATT_LT_2P85_EINT); 633 case WM8350_IRQ_CS1: 634 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK, 635 WM8350_IM_CS1_EINT); 636 case WM8350_IRQ_CS2: 637 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK, 638 WM8350_IM_CS2_EINT); 639 case WM8350_IRQ_USB_LIMIT: 640 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK, 641 WM8350_IM_USB_LIMIT_EINT); 642 case WM8350_IRQ_AUXADC_DATARDY: 643 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK, 644 WM8350_IM_AUXADC_DATARDY_EINT); 645 case WM8350_IRQ_AUXADC_DCOMP4: 646 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK, 647 WM8350_IM_AUXADC_DCOMP4_EINT); 648 case WM8350_IRQ_AUXADC_DCOMP3: 649 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK, 650 WM8350_IM_AUXADC_DCOMP3_EINT); 651 case WM8350_IRQ_AUXADC_DCOMP2: 652 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK, 653 WM8350_IM_AUXADC_DCOMP2_EINT); 654 case WM8350_IRQ_AUXADC_DCOMP1: 655 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK, 656 WM8350_IM_AUXADC_DCOMP1_EINT); 657 case WM8350_IRQ_SYS_HYST_COMP_FAIL: 658 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK, 659 WM8350_IM_SYS_HYST_COMP_FAIL_EINT); 660 case WM8350_IRQ_SYS_CHIP_GT115: 661 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK, 662 WM8350_IM_SYS_CHIP_GT115_EINT); 663 case WM8350_IRQ_SYS_CHIP_GT140: 664 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK, 665 WM8350_IM_SYS_CHIP_GT140_EINT); 666 case WM8350_IRQ_SYS_WDOG_TO: 667 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK, 668 WM8350_IM_SYS_WDOG_TO_EINT); 669 case WM8350_IRQ_UV_LDO4: 670 return wm8350_set_bits(wm8350, 671 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK, 672 WM8350_IM_UV_LDO4_EINT); 673 case WM8350_IRQ_UV_LDO3: 674 return wm8350_set_bits(wm8350, 675 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK, 676 WM8350_IM_UV_LDO3_EINT); 677 case WM8350_IRQ_UV_LDO2: 678 return wm8350_set_bits(wm8350, 679 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK, 680 WM8350_IM_UV_LDO2_EINT); 681 case WM8350_IRQ_UV_LDO1: 682 return wm8350_set_bits(wm8350, 683 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK, 684 WM8350_IM_UV_LDO1_EINT); 685 case WM8350_IRQ_UV_DC6: 686 return wm8350_set_bits(wm8350, 687 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK, 688 WM8350_IM_UV_DC6_EINT); 689 case WM8350_IRQ_UV_DC5: 690 return wm8350_set_bits(wm8350, 691 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK, 692 WM8350_IM_UV_DC5_EINT); 693 case WM8350_IRQ_UV_DC4: 694 return wm8350_set_bits(wm8350, 695 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK, 696 WM8350_IM_UV_DC4_EINT); 697 case WM8350_IRQ_UV_DC3: 698 return wm8350_set_bits(wm8350, 699 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK, 700 WM8350_IM_UV_DC3_EINT); 701 case WM8350_IRQ_UV_DC2: 702 return wm8350_set_bits(wm8350, 703 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK, 704 WM8350_IM_UV_DC2_EINT); 705 case WM8350_IRQ_UV_DC1: 706 return wm8350_set_bits(wm8350, 707 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK, 708 WM8350_IM_UV_DC1_EINT); 709 case WM8350_IRQ_OC_LS: 710 return wm8350_set_bits(wm8350, 711 WM8350_OVER_CURRENT_INT_STATUS_MASK, 712 WM8350_IM_OC_LS_EINT); 713 case WM8350_IRQ_EXT_USB_FB: 714 return wm8350_set_bits(wm8350, 715 WM8350_COMPARATOR_INT_STATUS_MASK, 716 WM8350_IM_EXT_USB_FB_EINT); 717 case WM8350_IRQ_EXT_WALL_FB: 718 return wm8350_set_bits(wm8350, 719 WM8350_COMPARATOR_INT_STATUS_MASK, 720 WM8350_IM_EXT_WALL_FB_EINT); 721 case WM8350_IRQ_EXT_BAT_FB: 722 return wm8350_set_bits(wm8350, 723 WM8350_COMPARATOR_INT_STATUS_MASK, 724 WM8350_IM_EXT_BAT_FB_EINT); 725 case WM8350_IRQ_CODEC_JCK_DET_L: 726 return wm8350_set_bits(wm8350, 727 WM8350_COMPARATOR_INT_STATUS_MASK, 728 WM8350_IM_CODEC_JCK_DET_L_EINT); 729 case WM8350_IRQ_CODEC_JCK_DET_R: 730 return wm8350_set_bits(wm8350, 731 WM8350_COMPARATOR_INT_STATUS_MASK, 732 WM8350_IM_CODEC_JCK_DET_R_EINT); 733 case WM8350_IRQ_CODEC_MICSCD: 734 return wm8350_set_bits(wm8350, 735 WM8350_COMPARATOR_INT_STATUS_MASK, 736 WM8350_IM_CODEC_MICSCD_EINT); 737 case WM8350_IRQ_CODEC_MICD: 738 return wm8350_set_bits(wm8350, 739 WM8350_COMPARATOR_INT_STATUS_MASK, 740 WM8350_IM_CODEC_MICD_EINT); 741 case WM8350_IRQ_WKUP_OFF_STATE: 742 return wm8350_set_bits(wm8350, 743 WM8350_COMPARATOR_INT_STATUS_MASK, 744 WM8350_IM_WKUP_OFF_STATE_EINT); 745 case WM8350_IRQ_WKUP_HIB_STATE: 746 return wm8350_set_bits(wm8350, 747 WM8350_COMPARATOR_INT_STATUS_MASK, 748 WM8350_IM_WKUP_HIB_STATE_EINT); 749 case WM8350_IRQ_WKUP_CONV_FAULT: 750 return wm8350_set_bits(wm8350, 751 WM8350_COMPARATOR_INT_STATUS_MASK, 752 WM8350_IM_WKUP_CONV_FAULT_EINT); 753 case WM8350_IRQ_WKUP_WDOG_RST: 754 return wm8350_set_bits(wm8350, 755 WM8350_COMPARATOR_INT_STATUS_MASK, 756 WM8350_IM_WKUP_OFF_STATE_EINT); 757 case WM8350_IRQ_WKUP_GP_PWR_ON: 758 return wm8350_set_bits(wm8350, 759 WM8350_COMPARATOR_INT_STATUS_MASK, 760 WM8350_IM_WKUP_GP_PWR_ON_EINT); 761 case WM8350_IRQ_WKUP_ONKEY: 762 return wm8350_set_bits(wm8350, 763 WM8350_COMPARATOR_INT_STATUS_MASK, 764 WM8350_IM_WKUP_ONKEY_EINT); 765 case WM8350_IRQ_WKUP_GP_WAKEUP: 766 return wm8350_set_bits(wm8350, 767 WM8350_COMPARATOR_INT_STATUS_MASK, 768 WM8350_IM_WKUP_GP_WAKEUP_EINT); 769 case WM8350_IRQ_GPIO(0): 770 return wm8350_set_bits(wm8350, 771 WM8350_GPIO_INT_STATUS_MASK, 772 WM8350_IM_GP0_EINT); 773 case WM8350_IRQ_GPIO(1): 774 return wm8350_set_bits(wm8350, 775 WM8350_GPIO_INT_STATUS_MASK, 776 WM8350_IM_GP1_EINT); 777 case WM8350_IRQ_GPIO(2): 778 return wm8350_set_bits(wm8350, 779 WM8350_GPIO_INT_STATUS_MASK, 780 WM8350_IM_GP2_EINT); 781 case WM8350_IRQ_GPIO(3): 782 return wm8350_set_bits(wm8350, 783 WM8350_GPIO_INT_STATUS_MASK, 784 WM8350_IM_GP3_EINT); 785 case WM8350_IRQ_GPIO(4): 786 return wm8350_set_bits(wm8350, 787 WM8350_GPIO_INT_STATUS_MASK, 788 WM8350_IM_GP4_EINT); 789 case WM8350_IRQ_GPIO(5): 790 return wm8350_set_bits(wm8350, 791 WM8350_GPIO_INT_STATUS_MASK, 792 WM8350_IM_GP5_EINT); 793 case WM8350_IRQ_GPIO(6): 794 return wm8350_set_bits(wm8350, 795 WM8350_GPIO_INT_STATUS_MASK, 796 WM8350_IM_GP6_EINT); 797 case WM8350_IRQ_GPIO(7): 798 return wm8350_set_bits(wm8350, 799 WM8350_GPIO_INT_STATUS_MASK, 800 WM8350_IM_GP7_EINT); 801 case WM8350_IRQ_GPIO(8): 802 return wm8350_set_bits(wm8350, 803 WM8350_GPIO_INT_STATUS_MASK, 804 WM8350_IM_GP8_EINT); 805 case WM8350_IRQ_GPIO(9): 806 return wm8350_set_bits(wm8350, 807 WM8350_GPIO_INT_STATUS_MASK, 808 WM8350_IM_GP9_EINT); 809 case WM8350_IRQ_GPIO(10): 810 return wm8350_set_bits(wm8350, 811 WM8350_GPIO_INT_STATUS_MASK, 812 WM8350_IM_GP10_EINT); 813 case WM8350_IRQ_GPIO(11): 814 return wm8350_set_bits(wm8350, 815 WM8350_GPIO_INT_STATUS_MASK, 816 WM8350_IM_GP11_EINT); 817 case WM8350_IRQ_GPIO(12): 818 return wm8350_set_bits(wm8350, 819 WM8350_GPIO_INT_STATUS_MASK, 820 WM8350_IM_GP12_EINT); 821 default: 822 dev_warn(wm8350->dev, "Attempting to mask unknown IRQ %d\n", 823 irq); 824 return -EINVAL; 825 } 826 return 0; 827 } 828 EXPORT_SYMBOL_GPL(wm8350_mask_irq); 829 830 int wm8350_unmask_irq(struct wm8350 *wm8350, int irq) 831 { 832 switch (irq) { 833 case WM8350_IRQ_CHG_BAT_HOT: 834 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK, 835 WM8350_IM_CHG_BAT_HOT_EINT); 836 case WM8350_IRQ_CHG_BAT_COLD: 837 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK, 838 WM8350_IM_CHG_BAT_COLD_EINT); 839 case WM8350_IRQ_CHG_BAT_FAIL: 840 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK, 841 WM8350_IM_CHG_BAT_FAIL_EINT); 842 case WM8350_IRQ_CHG_TO: 843 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK, 844 WM8350_IM_CHG_TO_EINT); 845 case WM8350_IRQ_CHG_END: 846 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK, 847 WM8350_IM_CHG_END_EINT); 848 case WM8350_IRQ_CHG_START: 849 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK, 850 WM8350_IM_CHG_START_EINT); 851 case WM8350_IRQ_CHG_FAST_RDY: 852 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK, 853 WM8350_IM_CHG_FAST_RDY_EINT); 854 case WM8350_IRQ_RTC_PER: 855 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK, 856 WM8350_IM_RTC_PER_EINT); 857 case WM8350_IRQ_RTC_SEC: 858 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK, 859 WM8350_IM_RTC_SEC_EINT); 860 case WM8350_IRQ_RTC_ALM: 861 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK, 862 WM8350_IM_RTC_ALM_EINT); 863 case WM8350_IRQ_CHG_VBATT_LT_3P9: 864 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK, 865 WM8350_IM_CHG_VBATT_LT_3P9_EINT); 866 case WM8350_IRQ_CHG_VBATT_LT_3P1: 867 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK, 868 WM8350_IM_CHG_VBATT_LT_3P1_EINT); 869 case WM8350_IRQ_CHG_VBATT_LT_2P85: 870 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK, 871 WM8350_IM_CHG_VBATT_LT_2P85_EINT); 872 case WM8350_IRQ_CS1: 873 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK, 874 WM8350_IM_CS1_EINT); 875 case WM8350_IRQ_CS2: 876 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK, 877 WM8350_IM_CS2_EINT); 878 case WM8350_IRQ_USB_LIMIT: 879 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK, 880 WM8350_IM_USB_LIMIT_EINT); 881 case WM8350_IRQ_AUXADC_DATARDY: 882 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK, 883 WM8350_IM_AUXADC_DATARDY_EINT); 884 case WM8350_IRQ_AUXADC_DCOMP4: 885 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK, 886 WM8350_IM_AUXADC_DCOMP4_EINT); 887 case WM8350_IRQ_AUXADC_DCOMP3: 888 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK, 889 WM8350_IM_AUXADC_DCOMP3_EINT); 890 case WM8350_IRQ_AUXADC_DCOMP2: 891 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK, 892 WM8350_IM_AUXADC_DCOMP2_EINT); 893 case WM8350_IRQ_AUXADC_DCOMP1: 894 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK, 895 WM8350_IM_AUXADC_DCOMP1_EINT); 896 case WM8350_IRQ_SYS_HYST_COMP_FAIL: 897 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK, 898 WM8350_IM_SYS_HYST_COMP_FAIL_EINT); 899 case WM8350_IRQ_SYS_CHIP_GT115: 900 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK, 901 WM8350_IM_SYS_CHIP_GT115_EINT); 902 case WM8350_IRQ_SYS_CHIP_GT140: 903 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK, 904 WM8350_IM_SYS_CHIP_GT140_EINT); 905 case WM8350_IRQ_SYS_WDOG_TO: 906 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK, 907 WM8350_IM_SYS_WDOG_TO_EINT); 908 case WM8350_IRQ_UV_LDO4: 909 return wm8350_clear_bits(wm8350, 910 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK, 911 WM8350_IM_UV_LDO4_EINT); 912 case WM8350_IRQ_UV_LDO3: 913 return wm8350_clear_bits(wm8350, 914 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK, 915 WM8350_IM_UV_LDO3_EINT); 916 case WM8350_IRQ_UV_LDO2: 917 return wm8350_clear_bits(wm8350, 918 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK, 919 WM8350_IM_UV_LDO2_EINT); 920 case WM8350_IRQ_UV_LDO1: 921 return wm8350_clear_bits(wm8350, 922 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK, 923 WM8350_IM_UV_LDO1_EINT); 924 case WM8350_IRQ_UV_DC6: 925 return wm8350_clear_bits(wm8350, 926 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK, 927 WM8350_IM_UV_DC6_EINT); 928 case WM8350_IRQ_UV_DC5: 929 return wm8350_clear_bits(wm8350, 930 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK, 931 WM8350_IM_UV_DC5_EINT); 932 case WM8350_IRQ_UV_DC4: 933 return wm8350_clear_bits(wm8350, 934 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK, 935 WM8350_IM_UV_DC4_EINT); 936 case WM8350_IRQ_UV_DC3: 937 return wm8350_clear_bits(wm8350, 938 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK, 939 WM8350_IM_UV_DC3_EINT); 940 case WM8350_IRQ_UV_DC2: 941 return wm8350_clear_bits(wm8350, 942 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK, 943 WM8350_IM_UV_DC2_EINT); 944 case WM8350_IRQ_UV_DC1: 945 return wm8350_clear_bits(wm8350, 946 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK, 947 WM8350_IM_UV_DC1_EINT); 948 case WM8350_IRQ_OC_LS: 949 return wm8350_clear_bits(wm8350, 950 WM8350_OVER_CURRENT_INT_STATUS_MASK, 951 WM8350_IM_OC_LS_EINT); 952 case WM8350_IRQ_EXT_USB_FB: 953 return wm8350_clear_bits(wm8350, 954 WM8350_COMPARATOR_INT_STATUS_MASK, 955 WM8350_IM_EXT_USB_FB_EINT); 956 case WM8350_IRQ_EXT_WALL_FB: 957 return wm8350_clear_bits(wm8350, 958 WM8350_COMPARATOR_INT_STATUS_MASK, 959 WM8350_IM_EXT_WALL_FB_EINT); 960 case WM8350_IRQ_EXT_BAT_FB: 961 return wm8350_clear_bits(wm8350, 962 WM8350_COMPARATOR_INT_STATUS_MASK, 963 WM8350_IM_EXT_BAT_FB_EINT); 964 case WM8350_IRQ_CODEC_JCK_DET_L: 965 return wm8350_clear_bits(wm8350, 966 WM8350_COMPARATOR_INT_STATUS_MASK, 967 WM8350_IM_CODEC_JCK_DET_L_EINT); 968 case WM8350_IRQ_CODEC_JCK_DET_R: 969 return wm8350_clear_bits(wm8350, 970 WM8350_COMPARATOR_INT_STATUS_MASK, 971 WM8350_IM_CODEC_JCK_DET_R_EINT); 972 case WM8350_IRQ_CODEC_MICSCD: 973 return wm8350_clear_bits(wm8350, 974 WM8350_COMPARATOR_INT_STATUS_MASK, 975 WM8350_IM_CODEC_MICSCD_EINT); 976 case WM8350_IRQ_CODEC_MICD: 977 return wm8350_clear_bits(wm8350, 978 WM8350_COMPARATOR_INT_STATUS_MASK, 979 WM8350_IM_CODEC_MICD_EINT); 980 case WM8350_IRQ_WKUP_OFF_STATE: 981 return wm8350_clear_bits(wm8350, 982 WM8350_COMPARATOR_INT_STATUS_MASK, 983 WM8350_IM_WKUP_OFF_STATE_EINT); 984 case WM8350_IRQ_WKUP_HIB_STATE: 985 return wm8350_clear_bits(wm8350, 986 WM8350_COMPARATOR_INT_STATUS_MASK, 987 WM8350_IM_WKUP_HIB_STATE_EINT); 988 case WM8350_IRQ_WKUP_CONV_FAULT: 989 return wm8350_clear_bits(wm8350, 990 WM8350_COMPARATOR_INT_STATUS_MASK, 991 WM8350_IM_WKUP_CONV_FAULT_EINT); 992 case WM8350_IRQ_WKUP_WDOG_RST: 993 return wm8350_clear_bits(wm8350, 994 WM8350_COMPARATOR_INT_STATUS_MASK, 995 WM8350_IM_WKUP_OFF_STATE_EINT); 996 case WM8350_IRQ_WKUP_GP_PWR_ON: 997 return wm8350_clear_bits(wm8350, 998 WM8350_COMPARATOR_INT_STATUS_MASK, 999 WM8350_IM_WKUP_GP_PWR_ON_EINT); 1000 case WM8350_IRQ_WKUP_ONKEY: 1001 return wm8350_clear_bits(wm8350, 1002 WM8350_COMPARATOR_INT_STATUS_MASK, 1003 WM8350_IM_WKUP_ONKEY_EINT); 1004 case WM8350_IRQ_WKUP_GP_WAKEUP: 1005 return wm8350_clear_bits(wm8350, 1006 WM8350_COMPARATOR_INT_STATUS_MASK, 1007 WM8350_IM_WKUP_GP_WAKEUP_EINT); 1008 case WM8350_IRQ_GPIO(0): 1009 return wm8350_clear_bits(wm8350, 1010 WM8350_GPIO_INT_STATUS_MASK, 1011 WM8350_IM_GP0_EINT); 1012 case WM8350_IRQ_GPIO(1): 1013 return wm8350_clear_bits(wm8350, 1014 WM8350_GPIO_INT_STATUS_MASK, 1015 WM8350_IM_GP1_EINT); 1016 case WM8350_IRQ_GPIO(2): 1017 return wm8350_clear_bits(wm8350, 1018 WM8350_GPIO_INT_STATUS_MASK, 1019 WM8350_IM_GP2_EINT); 1020 case WM8350_IRQ_GPIO(3): 1021 return wm8350_clear_bits(wm8350, 1022 WM8350_GPIO_INT_STATUS_MASK, 1023 WM8350_IM_GP3_EINT); 1024 case WM8350_IRQ_GPIO(4): 1025 return wm8350_clear_bits(wm8350, 1026 WM8350_GPIO_INT_STATUS_MASK, 1027 WM8350_IM_GP4_EINT); 1028 case WM8350_IRQ_GPIO(5): 1029 return wm8350_clear_bits(wm8350, 1030 WM8350_GPIO_INT_STATUS_MASK, 1031 WM8350_IM_GP5_EINT); 1032 case WM8350_IRQ_GPIO(6): 1033 return wm8350_clear_bits(wm8350, 1034 WM8350_GPIO_INT_STATUS_MASK, 1035 WM8350_IM_GP6_EINT); 1036 case WM8350_IRQ_GPIO(7): 1037 return wm8350_clear_bits(wm8350, 1038 WM8350_GPIO_INT_STATUS_MASK, 1039 WM8350_IM_GP7_EINT); 1040 case WM8350_IRQ_GPIO(8): 1041 return wm8350_clear_bits(wm8350, 1042 WM8350_GPIO_INT_STATUS_MASK, 1043 WM8350_IM_GP8_EINT); 1044 case WM8350_IRQ_GPIO(9): 1045 return wm8350_clear_bits(wm8350, 1046 WM8350_GPIO_INT_STATUS_MASK, 1047 WM8350_IM_GP9_EINT); 1048 case WM8350_IRQ_GPIO(10): 1049 return wm8350_clear_bits(wm8350, 1050 WM8350_GPIO_INT_STATUS_MASK, 1051 WM8350_IM_GP10_EINT); 1052 case WM8350_IRQ_GPIO(11): 1053 return wm8350_clear_bits(wm8350, 1054 WM8350_GPIO_INT_STATUS_MASK, 1055 WM8350_IM_GP11_EINT); 1056 case WM8350_IRQ_GPIO(12): 1057 return wm8350_clear_bits(wm8350, 1058 WM8350_GPIO_INT_STATUS_MASK, 1059 WM8350_IM_GP12_EINT); 1060 default: 1061 dev_warn(wm8350->dev, "Attempting to unmask unknown IRQ %d\n", 1062 irq); 1063 return -EINVAL; 1064 } 1065 return 0; 1066 } 1067 EXPORT_SYMBOL_GPL(wm8350_unmask_irq); 1068 1069 /* 1070 * Cache is always host endian. 1071 */ 1072 static int wm8350_create_cache(struct wm8350 *wm8350, int mode) 1073 { 1074 int i, ret = 0; 1075 u16 value; 1076 const u16 *reg_map; 1077 1078 switch (mode) { 1079 #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_0 1080 case 0: 1081 reg_map = wm8350_mode0_defaults; 1082 break; 1083 #endif 1084 #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_1 1085 case 1: 1086 reg_map = wm8350_mode1_defaults; 1087 break; 1088 #endif 1089 #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_2 1090 case 2: 1091 reg_map = wm8350_mode2_defaults; 1092 break; 1093 #endif 1094 #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_3 1095 case 3: 1096 reg_map = wm8350_mode3_defaults; 1097 break; 1098 #endif 1099 default: 1100 dev_err(wm8350->dev, "Configuration mode %d not supported\n", 1101 mode); 1102 return -EINVAL; 1103 } 1104 1105 wm8350->reg_cache = 1106 kzalloc(sizeof(u16) * (WM8350_MAX_REGISTER + 1), GFP_KERNEL); 1107 if (wm8350->reg_cache == NULL) 1108 return -ENOMEM; 1109 1110 /* Read the initial cache state back from the device - this is 1111 * a PMIC so the device many not be in a virgin state and we 1112 * can't rely on the silicon values. 1113 */ 1114 for (i = 0; i < WM8350_MAX_REGISTER; i++) { 1115 /* audio register range */ 1116 if (wm8350_reg_io_map[i].readable && 1117 (i < WM8350_CLOCK_CONTROL_1 || i > WM8350_AIF_TEST)) { 1118 ret = wm8350->read_dev(wm8350, i, 2, (char *)&value); 1119 if (ret < 0) { 1120 dev_err(wm8350->dev, 1121 "failed to read initial cache value\n"); 1122 goto out; 1123 } 1124 value = be16_to_cpu(value); 1125 value &= wm8350_reg_io_map[i].readable; 1126 value &= ~wm8350_reg_io_map[i].vol; 1127 wm8350->reg_cache[i] = value; 1128 } else 1129 wm8350->reg_cache[i] = reg_map[i]; 1130 } 1131 1132 out: 1133 return ret; 1134 } 1135 1136 /* 1137 * Register a client device. This is non-fatal since there is no need to 1138 * fail the entire device init due to a single platform device failing. 1139 */ 1140 static void wm8350_client_dev_register(struct wm8350 *wm8350, 1141 const char *name, 1142 struct platform_device **pdev) 1143 { 1144 int ret; 1145 1146 *pdev = platform_device_alloc(name, -1); 1147 if (pdev == NULL) { 1148 dev_err(wm8350->dev, "Failed to allocate %s\n", name); 1149 return; 1150 } 1151 1152 (*pdev)->dev.parent = wm8350->dev; 1153 platform_set_drvdata(*pdev, wm8350); 1154 ret = platform_device_add(*pdev); 1155 if (ret != 0) { 1156 dev_err(wm8350->dev, "Failed to register %s: %d\n", name, ret); 1157 platform_device_put(*pdev); 1158 *pdev = NULL; 1159 } 1160 } 1161 1162 int wm8350_device_init(struct wm8350 *wm8350, int irq, 1163 struct wm8350_platform_data *pdata) 1164 { 1165 int ret = -EINVAL; 1166 u16 id1, id2, mask, mode; 1167 1168 /* get WM8350 revision and config mode */ 1169 wm8350->read_dev(wm8350, WM8350_RESET_ID, sizeof(id1), &id1); 1170 wm8350->read_dev(wm8350, WM8350_ID, sizeof(id2), &id2); 1171 1172 id1 = be16_to_cpu(id1); 1173 id2 = be16_to_cpu(id2); 1174 1175 if (id1 == 0x6143) { 1176 switch ((id2 & WM8350_CHIP_REV_MASK) >> 12) { 1177 case WM8350_REV_E: 1178 dev_info(wm8350->dev, "Found Rev E device\n"); 1179 wm8350->rev = WM8350_REV_E; 1180 break; 1181 case WM8350_REV_F: 1182 dev_info(wm8350->dev, "Found Rev F device\n"); 1183 wm8350->rev = WM8350_REV_F; 1184 break; 1185 case WM8350_REV_G: 1186 dev_info(wm8350->dev, "Found Rev G device\n"); 1187 wm8350->rev = WM8350_REV_G; 1188 break; 1189 default: 1190 /* For safety we refuse to run on unknown hardware */ 1191 dev_info(wm8350->dev, "Found unknown rev\n"); 1192 ret = -ENODEV; 1193 goto err; 1194 } 1195 } else { 1196 dev_info(wm8350->dev, "Device with ID %x is not a WM8350\n", 1197 id1); 1198 ret = -ENODEV; 1199 goto err; 1200 } 1201 1202 mode = id2 & WM8350_CONF_STS_MASK >> 10; 1203 mask = id2 & WM8350_CUST_ID_MASK; 1204 dev_info(wm8350->dev, "Config mode %d, ROM mask %d\n", mode, mask); 1205 1206 ret = wm8350_create_cache(wm8350, mode); 1207 if (ret < 0) { 1208 printk(KERN_ERR "wm8350: failed to create register cache\n"); 1209 return ret; 1210 } 1211 1212 if (pdata->init) { 1213 ret = pdata->init(wm8350); 1214 if (ret != 0) { 1215 dev_err(wm8350->dev, "Platform init() failed: %d\n", 1216 ret); 1217 goto err; 1218 } 1219 } 1220 1221 mutex_init(&wm8350->irq_mutex); 1222 INIT_WORK(&wm8350->irq_work, wm8350_irq_worker); 1223 if (irq) { 1224 ret = request_irq(irq, wm8350_irq, 0, 1225 "wm8350", wm8350); 1226 if (ret != 0) { 1227 dev_err(wm8350->dev, "Failed to request IRQ: %d\n", 1228 ret); 1229 goto err; 1230 } 1231 } else { 1232 dev_err(wm8350->dev, "No IRQ configured\n"); 1233 goto err; 1234 } 1235 wm8350->chip_irq = irq; 1236 1237 wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0x0); 1238 1239 wm8350_client_dev_register(wm8350, "wm8350-codec", 1240 &(wm8350->codec.pdev)); 1241 wm8350_client_dev_register(wm8350, "wm8350-gpio", 1242 &(wm8350->gpio.pdev)); 1243 wm8350_client_dev_register(wm8350, "wm8350-power", 1244 &(wm8350->power.pdev)); 1245 wm8350_client_dev_register(wm8350, "wm8350-rtc", &(wm8350->rtc.pdev)); 1246 wm8350_client_dev_register(wm8350, "wm8350-wdt", &(wm8350->wdt.pdev)); 1247 1248 return 0; 1249 1250 err: 1251 kfree(wm8350->reg_cache); 1252 return ret; 1253 } 1254 EXPORT_SYMBOL_GPL(wm8350_device_init); 1255 1256 void wm8350_device_exit(struct wm8350 *wm8350) 1257 { 1258 int i; 1259 1260 for (i = 0; i < ARRAY_SIZE(wm8350->pmic.pdev); i++) 1261 platform_device_unregister(wm8350->pmic.pdev[i]); 1262 1263 platform_device_unregister(wm8350->wdt.pdev); 1264 platform_device_unregister(wm8350->rtc.pdev); 1265 platform_device_unregister(wm8350->power.pdev); 1266 platform_device_unregister(wm8350->gpio.pdev); 1267 platform_device_unregister(wm8350->codec.pdev); 1268 1269 free_irq(wm8350->chip_irq, wm8350); 1270 flush_work(&wm8350->irq_work); 1271 kfree(wm8350->reg_cache); 1272 } 1273 EXPORT_SYMBOL_GPL(wm8350_device_exit); 1274 1275 MODULE_DESCRIPTION("WM8350 AudioPlus PMIC core driver"); 1276 MODULE_LICENSE("GPL"); 1277