1 /* 2 * wm831x-irq.c -- Interrupt controller support for Wolfson WM831x PMICs 3 * 4 * Copyright 2009 Wolfson Microelectronics PLC. 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/i2c.h> 18 #include <linux/irq.h> 19 #include <linux/mfd/core.h> 20 #include <linux/interrupt.h> 21 22 #include <linux/mfd/wm831x/core.h> 23 #include <linux/mfd/wm831x/pdata.h> 24 #include <linux/mfd/wm831x/gpio.h> 25 #include <linux/mfd/wm831x/irq.h> 26 27 #include <linux/delay.h> 28 29 struct wm831x_irq_data { 30 int primary; 31 int reg; 32 int mask; 33 }; 34 35 static struct wm831x_irq_data wm831x_irqs[] = { 36 [WM831X_IRQ_TEMP_THW] = { 37 .primary = WM831X_TEMP_INT, 38 .reg = 1, 39 .mask = WM831X_TEMP_THW_EINT, 40 }, 41 [WM831X_IRQ_GPIO_1] = { 42 .primary = WM831X_GP_INT, 43 .reg = 5, 44 .mask = WM831X_GP1_EINT, 45 }, 46 [WM831X_IRQ_GPIO_2] = { 47 .primary = WM831X_GP_INT, 48 .reg = 5, 49 .mask = WM831X_GP2_EINT, 50 }, 51 [WM831X_IRQ_GPIO_3] = { 52 .primary = WM831X_GP_INT, 53 .reg = 5, 54 .mask = WM831X_GP3_EINT, 55 }, 56 [WM831X_IRQ_GPIO_4] = { 57 .primary = WM831X_GP_INT, 58 .reg = 5, 59 .mask = WM831X_GP4_EINT, 60 }, 61 [WM831X_IRQ_GPIO_5] = { 62 .primary = WM831X_GP_INT, 63 .reg = 5, 64 .mask = WM831X_GP5_EINT, 65 }, 66 [WM831X_IRQ_GPIO_6] = { 67 .primary = WM831X_GP_INT, 68 .reg = 5, 69 .mask = WM831X_GP6_EINT, 70 }, 71 [WM831X_IRQ_GPIO_7] = { 72 .primary = WM831X_GP_INT, 73 .reg = 5, 74 .mask = WM831X_GP7_EINT, 75 }, 76 [WM831X_IRQ_GPIO_8] = { 77 .primary = WM831X_GP_INT, 78 .reg = 5, 79 .mask = WM831X_GP8_EINT, 80 }, 81 [WM831X_IRQ_GPIO_9] = { 82 .primary = WM831X_GP_INT, 83 .reg = 5, 84 .mask = WM831X_GP9_EINT, 85 }, 86 [WM831X_IRQ_GPIO_10] = { 87 .primary = WM831X_GP_INT, 88 .reg = 5, 89 .mask = WM831X_GP10_EINT, 90 }, 91 [WM831X_IRQ_GPIO_11] = { 92 .primary = WM831X_GP_INT, 93 .reg = 5, 94 .mask = WM831X_GP11_EINT, 95 }, 96 [WM831X_IRQ_GPIO_12] = { 97 .primary = WM831X_GP_INT, 98 .reg = 5, 99 .mask = WM831X_GP12_EINT, 100 }, 101 [WM831X_IRQ_GPIO_13] = { 102 .primary = WM831X_GP_INT, 103 .reg = 5, 104 .mask = WM831X_GP13_EINT, 105 }, 106 [WM831X_IRQ_GPIO_14] = { 107 .primary = WM831X_GP_INT, 108 .reg = 5, 109 .mask = WM831X_GP14_EINT, 110 }, 111 [WM831X_IRQ_GPIO_15] = { 112 .primary = WM831X_GP_INT, 113 .reg = 5, 114 .mask = WM831X_GP15_EINT, 115 }, 116 [WM831X_IRQ_GPIO_16] = { 117 .primary = WM831X_GP_INT, 118 .reg = 5, 119 .mask = WM831X_GP16_EINT, 120 }, 121 [WM831X_IRQ_ON] = { 122 .primary = WM831X_ON_PIN_INT, 123 .reg = 1, 124 .mask = WM831X_ON_PIN_EINT, 125 }, 126 [WM831X_IRQ_PPM_SYSLO] = { 127 .primary = WM831X_PPM_INT, 128 .reg = 1, 129 .mask = WM831X_PPM_SYSLO_EINT, 130 }, 131 [WM831X_IRQ_PPM_PWR_SRC] = { 132 .primary = WM831X_PPM_INT, 133 .reg = 1, 134 .mask = WM831X_PPM_PWR_SRC_EINT, 135 }, 136 [WM831X_IRQ_PPM_USB_CURR] = { 137 .primary = WM831X_PPM_INT, 138 .reg = 1, 139 .mask = WM831X_PPM_USB_CURR_EINT, 140 }, 141 [WM831X_IRQ_WDOG_TO] = { 142 .primary = WM831X_WDOG_INT, 143 .reg = 1, 144 .mask = WM831X_WDOG_TO_EINT, 145 }, 146 [WM831X_IRQ_RTC_PER] = { 147 .primary = WM831X_RTC_INT, 148 .reg = 1, 149 .mask = WM831X_RTC_PER_EINT, 150 }, 151 [WM831X_IRQ_RTC_ALM] = { 152 .primary = WM831X_RTC_INT, 153 .reg = 1, 154 .mask = WM831X_RTC_ALM_EINT, 155 }, 156 [WM831X_IRQ_CHG_BATT_HOT] = { 157 .primary = WM831X_CHG_INT, 158 .reg = 2, 159 .mask = WM831X_CHG_BATT_HOT_EINT, 160 }, 161 [WM831X_IRQ_CHG_BATT_COLD] = { 162 .primary = WM831X_CHG_INT, 163 .reg = 2, 164 .mask = WM831X_CHG_BATT_COLD_EINT, 165 }, 166 [WM831X_IRQ_CHG_BATT_FAIL] = { 167 .primary = WM831X_CHG_INT, 168 .reg = 2, 169 .mask = WM831X_CHG_BATT_FAIL_EINT, 170 }, 171 [WM831X_IRQ_CHG_OV] = { 172 .primary = WM831X_CHG_INT, 173 .reg = 2, 174 .mask = WM831X_CHG_OV_EINT, 175 }, 176 [WM831X_IRQ_CHG_END] = { 177 .primary = WM831X_CHG_INT, 178 .reg = 2, 179 .mask = WM831X_CHG_END_EINT, 180 }, 181 [WM831X_IRQ_CHG_TO] = { 182 .primary = WM831X_CHG_INT, 183 .reg = 2, 184 .mask = WM831X_CHG_TO_EINT, 185 }, 186 [WM831X_IRQ_CHG_MODE] = { 187 .primary = WM831X_CHG_INT, 188 .reg = 2, 189 .mask = WM831X_CHG_MODE_EINT, 190 }, 191 [WM831X_IRQ_CHG_START] = { 192 .primary = WM831X_CHG_INT, 193 .reg = 2, 194 .mask = WM831X_CHG_START_EINT, 195 }, 196 [WM831X_IRQ_TCHDATA] = { 197 .primary = WM831X_TCHDATA_INT, 198 .reg = 1, 199 .mask = WM831X_TCHDATA_EINT, 200 }, 201 [WM831X_IRQ_TCHPD] = { 202 .primary = WM831X_TCHPD_INT, 203 .reg = 1, 204 .mask = WM831X_TCHPD_EINT, 205 }, 206 [WM831X_IRQ_AUXADC_DATA] = { 207 .primary = WM831X_AUXADC_INT, 208 .reg = 1, 209 .mask = WM831X_AUXADC_DATA_EINT, 210 }, 211 [WM831X_IRQ_AUXADC_DCOMP1] = { 212 .primary = WM831X_AUXADC_INT, 213 .reg = 1, 214 .mask = WM831X_AUXADC_DCOMP1_EINT, 215 }, 216 [WM831X_IRQ_AUXADC_DCOMP2] = { 217 .primary = WM831X_AUXADC_INT, 218 .reg = 1, 219 .mask = WM831X_AUXADC_DCOMP2_EINT, 220 }, 221 [WM831X_IRQ_AUXADC_DCOMP3] = { 222 .primary = WM831X_AUXADC_INT, 223 .reg = 1, 224 .mask = WM831X_AUXADC_DCOMP3_EINT, 225 }, 226 [WM831X_IRQ_AUXADC_DCOMP4] = { 227 .primary = WM831X_AUXADC_INT, 228 .reg = 1, 229 .mask = WM831X_AUXADC_DCOMP4_EINT, 230 }, 231 [WM831X_IRQ_CS1] = { 232 .primary = WM831X_CS_INT, 233 .reg = 2, 234 .mask = WM831X_CS1_EINT, 235 }, 236 [WM831X_IRQ_CS2] = { 237 .primary = WM831X_CS_INT, 238 .reg = 2, 239 .mask = WM831X_CS2_EINT, 240 }, 241 [WM831X_IRQ_HC_DC1] = { 242 .primary = WM831X_HC_INT, 243 .reg = 4, 244 .mask = WM831X_HC_DC1_EINT, 245 }, 246 [WM831X_IRQ_HC_DC2] = { 247 .primary = WM831X_HC_INT, 248 .reg = 4, 249 .mask = WM831X_HC_DC2_EINT, 250 }, 251 [WM831X_IRQ_UV_LDO1] = { 252 .primary = WM831X_UV_INT, 253 .reg = 3, 254 .mask = WM831X_UV_LDO1_EINT, 255 }, 256 [WM831X_IRQ_UV_LDO2] = { 257 .primary = WM831X_UV_INT, 258 .reg = 3, 259 .mask = WM831X_UV_LDO2_EINT, 260 }, 261 [WM831X_IRQ_UV_LDO3] = { 262 .primary = WM831X_UV_INT, 263 .reg = 3, 264 .mask = WM831X_UV_LDO3_EINT, 265 }, 266 [WM831X_IRQ_UV_LDO4] = { 267 .primary = WM831X_UV_INT, 268 .reg = 3, 269 .mask = WM831X_UV_LDO4_EINT, 270 }, 271 [WM831X_IRQ_UV_LDO5] = { 272 .primary = WM831X_UV_INT, 273 .reg = 3, 274 .mask = WM831X_UV_LDO5_EINT, 275 }, 276 [WM831X_IRQ_UV_LDO6] = { 277 .primary = WM831X_UV_INT, 278 .reg = 3, 279 .mask = WM831X_UV_LDO6_EINT, 280 }, 281 [WM831X_IRQ_UV_LDO7] = { 282 .primary = WM831X_UV_INT, 283 .reg = 3, 284 .mask = WM831X_UV_LDO7_EINT, 285 }, 286 [WM831X_IRQ_UV_LDO8] = { 287 .primary = WM831X_UV_INT, 288 .reg = 3, 289 .mask = WM831X_UV_LDO8_EINT, 290 }, 291 [WM831X_IRQ_UV_LDO9] = { 292 .primary = WM831X_UV_INT, 293 .reg = 3, 294 .mask = WM831X_UV_LDO9_EINT, 295 }, 296 [WM831X_IRQ_UV_LDO10] = { 297 .primary = WM831X_UV_INT, 298 .reg = 3, 299 .mask = WM831X_UV_LDO10_EINT, 300 }, 301 [WM831X_IRQ_UV_DC1] = { 302 .primary = WM831X_UV_INT, 303 .reg = 4, 304 .mask = WM831X_UV_DC1_EINT, 305 }, 306 [WM831X_IRQ_UV_DC2] = { 307 .primary = WM831X_UV_INT, 308 .reg = 4, 309 .mask = WM831X_UV_DC2_EINT, 310 }, 311 [WM831X_IRQ_UV_DC3] = { 312 .primary = WM831X_UV_INT, 313 .reg = 4, 314 .mask = WM831X_UV_DC3_EINT, 315 }, 316 [WM831X_IRQ_UV_DC4] = { 317 .primary = WM831X_UV_INT, 318 .reg = 4, 319 .mask = WM831X_UV_DC4_EINT, 320 }, 321 }; 322 323 static inline int irq_data_to_status_reg(struct wm831x_irq_data *irq_data) 324 { 325 return WM831X_INTERRUPT_STATUS_1 - 1 + irq_data->reg; 326 } 327 328 static inline struct wm831x_irq_data *irq_to_wm831x_irq(struct wm831x *wm831x, 329 int irq) 330 { 331 return &wm831x_irqs[irq - wm831x->irq_base]; 332 } 333 334 static void wm831x_irq_lock(struct irq_data *data) 335 { 336 struct wm831x *wm831x = irq_data_get_irq_chip_data(data); 337 338 mutex_lock(&wm831x->irq_lock); 339 } 340 341 static void wm831x_irq_sync_unlock(struct irq_data *data) 342 { 343 struct wm831x *wm831x = irq_data_get_irq_chip_data(data); 344 int i; 345 346 for (i = 0; i < ARRAY_SIZE(wm831x->gpio_update); i++) { 347 if (wm831x->gpio_update[i]) { 348 wm831x_set_bits(wm831x, WM831X_GPIO1_CONTROL + i, 349 WM831X_GPN_INT_MODE | WM831X_GPN_POL, 350 wm831x->gpio_update[i]); 351 wm831x->gpio_update[i] = 0; 352 } 353 } 354 355 for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) { 356 /* If there's been a change in the mask write it back 357 * to the hardware. */ 358 if (wm831x->irq_masks_cur[i] != wm831x->irq_masks_cache[i]) { 359 dev_dbg(wm831x->dev, "IRQ mask sync: %x = %x\n", 360 WM831X_INTERRUPT_STATUS_1_MASK + i, 361 wm831x->irq_masks_cur[i]); 362 363 wm831x->irq_masks_cache[i] = wm831x->irq_masks_cur[i]; 364 wm831x_reg_write(wm831x, 365 WM831X_INTERRUPT_STATUS_1_MASK + i, 366 wm831x->irq_masks_cur[i]); 367 } 368 } 369 370 mutex_unlock(&wm831x->irq_lock); 371 } 372 373 static void wm831x_irq_enable(struct irq_data *data) 374 { 375 struct wm831x *wm831x = irq_data_get_irq_chip_data(data); 376 struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x, 377 data->irq); 378 379 wm831x->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask; 380 } 381 382 static void wm831x_irq_disable(struct irq_data *data) 383 { 384 struct wm831x *wm831x = irq_data_get_irq_chip_data(data); 385 struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x, 386 data->irq); 387 388 wm831x->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask; 389 } 390 391 static int wm831x_irq_set_type(struct irq_data *data, unsigned int type) 392 { 393 struct wm831x *wm831x = irq_data_get_irq_chip_data(data); 394 int irq; 395 396 irq = data->irq - wm831x->irq_base; 397 398 if (irq < WM831X_IRQ_GPIO_1 || irq > WM831X_IRQ_GPIO_11) { 399 /* Ignore internal-only IRQs */ 400 if (irq >= 0 && irq < WM831X_NUM_IRQS) 401 return 0; 402 else 403 return -EINVAL; 404 } 405 406 /* Rebase the IRQ into the GPIO range so we've got a sensible array 407 * index. 408 */ 409 irq -= WM831X_IRQ_GPIO_1; 410 411 /* We set the high bit to flag that we need an update; don't 412 * do the update here as we can be called with the bus lock 413 * held. 414 */ 415 switch (type) { 416 case IRQ_TYPE_EDGE_BOTH: 417 wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_INT_MODE; 418 wm831x->gpio_level[irq] = false; 419 break; 420 case IRQ_TYPE_EDGE_RISING: 421 wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_POL; 422 wm831x->gpio_level[irq] = false; 423 break; 424 case IRQ_TYPE_EDGE_FALLING: 425 wm831x->gpio_update[irq] = 0x10000; 426 wm831x->gpio_level[irq] = false; 427 break; 428 case IRQ_TYPE_LEVEL_HIGH: 429 wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_POL; 430 wm831x->gpio_level[irq] = true; 431 break; 432 default: 433 return -EINVAL; 434 } 435 436 return 0; 437 } 438 439 static struct irq_chip wm831x_irq_chip = { 440 .name = "wm831x", 441 .irq_bus_lock = wm831x_irq_lock, 442 .irq_bus_sync_unlock = wm831x_irq_sync_unlock, 443 .irq_disable = wm831x_irq_disable, 444 .irq_enable = wm831x_irq_enable, 445 .irq_set_type = wm831x_irq_set_type, 446 }; 447 448 /* The processing of the primary interrupt occurs in a thread so that 449 * we can interact with the device over I2C or SPI. */ 450 static irqreturn_t wm831x_irq_thread(int irq, void *data) 451 { 452 struct wm831x *wm831x = data; 453 unsigned int i; 454 int primary, status_addr, ret; 455 int status_regs[WM831X_NUM_IRQ_REGS] = { 0 }; 456 int read[WM831X_NUM_IRQ_REGS] = { 0 }; 457 int *status; 458 459 primary = wm831x_reg_read(wm831x, WM831X_SYSTEM_INTERRUPTS); 460 if (primary < 0) { 461 dev_err(wm831x->dev, "Failed to read system interrupt: %d\n", 462 primary); 463 goto out; 464 } 465 466 /* The touch interrupts are visible in the primary register as 467 * an optimisation; open code this to avoid complicating the 468 * main handling loop and so we can also skip iterating the 469 * descriptors. 470 */ 471 if (primary & WM831X_TCHPD_INT) 472 handle_nested_irq(wm831x->irq_base + WM831X_IRQ_TCHPD); 473 if (primary & WM831X_TCHDATA_INT) 474 handle_nested_irq(wm831x->irq_base + WM831X_IRQ_TCHDATA); 475 if (primary & (WM831X_TCHDATA_EINT | WM831X_TCHPD_EINT)) 476 goto out; 477 478 for (i = 0; i < ARRAY_SIZE(wm831x_irqs); i++) { 479 int offset = wm831x_irqs[i].reg - 1; 480 481 if (!(primary & wm831x_irqs[i].primary)) 482 continue; 483 484 status = &status_regs[offset]; 485 486 /* Hopefully there should only be one register to read 487 * each time otherwise we ought to do a block read. */ 488 if (!read[offset]) { 489 status_addr = irq_data_to_status_reg(&wm831x_irqs[i]); 490 491 *status = wm831x_reg_read(wm831x, status_addr); 492 if (*status < 0) { 493 dev_err(wm831x->dev, 494 "Failed to read IRQ status: %d\n", 495 *status); 496 goto out; 497 } 498 499 read[offset] = 1; 500 501 /* Ignore any bits that we don't think are masked */ 502 *status &= ~wm831x->irq_masks_cur[offset]; 503 504 /* Acknowledge now so we don't miss 505 * notifications while we handle. 506 */ 507 wm831x_reg_write(wm831x, status_addr, *status); 508 } 509 510 if (*status & wm831x_irqs[i].mask) 511 handle_nested_irq(wm831x->irq_base + i); 512 513 /* Simulate an edge triggered IRQ by polling the input 514 * status. This is sucky but improves interoperability. 515 */ 516 if (primary == WM831X_GP_INT && 517 wm831x->gpio_level[i - WM831X_IRQ_GPIO_1]) { 518 ret = wm831x_reg_read(wm831x, WM831X_GPIO_LEVEL); 519 while (ret & 1 << (i - WM831X_IRQ_GPIO_1)) { 520 handle_nested_irq(wm831x->irq_base + i); 521 ret = wm831x_reg_read(wm831x, 522 WM831X_GPIO_LEVEL); 523 } 524 } 525 } 526 527 out: 528 return IRQ_HANDLED; 529 } 530 531 int wm831x_irq_init(struct wm831x *wm831x, int irq) 532 { 533 struct wm831x_pdata *pdata = wm831x->dev->platform_data; 534 int i, cur_irq, ret; 535 536 mutex_init(&wm831x->irq_lock); 537 538 /* Mask the individual interrupt sources */ 539 for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) { 540 wm831x->irq_masks_cur[i] = 0xffff; 541 wm831x->irq_masks_cache[i] = 0xffff; 542 wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1_MASK + i, 543 0xffff); 544 } 545 546 /* Try to dynamically allocate IRQs if no base is specified */ 547 if (!pdata || !pdata->irq_base) 548 wm831x->irq_base = -1; 549 else 550 wm831x->irq_base = pdata->irq_base; 551 552 wm831x->irq_base = irq_alloc_descs(wm831x->irq_base, 0, 553 WM831X_NUM_IRQS, 0); 554 if (wm831x->irq_base < 0) { 555 dev_warn(wm831x->dev, "Failed to allocate IRQs: %d\n", 556 wm831x->irq_base); 557 wm831x->irq_base = 0; 558 return 0; 559 } 560 561 if (pdata && pdata->irq_cmos) 562 i = 0; 563 else 564 i = WM831X_IRQ_OD; 565 566 wm831x_set_bits(wm831x, WM831X_IRQ_CONFIG, 567 WM831X_IRQ_OD, i); 568 569 /* Try to flag /IRQ as a wake source; there are a number of 570 * unconditional wake sources in the PMIC so this isn't 571 * conditional but we don't actually care *too* much if it 572 * fails. 573 */ 574 ret = enable_irq_wake(irq); 575 if (ret != 0) { 576 dev_warn(wm831x->dev, "Can't enable IRQ as wake source: %d\n", 577 ret); 578 } 579 580 wm831x->irq = irq; 581 582 /* Register them with genirq */ 583 for (cur_irq = wm831x->irq_base; 584 cur_irq < ARRAY_SIZE(wm831x_irqs) + wm831x->irq_base; 585 cur_irq++) { 586 irq_set_chip_data(cur_irq, wm831x); 587 irq_set_chip_and_handler(cur_irq, &wm831x_irq_chip, 588 handle_edge_irq); 589 irq_set_nested_thread(cur_irq, 1); 590 591 /* ARM needs us to explicitly flag the IRQ as valid 592 * and will set them noprobe when we do so. */ 593 #ifdef CONFIG_ARM 594 set_irq_flags(cur_irq, IRQF_VALID); 595 #else 596 irq_set_noprobe(cur_irq); 597 #endif 598 } 599 600 if (irq) { 601 ret = request_threaded_irq(irq, NULL, wm831x_irq_thread, 602 IRQF_TRIGGER_LOW | IRQF_ONESHOT, 603 "wm831x", wm831x); 604 if (ret != 0) { 605 dev_err(wm831x->dev, "Failed to request IRQ %d: %d\n", 606 irq, ret); 607 return ret; 608 } 609 } else { 610 dev_warn(wm831x->dev, 611 "No interrupt specified - functionality limited\n"); 612 } 613 614 /* Enable top level interrupts, we mask at secondary level */ 615 wm831x_reg_write(wm831x, WM831X_SYSTEM_INTERRUPTS_MASK, 0); 616 617 return 0; 618 } 619 620 void wm831x_irq_exit(struct wm831x *wm831x) 621 { 622 if (wm831x->irq) 623 free_irq(wm831x->irq, wm831x); 624 } 625