17d4d0a3eSMark Brown /* 27d4d0a3eSMark Brown * wm831x-irq.c -- Interrupt controller support for Wolfson WM831x PMICs 37d4d0a3eSMark Brown * 47d4d0a3eSMark Brown * Copyright 2009 Wolfson Microelectronics PLC. 57d4d0a3eSMark Brown * 67d4d0a3eSMark Brown * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 77d4d0a3eSMark Brown * 87d4d0a3eSMark Brown * This program is free software; you can redistribute it and/or modify it 97d4d0a3eSMark Brown * under the terms of the GNU General Public License as published by the 107d4d0a3eSMark Brown * Free Software Foundation; either version 2 of the License, or (at your 117d4d0a3eSMark Brown * option) any later version. 127d4d0a3eSMark Brown * 137d4d0a3eSMark Brown */ 147d4d0a3eSMark Brown 157d4d0a3eSMark Brown #include <linux/kernel.h> 167d4d0a3eSMark Brown #include <linux/module.h> 177d4d0a3eSMark Brown #include <linux/i2c.h> 185fb4d38bSMark Brown #include <linux/irq.h> 197d4d0a3eSMark Brown #include <linux/mfd/core.h> 207d4d0a3eSMark Brown #include <linux/interrupt.h> 217d4d0a3eSMark Brown 227d4d0a3eSMark Brown #include <linux/mfd/wm831x/core.h> 237d4d0a3eSMark Brown #include <linux/mfd/wm831x/pdata.h> 24896060c7SMark Brown #include <linux/mfd/wm831x/gpio.h> 257d4d0a3eSMark Brown #include <linux/mfd/wm831x/irq.h> 267d4d0a3eSMark Brown 277d4d0a3eSMark Brown #include <linux/delay.h> 287d4d0a3eSMark Brown 297d4d0a3eSMark Brown struct wm831x_irq_data { 307d4d0a3eSMark Brown int primary; 317d4d0a3eSMark Brown int reg; 327d4d0a3eSMark Brown int mask; 337d4d0a3eSMark Brown }; 347d4d0a3eSMark Brown 357d4d0a3eSMark Brown static struct wm831x_irq_data wm831x_irqs[] = { 367d4d0a3eSMark Brown [WM831X_IRQ_TEMP_THW] = { 377d4d0a3eSMark Brown .primary = WM831X_TEMP_INT, 387d4d0a3eSMark Brown .reg = 1, 397d4d0a3eSMark Brown .mask = WM831X_TEMP_THW_EINT, 407d4d0a3eSMark Brown }, 417d4d0a3eSMark Brown [WM831X_IRQ_GPIO_1] = { 427d4d0a3eSMark Brown .primary = WM831X_GP_INT, 437d4d0a3eSMark Brown .reg = 5, 447d4d0a3eSMark Brown .mask = WM831X_GP1_EINT, 457d4d0a3eSMark Brown }, 467d4d0a3eSMark Brown [WM831X_IRQ_GPIO_2] = { 477d4d0a3eSMark Brown .primary = WM831X_GP_INT, 487d4d0a3eSMark Brown .reg = 5, 497d4d0a3eSMark Brown .mask = WM831X_GP2_EINT, 507d4d0a3eSMark Brown }, 517d4d0a3eSMark Brown [WM831X_IRQ_GPIO_3] = { 527d4d0a3eSMark Brown .primary = WM831X_GP_INT, 537d4d0a3eSMark Brown .reg = 5, 547d4d0a3eSMark Brown .mask = WM831X_GP3_EINT, 557d4d0a3eSMark Brown }, 567d4d0a3eSMark Brown [WM831X_IRQ_GPIO_4] = { 577d4d0a3eSMark Brown .primary = WM831X_GP_INT, 587d4d0a3eSMark Brown .reg = 5, 597d4d0a3eSMark Brown .mask = WM831X_GP4_EINT, 607d4d0a3eSMark Brown }, 617d4d0a3eSMark Brown [WM831X_IRQ_GPIO_5] = { 627d4d0a3eSMark Brown .primary = WM831X_GP_INT, 637d4d0a3eSMark Brown .reg = 5, 647d4d0a3eSMark Brown .mask = WM831X_GP5_EINT, 657d4d0a3eSMark Brown }, 667d4d0a3eSMark Brown [WM831X_IRQ_GPIO_6] = { 677d4d0a3eSMark Brown .primary = WM831X_GP_INT, 687d4d0a3eSMark Brown .reg = 5, 697d4d0a3eSMark Brown .mask = WM831X_GP6_EINT, 707d4d0a3eSMark Brown }, 717d4d0a3eSMark Brown [WM831X_IRQ_GPIO_7] = { 727d4d0a3eSMark Brown .primary = WM831X_GP_INT, 737d4d0a3eSMark Brown .reg = 5, 747d4d0a3eSMark Brown .mask = WM831X_GP7_EINT, 757d4d0a3eSMark Brown }, 767d4d0a3eSMark Brown [WM831X_IRQ_GPIO_8] = { 777d4d0a3eSMark Brown .primary = WM831X_GP_INT, 787d4d0a3eSMark Brown .reg = 5, 797d4d0a3eSMark Brown .mask = WM831X_GP8_EINT, 807d4d0a3eSMark Brown }, 817d4d0a3eSMark Brown [WM831X_IRQ_GPIO_9] = { 827d4d0a3eSMark Brown .primary = WM831X_GP_INT, 837d4d0a3eSMark Brown .reg = 5, 847d4d0a3eSMark Brown .mask = WM831X_GP9_EINT, 857d4d0a3eSMark Brown }, 867d4d0a3eSMark Brown [WM831X_IRQ_GPIO_10] = { 877d4d0a3eSMark Brown .primary = WM831X_GP_INT, 887d4d0a3eSMark Brown .reg = 5, 897d4d0a3eSMark Brown .mask = WM831X_GP10_EINT, 907d4d0a3eSMark Brown }, 917d4d0a3eSMark Brown [WM831X_IRQ_GPIO_11] = { 927d4d0a3eSMark Brown .primary = WM831X_GP_INT, 937d4d0a3eSMark Brown .reg = 5, 947d4d0a3eSMark Brown .mask = WM831X_GP11_EINT, 957d4d0a3eSMark Brown }, 967d4d0a3eSMark Brown [WM831X_IRQ_GPIO_12] = { 977d4d0a3eSMark Brown .primary = WM831X_GP_INT, 987d4d0a3eSMark Brown .reg = 5, 997d4d0a3eSMark Brown .mask = WM831X_GP12_EINT, 1007d4d0a3eSMark Brown }, 1017d4d0a3eSMark Brown [WM831X_IRQ_GPIO_13] = { 1027d4d0a3eSMark Brown .primary = WM831X_GP_INT, 1037d4d0a3eSMark Brown .reg = 5, 1047d4d0a3eSMark Brown .mask = WM831X_GP13_EINT, 1057d4d0a3eSMark Brown }, 1067d4d0a3eSMark Brown [WM831X_IRQ_GPIO_14] = { 1077d4d0a3eSMark Brown .primary = WM831X_GP_INT, 1087d4d0a3eSMark Brown .reg = 5, 1097d4d0a3eSMark Brown .mask = WM831X_GP14_EINT, 1107d4d0a3eSMark Brown }, 1117d4d0a3eSMark Brown [WM831X_IRQ_GPIO_15] = { 1127d4d0a3eSMark Brown .primary = WM831X_GP_INT, 1137d4d0a3eSMark Brown .reg = 5, 1147d4d0a3eSMark Brown .mask = WM831X_GP15_EINT, 1157d4d0a3eSMark Brown }, 1167d4d0a3eSMark Brown [WM831X_IRQ_GPIO_16] = { 1177d4d0a3eSMark Brown .primary = WM831X_GP_INT, 1187d4d0a3eSMark Brown .reg = 5, 1197d4d0a3eSMark Brown .mask = WM831X_GP16_EINT, 1207d4d0a3eSMark Brown }, 1217d4d0a3eSMark Brown [WM831X_IRQ_ON] = { 1227d4d0a3eSMark Brown .primary = WM831X_ON_PIN_INT, 1237d4d0a3eSMark Brown .reg = 1, 1247d4d0a3eSMark Brown .mask = WM831X_ON_PIN_EINT, 1257d4d0a3eSMark Brown }, 1267d4d0a3eSMark Brown [WM831X_IRQ_PPM_SYSLO] = { 1277d4d0a3eSMark Brown .primary = WM831X_PPM_INT, 1287d4d0a3eSMark Brown .reg = 1, 1297d4d0a3eSMark Brown .mask = WM831X_PPM_SYSLO_EINT, 1307d4d0a3eSMark Brown }, 1317d4d0a3eSMark Brown [WM831X_IRQ_PPM_PWR_SRC] = { 1327d4d0a3eSMark Brown .primary = WM831X_PPM_INT, 1337d4d0a3eSMark Brown .reg = 1, 1347d4d0a3eSMark Brown .mask = WM831X_PPM_PWR_SRC_EINT, 1357d4d0a3eSMark Brown }, 1367d4d0a3eSMark Brown [WM831X_IRQ_PPM_USB_CURR] = { 1377d4d0a3eSMark Brown .primary = WM831X_PPM_INT, 1387d4d0a3eSMark Brown .reg = 1, 1397d4d0a3eSMark Brown .mask = WM831X_PPM_USB_CURR_EINT, 1407d4d0a3eSMark Brown }, 1417d4d0a3eSMark Brown [WM831X_IRQ_WDOG_TO] = { 1427d4d0a3eSMark Brown .primary = WM831X_WDOG_INT, 1437d4d0a3eSMark Brown .reg = 1, 1447d4d0a3eSMark Brown .mask = WM831X_WDOG_TO_EINT, 1457d4d0a3eSMark Brown }, 1467d4d0a3eSMark Brown [WM831X_IRQ_RTC_PER] = { 1477d4d0a3eSMark Brown .primary = WM831X_RTC_INT, 1487d4d0a3eSMark Brown .reg = 1, 1497d4d0a3eSMark Brown .mask = WM831X_RTC_PER_EINT, 1507d4d0a3eSMark Brown }, 1517d4d0a3eSMark Brown [WM831X_IRQ_RTC_ALM] = { 1527d4d0a3eSMark Brown .primary = WM831X_RTC_INT, 1537d4d0a3eSMark Brown .reg = 1, 1547d4d0a3eSMark Brown .mask = WM831X_RTC_ALM_EINT, 1557d4d0a3eSMark Brown }, 1567d4d0a3eSMark Brown [WM831X_IRQ_CHG_BATT_HOT] = { 1577d4d0a3eSMark Brown .primary = WM831X_CHG_INT, 1587d4d0a3eSMark Brown .reg = 2, 1597d4d0a3eSMark Brown .mask = WM831X_CHG_BATT_HOT_EINT, 1607d4d0a3eSMark Brown }, 1617d4d0a3eSMark Brown [WM831X_IRQ_CHG_BATT_COLD] = { 1627d4d0a3eSMark Brown .primary = WM831X_CHG_INT, 1637d4d0a3eSMark Brown .reg = 2, 1647d4d0a3eSMark Brown .mask = WM831X_CHG_BATT_COLD_EINT, 1657d4d0a3eSMark Brown }, 1667d4d0a3eSMark Brown [WM831X_IRQ_CHG_BATT_FAIL] = { 1677d4d0a3eSMark Brown .primary = WM831X_CHG_INT, 1687d4d0a3eSMark Brown .reg = 2, 1697d4d0a3eSMark Brown .mask = WM831X_CHG_BATT_FAIL_EINT, 1707d4d0a3eSMark Brown }, 1717d4d0a3eSMark Brown [WM831X_IRQ_CHG_OV] = { 1727d4d0a3eSMark Brown .primary = WM831X_CHG_INT, 1737d4d0a3eSMark Brown .reg = 2, 1747d4d0a3eSMark Brown .mask = WM831X_CHG_OV_EINT, 1757d4d0a3eSMark Brown }, 1767d4d0a3eSMark Brown [WM831X_IRQ_CHG_END] = { 1777d4d0a3eSMark Brown .primary = WM831X_CHG_INT, 1787d4d0a3eSMark Brown .reg = 2, 1797d4d0a3eSMark Brown .mask = WM831X_CHG_END_EINT, 1807d4d0a3eSMark Brown }, 1817d4d0a3eSMark Brown [WM831X_IRQ_CHG_TO] = { 1827d4d0a3eSMark Brown .primary = WM831X_CHG_INT, 1837d4d0a3eSMark Brown .reg = 2, 1847d4d0a3eSMark Brown .mask = WM831X_CHG_TO_EINT, 1857d4d0a3eSMark Brown }, 1867d4d0a3eSMark Brown [WM831X_IRQ_CHG_MODE] = { 1877d4d0a3eSMark Brown .primary = WM831X_CHG_INT, 1887d4d0a3eSMark Brown .reg = 2, 1897d4d0a3eSMark Brown .mask = WM831X_CHG_MODE_EINT, 1907d4d0a3eSMark Brown }, 1917d4d0a3eSMark Brown [WM831X_IRQ_CHG_START] = { 1927d4d0a3eSMark Brown .primary = WM831X_CHG_INT, 1937d4d0a3eSMark Brown .reg = 2, 1947d4d0a3eSMark Brown .mask = WM831X_CHG_START_EINT, 1957d4d0a3eSMark Brown }, 1967d4d0a3eSMark Brown [WM831X_IRQ_TCHDATA] = { 1977d4d0a3eSMark Brown .primary = WM831X_TCHDATA_INT, 1987d4d0a3eSMark Brown .reg = 1, 1997d4d0a3eSMark Brown .mask = WM831X_TCHDATA_EINT, 2007d4d0a3eSMark Brown }, 2017d4d0a3eSMark Brown [WM831X_IRQ_TCHPD] = { 2027d4d0a3eSMark Brown .primary = WM831X_TCHPD_INT, 2037d4d0a3eSMark Brown .reg = 1, 2047d4d0a3eSMark Brown .mask = WM831X_TCHPD_EINT, 2057d4d0a3eSMark Brown }, 2067d4d0a3eSMark Brown [WM831X_IRQ_AUXADC_DATA] = { 2077d4d0a3eSMark Brown .primary = WM831X_AUXADC_INT, 2087d4d0a3eSMark Brown .reg = 1, 2097d4d0a3eSMark Brown .mask = WM831X_AUXADC_DATA_EINT, 2107d4d0a3eSMark Brown }, 2117d4d0a3eSMark Brown [WM831X_IRQ_AUXADC_DCOMP1] = { 2127d4d0a3eSMark Brown .primary = WM831X_AUXADC_INT, 2137d4d0a3eSMark Brown .reg = 1, 2147d4d0a3eSMark Brown .mask = WM831X_AUXADC_DCOMP1_EINT, 2157d4d0a3eSMark Brown }, 2167d4d0a3eSMark Brown [WM831X_IRQ_AUXADC_DCOMP2] = { 2177d4d0a3eSMark Brown .primary = WM831X_AUXADC_INT, 2187d4d0a3eSMark Brown .reg = 1, 2197d4d0a3eSMark Brown .mask = WM831X_AUXADC_DCOMP2_EINT, 2207d4d0a3eSMark Brown }, 2217d4d0a3eSMark Brown [WM831X_IRQ_AUXADC_DCOMP3] = { 2227d4d0a3eSMark Brown .primary = WM831X_AUXADC_INT, 2237d4d0a3eSMark Brown .reg = 1, 2247d4d0a3eSMark Brown .mask = WM831X_AUXADC_DCOMP3_EINT, 2257d4d0a3eSMark Brown }, 2267d4d0a3eSMark Brown [WM831X_IRQ_AUXADC_DCOMP4] = { 2277d4d0a3eSMark Brown .primary = WM831X_AUXADC_INT, 2287d4d0a3eSMark Brown .reg = 1, 2297d4d0a3eSMark Brown .mask = WM831X_AUXADC_DCOMP4_EINT, 2307d4d0a3eSMark Brown }, 2317d4d0a3eSMark Brown [WM831X_IRQ_CS1] = { 2327d4d0a3eSMark Brown .primary = WM831X_CS_INT, 2337d4d0a3eSMark Brown .reg = 2, 2347d4d0a3eSMark Brown .mask = WM831X_CS1_EINT, 2357d4d0a3eSMark Brown }, 2367d4d0a3eSMark Brown [WM831X_IRQ_CS2] = { 2377d4d0a3eSMark Brown .primary = WM831X_CS_INT, 2387d4d0a3eSMark Brown .reg = 2, 2397d4d0a3eSMark Brown .mask = WM831X_CS2_EINT, 2407d4d0a3eSMark Brown }, 2417d4d0a3eSMark Brown [WM831X_IRQ_HC_DC1] = { 2427d4d0a3eSMark Brown .primary = WM831X_HC_INT, 2437d4d0a3eSMark Brown .reg = 4, 2447d4d0a3eSMark Brown .mask = WM831X_HC_DC1_EINT, 2457d4d0a3eSMark Brown }, 2467d4d0a3eSMark Brown [WM831X_IRQ_HC_DC2] = { 2477d4d0a3eSMark Brown .primary = WM831X_HC_INT, 2487d4d0a3eSMark Brown .reg = 4, 2497d4d0a3eSMark Brown .mask = WM831X_HC_DC2_EINT, 2507d4d0a3eSMark Brown }, 2517d4d0a3eSMark Brown [WM831X_IRQ_UV_LDO1] = { 2527d4d0a3eSMark Brown .primary = WM831X_UV_INT, 2537d4d0a3eSMark Brown .reg = 3, 2547d4d0a3eSMark Brown .mask = WM831X_UV_LDO1_EINT, 2557d4d0a3eSMark Brown }, 2567d4d0a3eSMark Brown [WM831X_IRQ_UV_LDO2] = { 2577d4d0a3eSMark Brown .primary = WM831X_UV_INT, 2587d4d0a3eSMark Brown .reg = 3, 2597d4d0a3eSMark Brown .mask = WM831X_UV_LDO2_EINT, 2607d4d0a3eSMark Brown }, 2617d4d0a3eSMark Brown [WM831X_IRQ_UV_LDO3] = { 2627d4d0a3eSMark Brown .primary = WM831X_UV_INT, 2637d4d0a3eSMark Brown .reg = 3, 2647d4d0a3eSMark Brown .mask = WM831X_UV_LDO3_EINT, 2657d4d0a3eSMark Brown }, 2667d4d0a3eSMark Brown [WM831X_IRQ_UV_LDO4] = { 2677d4d0a3eSMark Brown .primary = WM831X_UV_INT, 2687d4d0a3eSMark Brown .reg = 3, 2697d4d0a3eSMark Brown .mask = WM831X_UV_LDO4_EINT, 2707d4d0a3eSMark Brown }, 2717d4d0a3eSMark Brown [WM831X_IRQ_UV_LDO5] = { 2727d4d0a3eSMark Brown .primary = WM831X_UV_INT, 2737d4d0a3eSMark Brown .reg = 3, 2747d4d0a3eSMark Brown .mask = WM831X_UV_LDO5_EINT, 2757d4d0a3eSMark Brown }, 2767d4d0a3eSMark Brown [WM831X_IRQ_UV_LDO6] = { 2777d4d0a3eSMark Brown .primary = WM831X_UV_INT, 2787d4d0a3eSMark Brown .reg = 3, 2797d4d0a3eSMark Brown .mask = WM831X_UV_LDO6_EINT, 2807d4d0a3eSMark Brown }, 2817d4d0a3eSMark Brown [WM831X_IRQ_UV_LDO7] = { 2827d4d0a3eSMark Brown .primary = WM831X_UV_INT, 2837d4d0a3eSMark Brown .reg = 3, 2847d4d0a3eSMark Brown .mask = WM831X_UV_LDO7_EINT, 2857d4d0a3eSMark Brown }, 2867d4d0a3eSMark Brown [WM831X_IRQ_UV_LDO8] = { 2877d4d0a3eSMark Brown .primary = WM831X_UV_INT, 2887d4d0a3eSMark Brown .reg = 3, 2897d4d0a3eSMark Brown .mask = WM831X_UV_LDO8_EINT, 2907d4d0a3eSMark Brown }, 2917d4d0a3eSMark Brown [WM831X_IRQ_UV_LDO9] = { 2927d4d0a3eSMark Brown .primary = WM831X_UV_INT, 2937d4d0a3eSMark Brown .reg = 3, 2947d4d0a3eSMark Brown .mask = WM831X_UV_LDO9_EINT, 2957d4d0a3eSMark Brown }, 2967d4d0a3eSMark Brown [WM831X_IRQ_UV_LDO10] = { 2977d4d0a3eSMark Brown .primary = WM831X_UV_INT, 2987d4d0a3eSMark Brown .reg = 3, 2997d4d0a3eSMark Brown .mask = WM831X_UV_LDO10_EINT, 3007d4d0a3eSMark Brown }, 3017d4d0a3eSMark Brown [WM831X_IRQ_UV_DC1] = { 3027d4d0a3eSMark Brown .primary = WM831X_UV_INT, 3037d4d0a3eSMark Brown .reg = 4, 3047d4d0a3eSMark Brown .mask = WM831X_UV_DC1_EINT, 3057d4d0a3eSMark Brown }, 3067d4d0a3eSMark Brown [WM831X_IRQ_UV_DC2] = { 3077d4d0a3eSMark Brown .primary = WM831X_UV_INT, 3087d4d0a3eSMark Brown .reg = 4, 3097d4d0a3eSMark Brown .mask = WM831X_UV_DC2_EINT, 3107d4d0a3eSMark Brown }, 3117d4d0a3eSMark Brown [WM831X_IRQ_UV_DC3] = { 3127d4d0a3eSMark Brown .primary = WM831X_UV_INT, 3137d4d0a3eSMark Brown .reg = 4, 3147d4d0a3eSMark Brown .mask = WM831X_UV_DC3_EINT, 3157d4d0a3eSMark Brown }, 3167d4d0a3eSMark Brown [WM831X_IRQ_UV_DC4] = { 3177d4d0a3eSMark Brown .primary = WM831X_UV_INT, 3187d4d0a3eSMark Brown .reg = 4, 3197d4d0a3eSMark Brown .mask = WM831X_UV_DC4_EINT, 3207d4d0a3eSMark Brown }, 3217d4d0a3eSMark Brown }; 3227d4d0a3eSMark Brown 3237d4d0a3eSMark Brown static inline int irq_data_to_status_reg(struct wm831x_irq_data *irq_data) 3247d4d0a3eSMark Brown { 3257d4d0a3eSMark Brown return WM831X_INTERRUPT_STATUS_1 - 1 + irq_data->reg; 3267d4d0a3eSMark Brown } 3277d4d0a3eSMark Brown 3287d4d0a3eSMark Brown static inline int irq_data_to_mask_reg(struct wm831x_irq_data *irq_data) 3297d4d0a3eSMark Brown { 3307d4d0a3eSMark Brown return WM831X_INTERRUPT_STATUS_1_MASK - 1 + irq_data->reg; 3317d4d0a3eSMark Brown } 3327d4d0a3eSMark Brown 3335fb4d38bSMark Brown static inline struct wm831x_irq_data *irq_to_wm831x_irq(struct wm831x *wm831x, 3345fb4d38bSMark Brown int irq) 3357d4d0a3eSMark Brown { 3365fb4d38bSMark Brown return &wm831x_irqs[irq - wm831x->irq_base]; 3377d4d0a3eSMark Brown } 3387d4d0a3eSMark Brown 339ba81cd39SMark Brown static void wm831x_irq_lock(struct irq_data *data) 3407d4d0a3eSMark Brown { 34125a947f8SMark Brown struct wm831x *wm831x = irq_data_get_irq_chip_data(data); 3427d4d0a3eSMark Brown 3437d4d0a3eSMark Brown mutex_lock(&wm831x->irq_lock); 3447d4d0a3eSMark Brown } 3457d4d0a3eSMark Brown 346ba81cd39SMark Brown static void wm831x_irq_sync_unlock(struct irq_data *data) 3477d4d0a3eSMark Brown { 34825a947f8SMark Brown struct wm831x *wm831x = irq_data_get_irq_chip_data(data); 3495fb4d38bSMark Brown int i; 3507d4d0a3eSMark Brown 351ca7a7182SMark Brown for (i = 0; i < ARRAY_SIZE(wm831x->gpio_update); i++) { 352ca7a7182SMark Brown if (wm831x->gpio_update[i]) { 353ca7a7182SMark Brown wm831x_set_bits(wm831x, WM831X_GPIO1_CONTROL + i, 354ca7a7182SMark Brown WM831X_GPN_INT_MODE | WM831X_GPN_POL, 355ca7a7182SMark Brown wm831x->gpio_update[i]); 356ca7a7182SMark Brown wm831x->gpio_update[i] = 0; 357ca7a7182SMark Brown } 358ca7a7182SMark Brown } 359ca7a7182SMark Brown 3605fb4d38bSMark Brown for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) { 3615fb4d38bSMark Brown /* If there's been a change in the mask write it back 3625fb4d38bSMark Brown * to the hardware. */ 3635fb4d38bSMark Brown if (wm831x->irq_masks_cur[i] != wm831x->irq_masks_cache[i]) { 364f624effbSMark Brown dev_dbg(wm831x->dev, "IRQ mask sync: %x = %x\n", 365f624effbSMark Brown WM831X_INTERRUPT_STATUS_1_MASK + i, 366f624effbSMark Brown wm831x->irq_masks_cur[i]); 367f624effbSMark Brown 3685fb4d38bSMark Brown wm831x->irq_masks_cache[i] = wm831x->irq_masks_cur[i]; 3695fb4d38bSMark Brown wm831x_reg_write(wm831x, 3705fb4d38bSMark Brown WM831X_INTERRUPT_STATUS_1_MASK + i, 3715fb4d38bSMark Brown wm831x->irq_masks_cur[i]); 3725fb4d38bSMark Brown } 3735fb4d38bSMark Brown } 3747d4d0a3eSMark Brown 3757d4d0a3eSMark Brown mutex_unlock(&wm831x->irq_lock); 3767d4d0a3eSMark Brown } 3777d4d0a3eSMark Brown 378f624effbSMark Brown static void wm831x_irq_enable(struct irq_data *data) 3797d4d0a3eSMark Brown { 38025a947f8SMark Brown struct wm831x *wm831x = irq_data_get_irq_chip_data(data); 381ba81cd39SMark Brown struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x, 382ba81cd39SMark Brown data->irq); 3837d4d0a3eSMark Brown 3845fb4d38bSMark Brown wm831x->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask; 3857d4d0a3eSMark Brown } 3867d4d0a3eSMark Brown 387f624effbSMark Brown static void wm831x_irq_disable(struct irq_data *data) 3887d4d0a3eSMark Brown { 38925a947f8SMark Brown struct wm831x *wm831x = irq_data_get_irq_chip_data(data); 390ba81cd39SMark Brown struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x, 391ba81cd39SMark Brown data->irq); 3925fb4d38bSMark Brown 3935fb4d38bSMark Brown wm831x->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask; 3945fb4d38bSMark Brown } 3955fb4d38bSMark Brown 396ba81cd39SMark Brown static int wm831x_irq_set_type(struct irq_data *data, unsigned int type) 397896060c7SMark Brown { 39825a947f8SMark Brown struct wm831x *wm831x = irq_data_get_irq_chip_data(data); 399ca7a7182SMark Brown int irq; 400896060c7SMark Brown 401ba81cd39SMark Brown irq = data->irq - wm831x->irq_base; 402896060c7SMark Brown 403c9d66d35SMark Brown if (irq < WM831X_IRQ_GPIO_1 || irq > WM831X_IRQ_GPIO_11) { 404c9d66d35SMark Brown /* Ignore internal-only IRQs */ 405c9d66d35SMark Brown if (irq >= 0 && irq < WM831X_NUM_IRQS) 406c9d66d35SMark Brown return 0; 407c9d66d35SMark Brown else 408896060c7SMark Brown return -EINVAL; 409c9d66d35SMark Brown } 410896060c7SMark Brown 41108256712SDimitris Papastamos /* Rebase the IRQ into the GPIO range so we've got a sensible array 41208256712SDimitris Papastamos * index. 41308256712SDimitris Papastamos */ 41408256712SDimitris Papastamos irq -= WM831X_IRQ_GPIO_1; 41508256712SDimitris Papastamos 416ca7a7182SMark Brown /* We set the high bit to flag that we need an update; don't 417ca7a7182SMark Brown * do the update here as we can be called with the bus lock 418ca7a7182SMark Brown * held. 419ca7a7182SMark Brown */ 420896060c7SMark Brown switch (type) { 421896060c7SMark Brown case IRQ_TYPE_EDGE_BOTH: 422ca7a7182SMark Brown wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_INT_MODE; 423896060c7SMark Brown break; 424896060c7SMark Brown case IRQ_TYPE_EDGE_RISING: 425ca7a7182SMark Brown wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_POL; 426896060c7SMark Brown break; 427896060c7SMark Brown case IRQ_TYPE_EDGE_FALLING: 428ca7a7182SMark Brown wm831x->gpio_update[irq] = 0x10000; 429896060c7SMark Brown break; 430896060c7SMark Brown default: 431896060c7SMark Brown return -EINVAL; 432896060c7SMark Brown } 433896060c7SMark Brown 434ca7a7182SMark Brown return 0; 435896060c7SMark Brown } 436896060c7SMark Brown 4375fb4d38bSMark Brown static struct irq_chip wm831x_irq_chip = { 4385fb4d38bSMark Brown .name = "wm831x", 439ba81cd39SMark Brown .irq_bus_lock = wm831x_irq_lock, 440ba81cd39SMark Brown .irq_bus_sync_unlock = wm831x_irq_sync_unlock, 441f624effbSMark Brown .irq_disable = wm831x_irq_disable, 442f624effbSMark Brown .irq_enable = wm831x_irq_enable, 443ba81cd39SMark Brown .irq_set_type = wm831x_irq_set_type, 4445fb4d38bSMark Brown }; 4455fb4d38bSMark Brown 4465fb4d38bSMark Brown /* The processing of the primary interrupt occurs in a thread so that 4475fb4d38bSMark Brown * we can interact with the device over I2C or SPI. */ 4485fb4d38bSMark Brown static irqreturn_t wm831x_irq_thread(int irq, void *data) 4495fb4d38bSMark Brown { 4505fb4d38bSMark Brown struct wm831x *wm831x = data; 4517d4d0a3eSMark Brown unsigned int i; 45288c93977SMark Brown int primary, status_addr; 4535fb4d38bSMark Brown int status_regs[WM831X_NUM_IRQ_REGS] = { 0 }; 4545fb4d38bSMark Brown int read[WM831X_NUM_IRQ_REGS] = { 0 }; 4557d4d0a3eSMark Brown int *status; 4567d4d0a3eSMark Brown 4577d4d0a3eSMark Brown primary = wm831x_reg_read(wm831x, WM831X_SYSTEM_INTERRUPTS); 4587d4d0a3eSMark Brown if (primary < 0) { 4597d4d0a3eSMark Brown dev_err(wm831x->dev, "Failed to read system interrupt: %d\n", 4607d4d0a3eSMark Brown primary); 4617d4d0a3eSMark Brown goto out; 4627d4d0a3eSMark Brown } 4637d4d0a3eSMark Brown 4648546bd4aSMark Brown /* The touch interrupts are visible in the primary register as 4658546bd4aSMark Brown * an optimisation; open code this to avoid complicating the 4668546bd4aSMark Brown * main handling loop and so we can also skip iterating the 4678546bd4aSMark Brown * descriptors. 4688546bd4aSMark Brown */ 4698546bd4aSMark Brown if (primary & WM831X_TCHPD_INT) 4708546bd4aSMark Brown handle_nested_irq(wm831x->irq_base + WM831X_IRQ_TCHPD); 4718546bd4aSMark Brown if (primary & WM831X_TCHDATA_INT) 4728546bd4aSMark Brown handle_nested_irq(wm831x->irq_base + WM831X_IRQ_TCHDATA); 4738546bd4aSMark Brown if (primary & (WM831X_TCHDATA_EINT | WM831X_TCHPD_EINT)) 4748546bd4aSMark Brown goto out; 4758546bd4aSMark Brown 4767d4d0a3eSMark Brown for (i = 0; i < ARRAY_SIZE(wm831x_irqs); i++) { 4777d4d0a3eSMark Brown int offset = wm831x_irqs[i].reg - 1; 4787d4d0a3eSMark Brown 4797d4d0a3eSMark Brown if (!(primary & wm831x_irqs[i].primary)) 4807d4d0a3eSMark Brown continue; 4817d4d0a3eSMark Brown 4827d4d0a3eSMark Brown status = &status_regs[offset]; 4837d4d0a3eSMark Brown 4847d4d0a3eSMark Brown /* Hopefully there should only be one register to read 4857d4d0a3eSMark Brown * each time otherwise we ought to do a block read. */ 4867d4d0a3eSMark Brown if (!read[offset]) { 48788c93977SMark Brown status_addr = irq_data_to_status_reg(&wm831x_irqs[i]); 48888c93977SMark Brown 48988c93977SMark Brown *status = wm831x_reg_read(wm831x, status_addr); 4907d4d0a3eSMark Brown if (*status < 0) { 4917d4d0a3eSMark Brown dev_err(wm831x->dev, 4927d4d0a3eSMark Brown "Failed to read IRQ status: %d\n", 4937d4d0a3eSMark Brown *status); 4945fb4d38bSMark Brown goto out; 4957d4d0a3eSMark Brown } 4967d4d0a3eSMark Brown 4977d4d0a3eSMark Brown read[offset] = 1; 49888c93977SMark Brown 49988c93977SMark Brown /* Ignore any bits that we don't think are masked */ 50088c93977SMark Brown *status &= ~wm831x->irq_masks_cur[offset]; 50188c93977SMark Brown 50288c93977SMark Brown /* Acknowledge now so we don't miss 50388c93977SMark Brown * notifications while we handle. 50488c93977SMark Brown */ 50588c93977SMark Brown wm831x_reg_write(wm831x, status_addr, *status); 5067d4d0a3eSMark Brown } 5077d4d0a3eSMark Brown 50888c93977SMark Brown if (*status & wm831x_irqs[i].mask) 5095fb4d38bSMark Brown handle_nested_irq(wm831x->irq_base + i); 5107d4d0a3eSMark Brown } 5117d4d0a3eSMark Brown 5127d4d0a3eSMark Brown out: 5137d4d0a3eSMark Brown return IRQ_HANDLED; 5147d4d0a3eSMark Brown } 5157d4d0a3eSMark Brown 5167d4d0a3eSMark Brown int wm831x_irq_init(struct wm831x *wm831x, int irq) 5177d4d0a3eSMark Brown { 5185fb4d38bSMark Brown struct wm831x_pdata *pdata = wm831x->dev->platform_data; 5195fb4d38bSMark Brown int i, cur_irq, ret; 5207d4d0a3eSMark Brown 52114f572faSMark Brown mutex_init(&wm831x->irq_lock); 52214f572faSMark Brown 5230d7e0e39SMark Brown /* Mask the individual interrupt sources */ 5240d7e0e39SMark Brown for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) { 5250d7e0e39SMark Brown wm831x->irq_masks_cur[i] = 0xffff; 5260d7e0e39SMark Brown wm831x->irq_masks_cache[i] = 0xffff; 5270d7e0e39SMark Brown wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1_MASK + i, 5280d7e0e39SMark Brown 0xffff); 5290d7e0e39SMark Brown } 5300d7e0e39SMark Brown 5315c05a8d1SMark Brown /* Try to dynamically allocate IRQs if no base is specified */ 5325c05a8d1SMark Brown if (!pdata || !pdata->irq_base) 5335c05a8d1SMark Brown wm831x->irq_base = -1; 5345c05a8d1SMark Brown else 5355c05a8d1SMark Brown wm831x->irq_base = pdata->irq_base; 5365c05a8d1SMark Brown 5375c05a8d1SMark Brown wm831x->irq_base = irq_alloc_descs(wm831x->irq_base, 0, 5385c05a8d1SMark Brown WM831X_NUM_IRQS, 0); 5395c05a8d1SMark Brown if (wm831x->irq_base < 0) { 5405c05a8d1SMark Brown dev_warn(wm831x->dev, "Failed to allocate IRQs: %d\n", 5415c05a8d1SMark Brown wm831x->irq_base); 5425c05a8d1SMark Brown wm831x->irq_base = 0; 5435fb4d38bSMark Brown return 0; 5447d4d0a3eSMark Brown } 5457d4d0a3eSMark Brown 5465c05a8d1SMark Brown if (pdata && pdata->irq_cmos) 547b103e0b3SMark Brown i = 0; 548b103e0b3SMark Brown else 549b103e0b3SMark Brown i = WM831X_IRQ_OD; 550b103e0b3SMark Brown 551b103e0b3SMark Brown wm831x_set_bits(wm831x, WM831X_IRQ_CONFIG, 552b103e0b3SMark Brown WM831X_IRQ_OD, i); 553b103e0b3SMark Brown 554180e4f5fSMark Brown /* Try to flag /IRQ as a wake source; there are a number of 555180e4f5fSMark Brown * unconditional wake sources in the PMIC so this isn't 556180e4f5fSMark Brown * conditional but we don't actually care *too* much if it 557180e4f5fSMark Brown * fails. 558180e4f5fSMark Brown */ 559180e4f5fSMark Brown ret = enable_irq_wake(irq); 560180e4f5fSMark Brown if (ret != 0) { 561180e4f5fSMark Brown dev_warn(wm831x->dev, "Can't enable IRQ as wake source: %d\n", 562180e4f5fSMark Brown ret); 563180e4f5fSMark Brown } 564180e4f5fSMark Brown 5657d4d0a3eSMark Brown wm831x->irq = irq; 5667d4d0a3eSMark Brown 5675fb4d38bSMark Brown /* Register them with genirq */ 5685fb4d38bSMark Brown for (cur_irq = wm831x->irq_base; 5695fb4d38bSMark Brown cur_irq < ARRAY_SIZE(wm831x_irqs) + wm831x->irq_base; 5705fb4d38bSMark Brown cur_irq++) { 571d5bb1221SThomas Gleixner irq_set_chip_data(cur_irq, wm831x); 572d5bb1221SThomas Gleixner irq_set_chip_and_handler(cur_irq, &wm831x_irq_chip, 5735fb4d38bSMark Brown handle_edge_irq); 574d5bb1221SThomas Gleixner irq_set_nested_thread(cur_irq, 1); 5757d4d0a3eSMark Brown 5765fb4d38bSMark Brown /* ARM needs us to explicitly flag the IRQ as valid 5775fb4d38bSMark Brown * and will set them noprobe when we do so. */ 5785fb4d38bSMark Brown #ifdef CONFIG_ARM 5795fb4d38bSMark Brown set_irq_flags(cur_irq, IRQF_VALID); 5805fb4d38bSMark Brown #else 581d5bb1221SThomas Gleixner irq_set_noprobe(cur_irq); 5825fb4d38bSMark Brown #endif 5835fb4d38bSMark Brown } 5845fb4d38bSMark Brown 585bc86fceeSMark Brown if (irq) { 5865fb4d38bSMark Brown ret = request_threaded_irq(irq, NULL, wm831x_irq_thread, 5875fb4d38bSMark Brown IRQF_TRIGGER_LOW | IRQF_ONESHOT, 5887d4d0a3eSMark Brown "wm831x", wm831x); 5897d4d0a3eSMark Brown if (ret != 0) { 5907d4d0a3eSMark Brown dev_err(wm831x->dev, "Failed to request IRQ %d: %d\n", 5917d4d0a3eSMark Brown irq, ret); 5927d4d0a3eSMark Brown return ret; 5937d4d0a3eSMark Brown } 594bc86fceeSMark Brown } else { 595bc86fceeSMark Brown dev_warn(wm831x->dev, 596bc86fceeSMark Brown "No interrupt specified - functionality limited\n"); 597bc86fceeSMark Brown } 598bc86fceeSMark Brown 599bc86fceeSMark Brown 6007d4d0a3eSMark Brown 6015fb4d38bSMark Brown /* Enable top level interrupts, we mask at secondary level */ 6025fb4d38bSMark Brown wm831x_reg_write(wm831x, WM831X_SYSTEM_INTERRUPTS_MASK, 0); 6035fb4d38bSMark Brown 6047d4d0a3eSMark Brown return 0; 6057d4d0a3eSMark Brown } 6067d4d0a3eSMark Brown 6077d4d0a3eSMark Brown void wm831x_irq_exit(struct wm831x *wm831x) 6087d4d0a3eSMark Brown { 6097d4d0a3eSMark Brown if (wm831x->irq) 6107d4d0a3eSMark Brown free_irq(wm831x->irq, wm831x); 6117d4d0a3eSMark Brown } 612