12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
27d4d0a3eSMark Brown /*
37d4d0a3eSMark Brown * wm831x-irq.c -- Interrupt controller support for Wolfson WM831x PMICs
47d4d0a3eSMark Brown *
57d4d0a3eSMark Brown * Copyright 2009 Wolfson Microelectronics PLC.
67d4d0a3eSMark Brown *
77d4d0a3eSMark Brown * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
87d4d0a3eSMark Brown */
97d4d0a3eSMark Brown
107d4d0a3eSMark Brown #include <linux/kernel.h>
117d4d0a3eSMark Brown #include <linux/module.h>
127d4d0a3eSMark Brown #include <linux/i2c.h>
135fb4d38bSMark Brown #include <linux/irq.h>
147d4d0a3eSMark Brown #include <linux/mfd/core.h>
157d4d0a3eSMark Brown #include <linux/interrupt.h>
16cd99758bSMark Brown #include <linux/irqdomain.h>
177d4d0a3eSMark Brown
187d4d0a3eSMark Brown #include <linux/mfd/wm831x/core.h>
197d4d0a3eSMark Brown #include <linux/mfd/wm831x/pdata.h>
20896060c7SMark Brown #include <linux/mfd/wm831x/gpio.h>
217d4d0a3eSMark Brown #include <linux/mfd/wm831x/irq.h>
227d4d0a3eSMark Brown
237d4d0a3eSMark Brown #include <linux/delay.h>
247d4d0a3eSMark Brown
257d4d0a3eSMark Brown struct wm831x_irq_data {
267d4d0a3eSMark Brown int primary;
277d4d0a3eSMark Brown int reg;
287d4d0a3eSMark Brown int mask;
297d4d0a3eSMark Brown };
307d4d0a3eSMark Brown
317d4d0a3eSMark Brown static struct wm831x_irq_data wm831x_irqs[] = {
327d4d0a3eSMark Brown [WM831X_IRQ_TEMP_THW] = {
337d4d0a3eSMark Brown .primary = WM831X_TEMP_INT,
347d4d0a3eSMark Brown .reg = 1,
357d4d0a3eSMark Brown .mask = WM831X_TEMP_THW_EINT,
367d4d0a3eSMark Brown },
377d4d0a3eSMark Brown [WM831X_IRQ_GPIO_1] = {
387d4d0a3eSMark Brown .primary = WM831X_GP_INT,
397d4d0a3eSMark Brown .reg = 5,
407d4d0a3eSMark Brown .mask = WM831X_GP1_EINT,
417d4d0a3eSMark Brown },
427d4d0a3eSMark Brown [WM831X_IRQ_GPIO_2] = {
437d4d0a3eSMark Brown .primary = WM831X_GP_INT,
447d4d0a3eSMark Brown .reg = 5,
457d4d0a3eSMark Brown .mask = WM831X_GP2_EINT,
467d4d0a3eSMark Brown },
477d4d0a3eSMark Brown [WM831X_IRQ_GPIO_3] = {
487d4d0a3eSMark Brown .primary = WM831X_GP_INT,
497d4d0a3eSMark Brown .reg = 5,
507d4d0a3eSMark Brown .mask = WM831X_GP3_EINT,
517d4d0a3eSMark Brown },
527d4d0a3eSMark Brown [WM831X_IRQ_GPIO_4] = {
537d4d0a3eSMark Brown .primary = WM831X_GP_INT,
547d4d0a3eSMark Brown .reg = 5,
557d4d0a3eSMark Brown .mask = WM831X_GP4_EINT,
567d4d0a3eSMark Brown },
577d4d0a3eSMark Brown [WM831X_IRQ_GPIO_5] = {
587d4d0a3eSMark Brown .primary = WM831X_GP_INT,
597d4d0a3eSMark Brown .reg = 5,
607d4d0a3eSMark Brown .mask = WM831X_GP5_EINT,
617d4d0a3eSMark Brown },
627d4d0a3eSMark Brown [WM831X_IRQ_GPIO_6] = {
637d4d0a3eSMark Brown .primary = WM831X_GP_INT,
647d4d0a3eSMark Brown .reg = 5,
657d4d0a3eSMark Brown .mask = WM831X_GP6_EINT,
667d4d0a3eSMark Brown },
677d4d0a3eSMark Brown [WM831X_IRQ_GPIO_7] = {
687d4d0a3eSMark Brown .primary = WM831X_GP_INT,
697d4d0a3eSMark Brown .reg = 5,
707d4d0a3eSMark Brown .mask = WM831X_GP7_EINT,
717d4d0a3eSMark Brown },
727d4d0a3eSMark Brown [WM831X_IRQ_GPIO_8] = {
737d4d0a3eSMark Brown .primary = WM831X_GP_INT,
747d4d0a3eSMark Brown .reg = 5,
757d4d0a3eSMark Brown .mask = WM831X_GP8_EINT,
767d4d0a3eSMark Brown },
777d4d0a3eSMark Brown [WM831X_IRQ_GPIO_9] = {
787d4d0a3eSMark Brown .primary = WM831X_GP_INT,
797d4d0a3eSMark Brown .reg = 5,
807d4d0a3eSMark Brown .mask = WM831X_GP9_EINT,
817d4d0a3eSMark Brown },
827d4d0a3eSMark Brown [WM831X_IRQ_GPIO_10] = {
837d4d0a3eSMark Brown .primary = WM831X_GP_INT,
847d4d0a3eSMark Brown .reg = 5,
857d4d0a3eSMark Brown .mask = WM831X_GP10_EINT,
867d4d0a3eSMark Brown },
877d4d0a3eSMark Brown [WM831X_IRQ_GPIO_11] = {
887d4d0a3eSMark Brown .primary = WM831X_GP_INT,
897d4d0a3eSMark Brown .reg = 5,
907d4d0a3eSMark Brown .mask = WM831X_GP11_EINT,
917d4d0a3eSMark Brown },
927d4d0a3eSMark Brown [WM831X_IRQ_GPIO_12] = {
937d4d0a3eSMark Brown .primary = WM831X_GP_INT,
947d4d0a3eSMark Brown .reg = 5,
957d4d0a3eSMark Brown .mask = WM831X_GP12_EINT,
967d4d0a3eSMark Brown },
977d4d0a3eSMark Brown [WM831X_IRQ_GPIO_13] = {
987d4d0a3eSMark Brown .primary = WM831X_GP_INT,
997d4d0a3eSMark Brown .reg = 5,
1007d4d0a3eSMark Brown .mask = WM831X_GP13_EINT,
1017d4d0a3eSMark Brown },
1027d4d0a3eSMark Brown [WM831X_IRQ_GPIO_14] = {
1037d4d0a3eSMark Brown .primary = WM831X_GP_INT,
1047d4d0a3eSMark Brown .reg = 5,
1057d4d0a3eSMark Brown .mask = WM831X_GP14_EINT,
1067d4d0a3eSMark Brown },
1077d4d0a3eSMark Brown [WM831X_IRQ_GPIO_15] = {
1087d4d0a3eSMark Brown .primary = WM831X_GP_INT,
1097d4d0a3eSMark Brown .reg = 5,
1107d4d0a3eSMark Brown .mask = WM831X_GP15_EINT,
1117d4d0a3eSMark Brown },
1127d4d0a3eSMark Brown [WM831X_IRQ_GPIO_16] = {
1137d4d0a3eSMark Brown .primary = WM831X_GP_INT,
1147d4d0a3eSMark Brown .reg = 5,
1157d4d0a3eSMark Brown .mask = WM831X_GP16_EINT,
1167d4d0a3eSMark Brown },
1177d4d0a3eSMark Brown [WM831X_IRQ_ON] = {
1187d4d0a3eSMark Brown .primary = WM831X_ON_PIN_INT,
1197d4d0a3eSMark Brown .reg = 1,
1207d4d0a3eSMark Brown .mask = WM831X_ON_PIN_EINT,
1217d4d0a3eSMark Brown },
1227d4d0a3eSMark Brown [WM831X_IRQ_PPM_SYSLO] = {
1237d4d0a3eSMark Brown .primary = WM831X_PPM_INT,
1247d4d0a3eSMark Brown .reg = 1,
1257d4d0a3eSMark Brown .mask = WM831X_PPM_SYSLO_EINT,
1267d4d0a3eSMark Brown },
1277d4d0a3eSMark Brown [WM831X_IRQ_PPM_PWR_SRC] = {
1287d4d0a3eSMark Brown .primary = WM831X_PPM_INT,
1297d4d0a3eSMark Brown .reg = 1,
1307d4d0a3eSMark Brown .mask = WM831X_PPM_PWR_SRC_EINT,
1317d4d0a3eSMark Brown },
1327d4d0a3eSMark Brown [WM831X_IRQ_PPM_USB_CURR] = {
1337d4d0a3eSMark Brown .primary = WM831X_PPM_INT,
1347d4d0a3eSMark Brown .reg = 1,
1357d4d0a3eSMark Brown .mask = WM831X_PPM_USB_CURR_EINT,
1367d4d0a3eSMark Brown },
1377d4d0a3eSMark Brown [WM831X_IRQ_WDOG_TO] = {
1387d4d0a3eSMark Brown .primary = WM831X_WDOG_INT,
1397d4d0a3eSMark Brown .reg = 1,
1407d4d0a3eSMark Brown .mask = WM831X_WDOG_TO_EINT,
1417d4d0a3eSMark Brown },
1427d4d0a3eSMark Brown [WM831X_IRQ_RTC_PER] = {
1437d4d0a3eSMark Brown .primary = WM831X_RTC_INT,
1447d4d0a3eSMark Brown .reg = 1,
1457d4d0a3eSMark Brown .mask = WM831X_RTC_PER_EINT,
1467d4d0a3eSMark Brown },
1477d4d0a3eSMark Brown [WM831X_IRQ_RTC_ALM] = {
1487d4d0a3eSMark Brown .primary = WM831X_RTC_INT,
1497d4d0a3eSMark Brown .reg = 1,
1507d4d0a3eSMark Brown .mask = WM831X_RTC_ALM_EINT,
1517d4d0a3eSMark Brown },
1527d4d0a3eSMark Brown [WM831X_IRQ_CHG_BATT_HOT] = {
1537d4d0a3eSMark Brown .primary = WM831X_CHG_INT,
1547d4d0a3eSMark Brown .reg = 2,
1557d4d0a3eSMark Brown .mask = WM831X_CHG_BATT_HOT_EINT,
1567d4d0a3eSMark Brown },
1577d4d0a3eSMark Brown [WM831X_IRQ_CHG_BATT_COLD] = {
1587d4d0a3eSMark Brown .primary = WM831X_CHG_INT,
1597d4d0a3eSMark Brown .reg = 2,
1607d4d0a3eSMark Brown .mask = WM831X_CHG_BATT_COLD_EINT,
1617d4d0a3eSMark Brown },
1627d4d0a3eSMark Brown [WM831X_IRQ_CHG_BATT_FAIL] = {
1637d4d0a3eSMark Brown .primary = WM831X_CHG_INT,
1647d4d0a3eSMark Brown .reg = 2,
1657d4d0a3eSMark Brown .mask = WM831X_CHG_BATT_FAIL_EINT,
1667d4d0a3eSMark Brown },
1677d4d0a3eSMark Brown [WM831X_IRQ_CHG_OV] = {
1687d4d0a3eSMark Brown .primary = WM831X_CHG_INT,
1697d4d0a3eSMark Brown .reg = 2,
1707d4d0a3eSMark Brown .mask = WM831X_CHG_OV_EINT,
1717d4d0a3eSMark Brown },
1727d4d0a3eSMark Brown [WM831X_IRQ_CHG_END] = {
1737d4d0a3eSMark Brown .primary = WM831X_CHG_INT,
1747d4d0a3eSMark Brown .reg = 2,
1757d4d0a3eSMark Brown .mask = WM831X_CHG_END_EINT,
1767d4d0a3eSMark Brown },
1777d4d0a3eSMark Brown [WM831X_IRQ_CHG_TO] = {
1787d4d0a3eSMark Brown .primary = WM831X_CHG_INT,
1797d4d0a3eSMark Brown .reg = 2,
1807d4d0a3eSMark Brown .mask = WM831X_CHG_TO_EINT,
1817d4d0a3eSMark Brown },
1827d4d0a3eSMark Brown [WM831X_IRQ_CHG_MODE] = {
1837d4d0a3eSMark Brown .primary = WM831X_CHG_INT,
1847d4d0a3eSMark Brown .reg = 2,
1857d4d0a3eSMark Brown .mask = WM831X_CHG_MODE_EINT,
1867d4d0a3eSMark Brown },
1877d4d0a3eSMark Brown [WM831X_IRQ_CHG_START] = {
1887d4d0a3eSMark Brown .primary = WM831X_CHG_INT,
1897d4d0a3eSMark Brown .reg = 2,
1907d4d0a3eSMark Brown .mask = WM831X_CHG_START_EINT,
1917d4d0a3eSMark Brown },
1927d4d0a3eSMark Brown [WM831X_IRQ_TCHDATA] = {
1937d4d0a3eSMark Brown .primary = WM831X_TCHDATA_INT,
1947d4d0a3eSMark Brown .reg = 1,
1957d4d0a3eSMark Brown .mask = WM831X_TCHDATA_EINT,
1967d4d0a3eSMark Brown },
1977d4d0a3eSMark Brown [WM831X_IRQ_TCHPD] = {
1987d4d0a3eSMark Brown .primary = WM831X_TCHPD_INT,
1997d4d0a3eSMark Brown .reg = 1,
2007d4d0a3eSMark Brown .mask = WM831X_TCHPD_EINT,
2017d4d0a3eSMark Brown },
2027d4d0a3eSMark Brown [WM831X_IRQ_AUXADC_DATA] = {
2037d4d0a3eSMark Brown .primary = WM831X_AUXADC_INT,
2047d4d0a3eSMark Brown .reg = 1,
2057d4d0a3eSMark Brown .mask = WM831X_AUXADC_DATA_EINT,
2067d4d0a3eSMark Brown },
2077d4d0a3eSMark Brown [WM831X_IRQ_AUXADC_DCOMP1] = {
2087d4d0a3eSMark Brown .primary = WM831X_AUXADC_INT,
2097d4d0a3eSMark Brown .reg = 1,
2107d4d0a3eSMark Brown .mask = WM831X_AUXADC_DCOMP1_EINT,
2117d4d0a3eSMark Brown },
2127d4d0a3eSMark Brown [WM831X_IRQ_AUXADC_DCOMP2] = {
2137d4d0a3eSMark Brown .primary = WM831X_AUXADC_INT,
2147d4d0a3eSMark Brown .reg = 1,
2157d4d0a3eSMark Brown .mask = WM831X_AUXADC_DCOMP2_EINT,
2167d4d0a3eSMark Brown },
2177d4d0a3eSMark Brown [WM831X_IRQ_AUXADC_DCOMP3] = {
2187d4d0a3eSMark Brown .primary = WM831X_AUXADC_INT,
2197d4d0a3eSMark Brown .reg = 1,
2207d4d0a3eSMark Brown .mask = WM831X_AUXADC_DCOMP3_EINT,
2217d4d0a3eSMark Brown },
2227d4d0a3eSMark Brown [WM831X_IRQ_AUXADC_DCOMP4] = {
2237d4d0a3eSMark Brown .primary = WM831X_AUXADC_INT,
2247d4d0a3eSMark Brown .reg = 1,
2257d4d0a3eSMark Brown .mask = WM831X_AUXADC_DCOMP4_EINT,
2267d4d0a3eSMark Brown },
2277d4d0a3eSMark Brown [WM831X_IRQ_CS1] = {
2287d4d0a3eSMark Brown .primary = WM831X_CS_INT,
2297d4d0a3eSMark Brown .reg = 2,
2307d4d0a3eSMark Brown .mask = WM831X_CS1_EINT,
2317d4d0a3eSMark Brown },
2327d4d0a3eSMark Brown [WM831X_IRQ_CS2] = {
2337d4d0a3eSMark Brown .primary = WM831X_CS_INT,
2347d4d0a3eSMark Brown .reg = 2,
2357d4d0a3eSMark Brown .mask = WM831X_CS2_EINT,
2367d4d0a3eSMark Brown },
2377d4d0a3eSMark Brown [WM831X_IRQ_HC_DC1] = {
2387d4d0a3eSMark Brown .primary = WM831X_HC_INT,
2397d4d0a3eSMark Brown .reg = 4,
2407d4d0a3eSMark Brown .mask = WM831X_HC_DC1_EINT,
2417d4d0a3eSMark Brown },
2427d4d0a3eSMark Brown [WM831X_IRQ_HC_DC2] = {
2437d4d0a3eSMark Brown .primary = WM831X_HC_INT,
2447d4d0a3eSMark Brown .reg = 4,
2457d4d0a3eSMark Brown .mask = WM831X_HC_DC2_EINT,
2467d4d0a3eSMark Brown },
2477d4d0a3eSMark Brown [WM831X_IRQ_UV_LDO1] = {
2487d4d0a3eSMark Brown .primary = WM831X_UV_INT,
2497d4d0a3eSMark Brown .reg = 3,
2507d4d0a3eSMark Brown .mask = WM831X_UV_LDO1_EINT,
2517d4d0a3eSMark Brown },
2527d4d0a3eSMark Brown [WM831X_IRQ_UV_LDO2] = {
2537d4d0a3eSMark Brown .primary = WM831X_UV_INT,
2547d4d0a3eSMark Brown .reg = 3,
2557d4d0a3eSMark Brown .mask = WM831X_UV_LDO2_EINT,
2567d4d0a3eSMark Brown },
2577d4d0a3eSMark Brown [WM831X_IRQ_UV_LDO3] = {
2587d4d0a3eSMark Brown .primary = WM831X_UV_INT,
2597d4d0a3eSMark Brown .reg = 3,
2607d4d0a3eSMark Brown .mask = WM831X_UV_LDO3_EINT,
2617d4d0a3eSMark Brown },
2627d4d0a3eSMark Brown [WM831X_IRQ_UV_LDO4] = {
2637d4d0a3eSMark Brown .primary = WM831X_UV_INT,
2647d4d0a3eSMark Brown .reg = 3,
2657d4d0a3eSMark Brown .mask = WM831X_UV_LDO4_EINT,
2667d4d0a3eSMark Brown },
2677d4d0a3eSMark Brown [WM831X_IRQ_UV_LDO5] = {
2687d4d0a3eSMark Brown .primary = WM831X_UV_INT,
2697d4d0a3eSMark Brown .reg = 3,
2707d4d0a3eSMark Brown .mask = WM831X_UV_LDO5_EINT,
2717d4d0a3eSMark Brown },
2727d4d0a3eSMark Brown [WM831X_IRQ_UV_LDO6] = {
2737d4d0a3eSMark Brown .primary = WM831X_UV_INT,
2747d4d0a3eSMark Brown .reg = 3,
2757d4d0a3eSMark Brown .mask = WM831X_UV_LDO6_EINT,
2767d4d0a3eSMark Brown },
2777d4d0a3eSMark Brown [WM831X_IRQ_UV_LDO7] = {
2787d4d0a3eSMark Brown .primary = WM831X_UV_INT,
2797d4d0a3eSMark Brown .reg = 3,
2807d4d0a3eSMark Brown .mask = WM831X_UV_LDO7_EINT,
2817d4d0a3eSMark Brown },
2827d4d0a3eSMark Brown [WM831X_IRQ_UV_LDO8] = {
2837d4d0a3eSMark Brown .primary = WM831X_UV_INT,
2847d4d0a3eSMark Brown .reg = 3,
2857d4d0a3eSMark Brown .mask = WM831X_UV_LDO8_EINT,
2867d4d0a3eSMark Brown },
2877d4d0a3eSMark Brown [WM831X_IRQ_UV_LDO9] = {
2887d4d0a3eSMark Brown .primary = WM831X_UV_INT,
2897d4d0a3eSMark Brown .reg = 3,
2907d4d0a3eSMark Brown .mask = WM831X_UV_LDO9_EINT,
2917d4d0a3eSMark Brown },
2927d4d0a3eSMark Brown [WM831X_IRQ_UV_LDO10] = {
2937d4d0a3eSMark Brown .primary = WM831X_UV_INT,
2947d4d0a3eSMark Brown .reg = 3,
2957d4d0a3eSMark Brown .mask = WM831X_UV_LDO10_EINT,
2967d4d0a3eSMark Brown },
2977d4d0a3eSMark Brown [WM831X_IRQ_UV_DC1] = {
2987d4d0a3eSMark Brown .primary = WM831X_UV_INT,
2997d4d0a3eSMark Brown .reg = 4,
3007d4d0a3eSMark Brown .mask = WM831X_UV_DC1_EINT,
3017d4d0a3eSMark Brown },
3027d4d0a3eSMark Brown [WM831X_IRQ_UV_DC2] = {
3037d4d0a3eSMark Brown .primary = WM831X_UV_INT,
3047d4d0a3eSMark Brown .reg = 4,
3057d4d0a3eSMark Brown .mask = WM831X_UV_DC2_EINT,
3067d4d0a3eSMark Brown },
3077d4d0a3eSMark Brown [WM831X_IRQ_UV_DC3] = {
3087d4d0a3eSMark Brown .primary = WM831X_UV_INT,
3097d4d0a3eSMark Brown .reg = 4,
3107d4d0a3eSMark Brown .mask = WM831X_UV_DC3_EINT,
3117d4d0a3eSMark Brown },
3127d4d0a3eSMark Brown [WM831X_IRQ_UV_DC4] = {
3137d4d0a3eSMark Brown .primary = WM831X_UV_INT,
3147d4d0a3eSMark Brown .reg = 4,
3157d4d0a3eSMark Brown .mask = WM831X_UV_DC4_EINT,
3167d4d0a3eSMark Brown },
3177d4d0a3eSMark Brown };
3187d4d0a3eSMark Brown
irq_data_to_status_reg(struct wm831x_irq_data * irq_data)3197d4d0a3eSMark Brown static inline int irq_data_to_status_reg(struct wm831x_irq_data *irq_data)
3207d4d0a3eSMark Brown {
3217d4d0a3eSMark Brown return WM831X_INTERRUPT_STATUS_1 - 1 + irq_data->reg;
3227d4d0a3eSMark Brown }
3237d4d0a3eSMark Brown
irq_to_wm831x_irq(struct wm831x * wm831x,int irq)3245fb4d38bSMark Brown static inline struct wm831x_irq_data *irq_to_wm831x_irq(struct wm831x *wm831x,
3255fb4d38bSMark Brown int irq)
3267d4d0a3eSMark Brown {
327cd99758bSMark Brown return &wm831x_irqs[irq];
3287d4d0a3eSMark Brown }
3297d4d0a3eSMark Brown
wm831x_irq_lock(struct irq_data * data)330ba81cd39SMark Brown static void wm831x_irq_lock(struct irq_data *data)
3317d4d0a3eSMark Brown {
33225a947f8SMark Brown struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
3337d4d0a3eSMark Brown
3347d4d0a3eSMark Brown mutex_lock(&wm831x->irq_lock);
3357d4d0a3eSMark Brown }
3367d4d0a3eSMark Brown
wm831x_irq_sync_unlock(struct irq_data * data)337ba81cd39SMark Brown static void wm831x_irq_sync_unlock(struct irq_data *data)
3387d4d0a3eSMark Brown {
33925a947f8SMark Brown struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
3405fb4d38bSMark Brown int i;
3417d4d0a3eSMark Brown
342ca7a7182SMark Brown for (i = 0; i < ARRAY_SIZE(wm831x->gpio_update); i++) {
343ca7a7182SMark Brown if (wm831x->gpio_update[i]) {
344ca7a7182SMark Brown wm831x_set_bits(wm831x, WM831X_GPIO1_CONTROL + i,
345ca7a7182SMark Brown WM831X_GPN_INT_MODE | WM831X_GPN_POL,
346ca7a7182SMark Brown wm831x->gpio_update[i]);
347ca7a7182SMark Brown wm831x->gpio_update[i] = 0;
348ca7a7182SMark Brown }
349ca7a7182SMark Brown }
350ca7a7182SMark Brown
3515fb4d38bSMark Brown for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
3525fb4d38bSMark Brown /* If there's been a change in the mask write it back
3535fb4d38bSMark Brown * to the hardware. */
3545fb4d38bSMark Brown if (wm831x->irq_masks_cur[i] != wm831x->irq_masks_cache[i]) {
355f624effbSMark Brown dev_dbg(wm831x->dev, "IRQ mask sync: %x = %x\n",
356f624effbSMark Brown WM831X_INTERRUPT_STATUS_1_MASK + i,
357f624effbSMark Brown wm831x->irq_masks_cur[i]);
358f624effbSMark Brown
3595fb4d38bSMark Brown wm831x->irq_masks_cache[i] = wm831x->irq_masks_cur[i];
3605fb4d38bSMark Brown wm831x_reg_write(wm831x,
3615fb4d38bSMark Brown WM831X_INTERRUPT_STATUS_1_MASK + i,
3625fb4d38bSMark Brown wm831x->irq_masks_cur[i]);
3635fb4d38bSMark Brown }
3645fb4d38bSMark Brown }
3657d4d0a3eSMark Brown
3667d4d0a3eSMark Brown mutex_unlock(&wm831x->irq_lock);
3677d4d0a3eSMark Brown }
3687d4d0a3eSMark Brown
wm831x_irq_enable(struct irq_data * data)369f624effbSMark Brown static void wm831x_irq_enable(struct irq_data *data)
3707d4d0a3eSMark Brown {
37125a947f8SMark Brown struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
372ba81cd39SMark Brown struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x,
373cd99758bSMark Brown data->hwirq);
3747d4d0a3eSMark Brown
3755fb4d38bSMark Brown wm831x->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
3767d4d0a3eSMark Brown }
3777d4d0a3eSMark Brown
wm831x_irq_disable(struct irq_data * data)378f624effbSMark Brown static void wm831x_irq_disable(struct irq_data *data)
3797d4d0a3eSMark Brown {
38025a947f8SMark Brown struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
381ba81cd39SMark Brown struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x,
382cd99758bSMark Brown data->hwirq);
3835fb4d38bSMark Brown
3845fb4d38bSMark Brown wm831x->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
3855fb4d38bSMark Brown }
3865fb4d38bSMark Brown
wm831x_irq_set_type(struct irq_data * data,unsigned int type)387ba81cd39SMark Brown static int wm831x_irq_set_type(struct irq_data *data, unsigned int type)
388896060c7SMark Brown {
38925a947f8SMark Brown struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
390ca7a7182SMark Brown int irq;
391896060c7SMark Brown
392cd99758bSMark Brown irq = data->hwirq;
393896060c7SMark Brown
394c9d66d35SMark Brown if (irq < WM831X_IRQ_GPIO_1 || irq > WM831X_IRQ_GPIO_11) {
395c9d66d35SMark Brown /* Ignore internal-only IRQs */
396c9d66d35SMark Brown if (irq >= 0 && irq < WM831X_NUM_IRQS)
397c9d66d35SMark Brown return 0;
398c9d66d35SMark Brown else
399896060c7SMark Brown return -EINVAL;
400c9d66d35SMark Brown }
401896060c7SMark Brown
40208256712SDimitris Papastamos /* Rebase the IRQ into the GPIO range so we've got a sensible array
40308256712SDimitris Papastamos * index.
40408256712SDimitris Papastamos */
40508256712SDimitris Papastamos irq -= WM831X_IRQ_GPIO_1;
40608256712SDimitris Papastamos
407ca7a7182SMark Brown /* We set the high bit to flag that we need an update; don't
408ca7a7182SMark Brown * do the update here as we can be called with the bus lock
409ca7a7182SMark Brown * held.
410ca7a7182SMark Brown */
4111fe17a24SMark Brown wm831x->gpio_level_low[irq] = false;
4121fe17a24SMark Brown wm831x->gpio_level_high[irq] = false;
413896060c7SMark Brown switch (type) {
414896060c7SMark Brown case IRQ_TYPE_EDGE_BOTH:
415ca7a7182SMark Brown wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_INT_MODE;
416896060c7SMark Brown break;
417896060c7SMark Brown case IRQ_TYPE_EDGE_RISING:
418ca7a7182SMark Brown wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_POL;
419896060c7SMark Brown break;
420896060c7SMark Brown case IRQ_TYPE_EDGE_FALLING:
421ca7a7182SMark Brown wm831x->gpio_update[irq] = 0x10000;
4227583a213SMark Brown break;
4237583a213SMark Brown case IRQ_TYPE_LEVEL_HIGH:
4247583a213SMark Brown wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_POL;
4251fe17a24SMark Brown wm831x->gpio_level_high[irq] = true;
4261fe17a24SMark Brown break;
4271fe17a24SMark Brown case IRQ_TYPE_LEVEL_LOW:
4281fe17a24SMark Brown wm831x->gpio_update[irq] = 0x10000;
4291fe17a24SMark Brown wm831x->gpio_level_low[irq] = true;
430896060c7SMark Brown break;
431896060c7SMark Brown default:
432896060c7SMark Brown return -EINVAL;
433896060c7SMark Brown }
434896060c7SMark Brown
435ca7a7182SMark Brown return 0;
436896060c7SMark Brown }
437896060c7SMark Brown
4385fb4d38bSMark Brown static struct irq_chip wm831x_irq_chip = {
4395fb4d38bSMark Brown .name = "wm831x",
440ba81cd39SMark Brown .irq_bus_lock = wm831x_irq_lock,
441ba81cd39SMark Brown .irq_bus_sync_unlock = wm831x_irq_sync_unlock,
442f624effbSMark Brown .irq_disable = wm831x_irq_disable,
443f624effbSMark Brown .irq_enable = wm831x_irq_enable,
444ba81cd39SMark Brown .irq_set_type = wm831x_irq_set_type,
4455fb4d38bSMark Brown };
4465fb4d38bSMark Brown
4475fb4d38bSMark Brown /* The processing of the primary interrupt occurs in a thread so that
4485fb4d38bSMark Brown * we can interact with the device over I2C or SPI. */
wm831x_irq_thread(int irq,void * data)4495fb4d38bSMark Brown static irqreturn_t wm831x_irq_thread(int irq, void *data)
4505fb4d38bSMark Brown {
4515fb4d38bSMark Brown struct wm831x *wm831x = data;
4527d4d0a3eSMark Brown unsigned int i;
4537583a213SMark Brown int primary, status_addr, ret;
4545fb4d38bSMark Brown int status_regs[WM831X_NUM_IRQ_REGS] = { 0 };
4555fb4d38bSMark Brown int read[WM831X_NUM_IRQ_REGS] = { 0 };
4567d4d0a3eSMark Brown int *status;
4577d4d0a3eSMark Brown
4587d4d0a3eSMark Brown primary = wm831x_reg_read(wm831x, WM831X_SYSTEM_INTERRUPTS);
4597d4d0a3eSMark Brown if (primary < 0) {
4607d4d0a3eSMark Brown dev_err(wm831x->dev, "Failed to read system interrupt: %d\n",
4617d4d0a3eSMark Brown primary);
4627d4d0a3eSMark Brown goto out;
4637d4d0a3eSMark Brown }
4647d4d0a3eSMark Brown
4658546bd4aSMark Brown /* The touch interrupts are visible in the primary register as
4668546bd4aSMark Brown * an optimisation; open code this to avoid complicating the
4678546bd4aSMark Brown * main handling loop and so we can also skip iterating the
4688546bd4aSMark Brown * descriptors.
4698546bd4aSMark Brown */
4708546bd4aSMark Brown if (primary & WM831X_TCHPD_INT)
471cd99758bSMark Brown handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
472cd99758bSMark Brown WM831X_IRQ_TCHPD));
4738546bd4aSMark Brown if (primary & WM831X_TCHDATA_INT)
474cd99758bSMark Brown handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
475cd99758bSMark Brown WM831X_IRQ_TCHDATA));
476953c7d02SMark Brown primary &= ~(WM831X_TCHDATA_EINT | WM831X_TCHPD_EINT);
4778546bd4aSMark Brown
4787d4d0a3eSMark Brown for (i = 0; i < ARRAY_SIZE(wm831x_irqs); i++) {
4797d4d0a3eSMark Brown int offset = wm831x_irqs[i].reg - 1;
4807d4d0a3eSMark Brown
4817d4d0a3eSMark Brown if (!(primary & wm831x_irqs[i].primary))
4827d4d0a3eSMark Brown continue;
4837d4d0a3eSMark Brown
4847d4d0a3eSMark Brown status = &status_regs[offset];
4857d4d0a3eSMark Brown
4867d4d0a3eSMark Brown /* Hopefully there should only be one register to read
4877d4d0a3eSMark Brown * each time otherwise we ought to do a block read. */
4887d4d0a3eSMark Brown if (!read[offset]) {
48988c93977SMark Brown status_addr = irq_data_to_status_reg(&wm831x_irqs[i]);
49088c93977SMark Brown
49188c93977SMark Brown *status = wm831x_reg_read(wm831x, status_addr);
4927d4d0a3eSMark Brown if (*status < 0) {
4937d4d0a3eSMark Brown dev_err(wm831x->dev,
4947d4d0a3eSMark Brown "Failed to read IRQ status: %d\n",
4957d4d0a3eSMark Brown *status);
4965fb4d38bSMark Brown goto out;
4977d4d0a3eSMark Brown }
4987d4d0a3eSMark Brown
4997d4d0a3eSMark Brown read[offset] = 1;
50088c93977SMark Brown
50188c93977SMark Brown /* Ignore any bits that we don't think are masked */
50288c93977SMark Brown *status &= ~wm831x->irq_masks_cur[offset];
50388c93977SMark Brown
50488c93977SMark Brown /* Acknowledge now so we don't miss
50588c93977SMark Brown * notifications while we handle.
50688c93977SMark Brown */
50788c93977SMark Brown wm831x_reg_write(wm831x, status_addr, *status);
5087d4d0a3eSMark Brown }
5097d4d0a3eSMark Brown
51088c93977SMark Brown if (*status & wm831x_irqs[i].mask)
511cd99758bSMark Brown handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
512cd99758bSMark Brown i));
5137583a213SMark Brown
5147583a213SMark Brown /* Simulate an edge triggered IRQ by polling the input
5157583a213SMark Brown * status. This is sucky but improves interoperability.
5167583a213SMark Brown */
5177583a213SMark Brown if (primary == WM831X_GP_INT &&
5181fe17a24SMark Brown wm831x->gpio_level_high[i - WM831X_IRQ_GPIO_1]) {
5197583a213SMark Brown ret = wm831x_reg_read(wm831x, WM831X_GPIO_LEVEL);
5207583a213SMark Brown while (ret & 1 << (i - WM831X_IRQ_GPIO_1)) {
521cd99758bSMark Brown handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
522cd99758bSMark Brown i));
5237583a213SMark Brown ret = wm831x_reg_read(wm831x,
5247583a213SMark Brown WM831X_GPIO_LEVEL);
5257583a213SMark Brown }
5267583a213SMark Brown }
5271fe17a24SMark Brown
5281fe17a24SMark Brown if (primary == WM831X_GP_INT &&
5291fe17a24SMark Brown wm831x->gpio_level_low[i - WM831X_IRQ_GPIO_1]) {
5301fe17a24SMark Brown ret = wm831x_reg_read(wm831x, WM831X_GPIO_LEVEL);
5311fe17a24SMark Brown while (!(ret & 1 << (i - WM831X_IRQ_GPIO_1))) {
5321fe17a24SMark Brown handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
5331fe17a24SMark Brown i));
5341fe17a24SMark Brown ret = wm831x_reg_read(wm831x,
5351fe17a24SMark Brown WM831X_GPIO_LEVEL);
5361fe17a24SMark Brown }
5371fe17a24SMark Brown }
5387d4d0a3eSMark Brown }
5397d4d0a3eSMark Brown
5407d4d0a3eSMark Brown out:
5417d4d0a3eSMark Brown return IRQ_HANDLED;
5427d4d0a3eSMark Brown }
5437d4d0a3eSMark Brown
wm831x_irq_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw)544cd99758bSMark Brown static int wm831x_irq_map(struct irq_domain *h, unsigned int virq,
545cd99758bSMark Brown irq_hw_number_t hw)
546cd99758bSMark Brown {
547cd99758bSMark Brown irq_set_chip_data(virq, h->host_data);
548cd99758bSMark Brown irq_set_chip_and_handler(virq, &wm831x_irq_chip, handle_edge_irq);
549cd99758bSMark Brown irq_set_nested_thread(virq, 1);
550cd99758bSMark Brown irq_set_noprobe(virq);
551cd99758bSMark Brown
552cd99758bSMark Brown return 0;
553cd99758bSMark Brown }
554cd99758bSMark Brown
5557ce7b26fSKrzysztof Kozlowski static const struct irq_domain_ops wm831x_irq_domain_ops = {
556cd99758bSMark Brown .map = wm831x_irq_map,
557cd99758bSMark Brown .xlate = irq_domain_xlate_twocell,
558cd99758bSMark Brown };
559cd99758bSMark Brown
wm831x_irq_init(struct wm831x * wm831x,int irq)5607d4d0a3eSMark Brown int wm831x_irq_init(struct wm831x *wm831x, int irq)
5617d4d0a3eSMark Brown {
562f6dd8449SCharles Keepax struct wm831x_pdata *pdata = &wm831x->pdata;
563cd99758bSMark Brown struct irq_domain *domain;
564cd99758bSMark Brown int i, ret, irq_base;
5657d4d0a3eSMark Brown
56614f572faSMark Brown mutex_init(&wm831x->irq_lock);
56714f572faSMark Brown
5680d7e0e39SMark Brown /* Mask the individual interrupt sources */
5690d7e0e39SMark Brown for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
5700d7e0e39SMark Brown wm831x->irq_masks_cur[i] = 0xffff;
5710d7e0e39SMark Brown wm831x->irq_masks_cache[i] = 0xffff;
5720d7e0e39SMark Brown wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1_MASK + i,
5730d7e0e39SMark Brown 0xffff);
5740d7e0e39SMark Brown }
5750d7e0e39SMark Brown
5765c05a8d1SMark Brown /* Try to dynamically allocate IRQs if no base is specified */
577f6dd8449SCharles Keepax if (pdata->irq_base) {
578cd99758bSMark Brown irq_base = irq_alloc_descs(pdata->irq_base, 0,
5795c05a8d1SMark Brown WM831X_NUM_IRQS, 0);
580cd99758bSMark Brown if (irq_base < 0) {
5815c05a8d1SMark Brown dev_warn(wm831x->dev, "Failed to allocate IRQs: %d\n",
582cd99758bSMark Brown irq_base);
583cd99758bSMark Brown irq_base = 0;
584cd99758bSMark Brown }
585cd99758bSMark Brown } else {
586cd99758bSMark Brown irq_base = 0;
587cd99758bSMark Brown }
588cd99758bSMark Brown
589cd99758bSMark Brown if (irq_base)
590cd99758bSMark Brown domain = irq_domain_add_legacy(wm831x->dev->of_node,
591cd99758bSMark Brown ARRAY_SIZE(wm831x_irqs),
592cd99758bSMark Brown irq_base, 0,
593cd99758bSMark Brown &wm831x_irq_domain_ops,
594cd99758bSMark Brown wm831x);
595cd99758bSMark Brown else
596cd99758bSMark Brown domain = irq_domain_add_linear(wm831x->dev->of_node,
597cd99758bSMark Brown ARRAY_SIZE(wm831x_irqs),
598cd99758bSMark Brown &wm831x_irq_domain_ops,
599cd99758bSMark Brown wm831x);
600cd99758bSMark Brown
601cd99758bSMark Brown if (!domain) {
602cd99758bSMark Brown dev_warn(wm831x->dev, "Failed to allocate IRQ domain\n");
603cd99758bSMark Brown return -EINVAL;
6047d4d0a3eSMark Brown }
6057d4d0a3eSMark Brown
606f6dd8449SCharles Keepax if (pdata->irq_cmos)
607b103e0b3SMark Brown i = 0;
608b103e0b3SMark Brown else
609b103e0b3SMark Brown i = WM831X_IRQ_OD;
610b103e0b3SMark Brown
611b103e0b3SMark Brown wm831x_set_bits(wm831x, WM831X_IRQ_CONFIG,
612b103e0b3SMark Brown WM831X_IRQ_OD, i);
613b103e0b3SMark Brown
6147d4d0a3eSMark Brown wm831x->irq = irq;
615cd99758bSMark Brown wm831x->irq_domain = domain;
6165fb4d38bSMark Brown
617bc86fceeSMark Brown if (irq) {
6184492c4c3SMark Brown /* Try to flag /IRQ as a wake source; there are a number of
6194492c4c3SMark Brown * unconditional wake sources in the PMIC so this isn't
6204492c4c3SMark Brown * conditional but we don't actually care *too* much if it
6214492c4c3SMark Brown * fails.
6224492c4c3SMark Brown */
6234492c4c3SMark Brown ret = enable_irq_wake(irq);
6244492c4c3SMark Brown if (ret != 0) {
6254492c4c3SMark Brown dev_warn(wm831x->dev,
6264492c4c3SMark Brown "Can't enable IRQ as wake source: %d\n",
6274492c4c3SMark Brown ret);
6284492c4c3SMark Brown }
6294492c4c3SMark Brown
6305fb4d38bSMark Brown ret = request_threaded_irq(irq, NULL, wm831x_irq_thread,
6315fb4d38bSMark Brown IRQF_TRIGGER_LOW | IRQF_ONESHOT,
6327d4d0a3eSMark Brown "wm831x", wm831x);
6337d4d0a3eSMark Brown if (ret != 0) {
6347d4d0a3eSMark Brown dev_err(wm831x->dev, "Failed to request IRQ %d: %d\n",
6357d4d0a3eSMark Brown irq, ret);
6367d4d0a3eSMark Brown return ret;
6377d4d0a3eSMark Brown }
638bc86fceeSMark Brown } else {
639bc86fceeSMark Brown dev_warn(wm831x->dev,
640bc86fceeSMark Brown "No interrupt specified - functionality limited\n");
641bc86fceeSMark Brown }
642bc86fceeSMark Brown
6435fb4d38bSMark Brown /* Enable top level interrupts, we mask at secondary level */
6445fb4d38bSMark Brown wm831x_reg_write(wm831x, WM831X_SYSTEM_INTERRUPTS_MASK, 0);
6455fb4d38bSMark Brown
6467d4d0a3eSMark Brown return 0;
6477d4d0a3eSMark Brown }
6487d4d0a3eSMark Brown
wm831x_irq_exit(struct wm831x * wm831x)6497d4d0a3eSMark Brown void wm831x_irq_exit(struct wm831x *wm831x)
6507d4d0a3eSMark Brown {
6517d4d0a3eSMark Brown if (wm831x->irq)
6527d4d0a3eSMark Brown free_irq(wm831x->irq, wm831x);
6537d4d0a3eSMark Brown }
654