11a59d1b8SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
2e8deb28cSBalaji T K /*
3e8deb28cSBalaji T K * twl6030-irq.c - TWL6030 irq support
4e8deb28cSBalaji T K *
5e8deb28cSBalaji T K * Copyright (C) 2005-2009 Texas Instruments, Inc.
6e8deb28cSBalaji T K *
7e8deb28cSBalaji T K * Modifications to defer interrupt handling to a kernel thread:
8e8deb28cSBalaji T K * Copyright (C) 2006 MontaVista Software, Inc.
9e8deb28cSBalaji T K *
10e8deb28cSBalaji T K * Based on tlv320aic23.c:
11e8deb28cSBalaji T K * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
12e8deb28cSBalaji T K *
13e8deb28cSBalaji T K * Code cleanup and modifications to IRQ handler.
14e8deb28cSBalaji T K * by syed khasim <x0khasim@ti.com>
15e8deb28cSBalaji T K *
16e8deb28cSBalaji T K * TWL6030 specific code and IRQ handling changes by
17e8deb28cSBalaji T K * Jagadeesh Bhaskar Pakaravoor <j-pakaravoor@ti.com>
18e8deb28cSBalaji T K * Balaji T K <balajitk@ti.com>
19e8deb28cSBalaji T K */
20e8deb28cSBalaji T K
215d4a357dSPaul Gortmaker #include <linux/export.h>
22e8deb28cSBalaji T K #include <linux/interrupt.h>
23e8deb28cSBalaji T K #include <linux/irq.h>
24e8deb28cSBalaji T K #include <linux/kthread.h>
25a2054256SWolfram Sang #include <linux/mfd/twl.h>
2672f2e2c7Skishore kadiyala #include <linux/platform_device.h>
27ab2b9260STodd Poynor #include <linux/suspend.h>
2878518ffaSBenoit Cousson #include <linux/of.h>
2978518ffaSBenoit Cousson #include <linux/irqdomain.h>
3074d85e47SOleksandr Dmytryshyn #include <linux/of_device.h>
31e8deb28cSBalaji T K
32b0b4a7c2SG, Manjunath Kondaiah #include "twl-core.h"
33b0b4a7c2SG, Manjunath Kondaiah
34e8deb28cSBalaji T K /*
35e8deb28cSBalaji T K * TWL6030 (unlike its predecessors, which had two level interrupt handling)
36e8deb28cSBalaji T K * three interrupt registers INT_STS_A, INT_STS_B and INT_STS_C.
37e8deb28cSBalaji T K * It exposes status bits saying who has raised an interrupt. There are
38e8deb28cSBalaji T K * three mask registers that corresponds to these status registers, that
39e8deb28cSBalaji T K * enables/disables these interrupts.
40e8deb28cSBalaji T K *
41e8deb28cSBalaji T K * We set up IRQs starting at a platform-specified base. An interrupt map table,
42e8deb28cSBalaji T K * specifies mapping between interrupt number and the associated module.
43e8deb28cSBalaji T K */
4478518ffaSBenoit Cousson #define TWL6030_NR_IRQS 20
45e8deb28cSBalaji T K
46e8deb28cSBalaji T K static int twl6030_interrupt_mapping[24] = {
47e8deb28cSBalaji T K PWR_INTR_OFFSET, /* Bit 0 PWRON */
48e8deb28cSBalaji T K PWR_INTR_OFFSET, /* Bit 1 RPWRON */
49e8deb28cSBalaji T K PWR_INTR_OFFSET, /* Bit 2 BAT_VLOW */
50e8deb28cSBalaji T K RTC_INTR_OFFSET, /* Bit 3 RTC_ALARM */
51e8deb28cSBalaji T K RTC_INTR_OFFSET, /* Bit 4 RTC_PERIOD */
52e8deb28cSBalaji T K HOTDIE_INTR_OFFSET, /* Bit 5 HOT_DIE */
53e8deb28cSBalaji T K SMPSLDO_INTR_OFFSET, /* Bit 6 VXXX_SHORT */
54e8deb28cSBalaji T K SMPSLDO_INTR_OFFSET, /* Bit 7 VMMC_SHORT */
55e8deb28cSBalaji T K
56e8deb28cSBalaji T K SMPSLDO_INTR_OFFSET, /* Bit 8 VUSIM_SHORT */
57e8deb28cSBalaji T K BATDETECT_INTR_OFFSET, /* Bit 9 BAT */
58e8deb28cSBalaji T K SIMDETECT_INTR_OFFSET, /* Bit 10 SIM */
59e8deb28cSBalaji T K MMCDETECT_INTR_OFFSET, /* Bit 11 MMC */
60e8deb28cSBalaji T K RSV_INTR_OFFSET, /* Bit 12 Reserved */
61e8deb28cSBalaji T K MADC_INTR_OFFSET, /* Bit 13 GPADC_RT_EOC */
62e8deb28cSBalaji T K MADC_INTR_OFFSET, /* Bit 14 GPADC_SW_EOC */
63e8deb28cSBalaji T K GASGAUGE_INTR_OFFSET, /* Bit 15 CC_AUTOCAL */
64e8deb28cSBalaji T K
65e8deb28cSBalaji T K USBOTG_INTR_OFFSET, /* Bit 16 ID_WKUP */
66e8deb28cSBalaji T K USBOTG_INTR_OFFSET, /* Bit 17 VBUS_WKUP */
67e8deb28cSBalaji T K USBOTG_INTR_OFFSET, /* Bit 18 ID */
6877b1d3faSHema HK USB_PRES_INTR_OFFSET, /* Bit 19 VBUS */
69e8deb28cSBalaji T K CHARGER_INTR_OFFSET, /* Bit 20 CHRG_CTRL */
706523b148SGraeme Gregory CHARGERFAULT_INTR_OFFSET, /* Bit 21 EXT_CHRG */
716523b148SGraeme Gregory CHARGERFAULT_INTR_OFFSET, /* Bit 22 INT_CHRG */
72e8deb28cSBalaji T K RSV_INTR_OFFSET, /* Bit 23 Reserved */
73e8deb28cSBalaji T K };
7474d85e47SOleksandr Dmytryshyn
7574d85e47SOleksandr Dmytryshyn static int twl6032_interrupt_mapping[24] = {
7674d85e47SOleksandr Dmytryshyn PWR_INTR_OFFSET, /* Bit 0 PWRON */
7774d85e47SOleksandr Dmytryshyn PWR_INTR_OFFSET, /* Bit 1 RPWRON */
7874d85e47SOleksandr Dmytryshyn PWR_INTR_OFFSET, /* Bit 2 SYS_VLOW */
7974d85e47SOleksandr Dmytryshyn RTC_INTR_OFFSET, /* Bit 3 RTC_ALARM */
8074d85e47SOleksandr Dmytryshyn RTC_INTR_OFFSET, /* Bit 4 RTC_PERIOD */
8174d85e47SOleksandr Dmytryshyn HOTDIE_INTR_OFFSET, /* Bit 5 HOT_DIE */
8274d85e47SOleksandr Dmytryshyn SMPSLDO_INTR_OFFSET, /* Bit 6 VXXX_SHORT */
8374d85e47SOleksandr Dmytryshyn PWR_INTR_OFFSET, /* Bit 7 SPDURATION */
8474d85e47SOleksandr Dmytryshyn
8574d85e47SOleksandr Dmytryshyn PWR_INTR_OFFSET, /* Bit 8 WATCHDOG */
8674d85e47SOleksandr Dmytryshyn BATDETECT_INTR_OFFSET, /* Bit 9 BAT */
8774d85e47SOleksandr Dmytryshyn SIMDETECT_INTR_OFFSET, /* Bit 10 SIM */
8874d85e47SOleksandr Dmytryshyn MMCDETECT_INTR_OFFSET, /* Bit 11 MMC */
8974d85e47SOleksandr Dmytryshyn MADC_INTR_OFFSET, /* Bit 12 GPADC_RT_EOC */
9074d85e47SOleksandr Dmytryshyn MADC_INTR_OFFSET, /* Bit 13 GPADC_SW_EOC */
9174d85e47SOleksandr Dmytryshyn GASGAUGE_INTR_OFFSET, /* Bit 14 CC_EOC */
9274d85e47SOleksandr Dmytryshyn GASGAUGE_INTR_OFFSET, /* Bit 15 CC_AUTOCAL */
9374d85e47SOleksandr Dmytryshyn
9474d85e47SOleksandr Dmytryshyn USBOTG_INTR_OFFSET, /* Bit 16 ID_WKUP */
9574d85e47SOleksandr Dmytryshyn USBOTG_INTR_OFFSET, /* Bit 17 VBUS_WKUP */
9674d85e47SOleksandr Dmytryshyn USBOTG_INTR_OFFSET, /* Bit 18 ID */
9774d85e47SOleksandr Dmytryshyn USB_PRES_INTR_OFFSET, /* Bit 19 VBUS */
9874d85e47SOleksandr Dmytryshyn CHARGER_INTR_OFFSET, /* Bit 20 CHRG_CTRL */
9974d85e47SOleksandr Dmytryshyn CHARGERFAULT_INTR_OFFSET, /* Bit 21 EXT_CHRG */
10074d85e47SOleksandr Dmytryshyn CHARGERFAULT_INTR_OFFSET, /* Bit 22 INT_CHRG */
10174d85e47SOleksandr Dmytryshyn RSV_INTR_OFFSET, /* Bit 23 Reserved */
10274d85e47SOleksandr Dmytryshyn };
10374d85e47SOleksandr Dmytryshyn
104e8deb28cSBalaji T K /*----------------------------------------------------------------------*/
105e8deb28cSBalaji T K
1060aa8c685SGrygorii Strashko struct twl6030_irq {
1070aa8c685SGrygorii Strashko unsigned int irq_base;
1080aa8c685SGrygorii Strashko int twl_irq;
1090aa8c685SGrygorii Strashko bool irq_wake_enabled;
1100aa8c685SGrygorii Strashko atomic_t wakeirqs;
1110aa8c685SGrygorii Strashko struct notifier_block pm_nb;
1120aa8c685SGrygorii Strashko struct irq_chip irq_chip;
113b32408f6SGrygorii Strashko struct irq_domain *irq_domain;
11474d85e47SOleksandr Dmytryshyn const int *irq_mapping_tbl;
1150aa8c685SGrygorii Strashko };
1160aa8c685SGrygorii Strashko
1170aa8c685SGrygorii Strashko static struct twl6030_irq *twl6030_irq;
118ab2b9260STodd Poynor
twl6030_irq_pm_notifier(struct notifier_block * notifier,unsigned long pm_event,void * unused)119ab2b9260STodd Poynor static int twl6030_irq_pm_notifier(struct notifier_block *notifier,
120ab2b9260STodd Poynor unsigned long pm_event, void *unused)
121ab2b9260STodd Poynor {
122ab2b9260STodd Poynor int chained_wakeups;
1230aa8c685SGrygorii Strashko struct twl6030_irq *pdata = container_of(notifier, struct twl6030_irq,
1240aa8c685SGrygorii Strashko pm_nb);
125ab2b9260STodd Poynor
126ab2b9260STodd Poynor switch (pm_event) {
127ab2b9260STodd Poynor case PM_SUSPEND_PREPARE:
1280aa8c685SGrygorii Strashko chained_wakeups = atomic_read(&pdata->wakeirqs);
129ab2b9260STodd Poynor
1300aa8c685SGrygorii Strashko if (chained_wakeups && !pdata->irq_wake_enabled) {
1310aa8c685SGrygorii Strashko if (enable_irq_wake(pdata->twl_irq))
132ab2b9260STodd Poynor pr_err("twl6030 IRQ wake enable failed\n");
133ab2b9260STodd Poynor else
1340aa8c685SGrygorii Strashko pdata->irq_wake_enabled = true;
1350aa8c685SGrygorii Strashko } else if (!chained_wakeups && pdata->irq_wake_enabled) {
1360aa8c685SGrygorii Strashko disable_irq_wake(pdata->twl_irq);
1370aa8c685SGrygorii Strashko pdata->irq_wake_enabled = false;
138ab2b9260STodd Poynor }
139ab2b9260STodd Poynor
1400aa8c685SGrygorii Strashko disable_irq(pdata->twl_irq);
141ab2b9260STodd Poynor break;
142782baa20STodd Poynor
143782baa20STodd Poynor case PM_POST_SUSPEND:
1440aa8c685SGrygorii Strashko enable_irq(pdata->twl_irq);
145782baa20STodd Poynor break;
146782baa20STodd Poynor
147ab2b9260STodd Poynor default:
148ab2b9260STodd Poynor break;
149ab2b9260STodd Poynor }
150ab2b9260STodd Poynor
151ab2b9260STodd Poynor return NOTIFY_DONE;
152ab2b9260STodd Poynor }
153ab2b9260STodd Poynor
154e8deb28cSBalaji T K /*
15587343e53SNaga Venkata Srikanth V * Threaded irq handler for the twl6030 interrupt.
15687343e53SNaga Venkata Srikanth V * We query the interrupt controller in the twl6030 to determine
15787343e53SNaga Venkata Srikanth V * which module is generating the interrupt request and call
15887343e53SNaga Venkata Srikanth V * handle_nested_irq for that module.
159e8deb28cSBalaji T K */
twl6030_irq_thread(int irq,void * data)16087343e53SNaga Venkata Srikanth V static irqreturn_t twl6030_irq_thread(int irq, void *data)
161e8deb28cSBalaji T K {
16287343e53SNaga Venkata Srikanth V int i, ret;
163e8deb28cSBalaji T K union {
164e8deb28cSBalaji T K u8 bytes[4];
165754fa7bcSDanke Xie __le32 int_sts;
166e8deb28cSBalaji T K } sts;
167754fa7bcSDanke Xie u32 int_sts; /* sts.int_sts converted to CPU endianness */
1680aa8c685SGrygorii Strashko struct twl6030_irq *pdata = data;
169e8deb28cSBalaji T K
170e8deb28cSBalaji T K /* read INT_STS_A, B and C in one shot using a burst read */
17187343e53SNaga Venkata Srikanth V ret = twl_i2c_read(TWL_MODULE_PIH, sts.bytes, REG_INT_STS_A, 3);
172e8deb28cSBalaji T K if (ret) {
17387343e53SNaga Venkata Srikanth V pr_warn("twl6030_irq: I2C error %d reading PIH ISR\n", ret);
17487343e53SNaga Venkata Srikanth V return IRQ_HANDLED;
175e8deb28cSBalaji T K }
176e8deb28cSBalaji T K
177e8deb28cSBalaji T K sts.bytes[3] = 0; /* Only 24 bits are valid*/
178e8deb28cSBalaji T K
17977b1d3faSHema HK /*
18077b1d3faSHema HK * Since VBUS status bit is not reliable for VBUS disconnect
18177b1d3faSHema HK * use CHARGER VBUS detection status bit instead.
18277b1d3faSHema HK */
18377b1d3faSHema HK if (sts.bytes[2] & 0x10)
18477b1d3faSHema HK sts.bytes[2] |= 0x08;
18577b1d3faSHema HK
186754fa7bcSDanke Xie int_sts = le32_to_cpu(sts.int_sts);
187754fa7bcSDanke Xie for (i = 0; int_sts; int_sts >>= 1, i++)
188754fa7bcSDanke Xie if (int_sts & 0x1) {
189b32408f6SGrygorii Strashko int module_irq =
1900aa8c685SGrygorii Strashko irq_find_mapping(pdata->irq_domain,
19174d85e47SOleksandr Dmytryshyn pdata->irq_mapping_tbl[i]);
192b32408f6SGrygorii Strashko if (module_irq)
19387343e53SNaga Venkata Srikanth V handle_nested_irq(module_irq);
194b32408f6SGrygorii Strashko else
195b32408f6SGrygorii Strashko pr_err("twl6030_irq: Unmapped PIH ISR %u detected\n",
196b32408f6SGrygorii Strashko i);
19787343e53SNaga Venkata Srikanth V pr_debug("twl6030_irq: PIH ISR %u, virq%u\n",
19887343e53SNaga Venkata Srikanth V i, module_irq);
199e8deb28cSBalaji T K }
2003f8349e6SNishanth Menon
2013f8349e6SNishanth Menon /*
2023f8349e6SNishanth Menon * NOTE:
2033f8349e6SNishanth Menon * Simulation confirms that documentation is wrong w.r.t the
2043f8349e6SNishanth Menon * interrupt status clear operation. A single *byte* write to
2053f8349e6SNishanth Menon * any one of STS_A to STS_C register results in all three
2063f8349e6SNishanth Menon * STS registers being reset. Since it does not matter which
2073f8349e6SNishanth Menon * value is written, all three registers are cleared on a
2083f8349e6SNishanth Menon * single byte write, so we just use 0x0 to clear.
2093f8349e6SNishanth Menon */
2103f8349e6SNishanth Menon ret = twl_i2c_write_u8(TWL_MODULE_PIH, 0x00, REG_INT_STS_A);
211e8deb28cSBalaji T K if (ret)
21287343e53SNaga Venkata Srikanth V pr_warn("twl6030_irq: I2C error in clearing PIH ISR\n");
213e8deb28cSBalaji T K
214e8deb28cSBalaji T K return IRQ_HANDLED;
215e8deb28cSBalaji T K }
216e8deb28cSBalaji T K
217e8deb28cSBalaji T K /*----------------------------------------------------------------------*/
218e8deb28cSBalaji T K
twl6030_irq_set_wake(struct irq_data * d,unsigned int on)219b8b8d793SNishanth Menon static int twl6030_irq_set_wake(struct irq_data *d, unsigned int on)
22049dcd070SSantosh Shilimkar {
2211e84aa44SJiang Liu struct twl6030_irq *pdata = irq_data_get_irq_chip_data(d);
2220aa8c685SGrygorii Strashko
223ab2b9260STodd Poynor if (on)
2240aa8c685SGrygorii Strashko atomic_inc(&pdata->wakeirqs);
225ab2b9260STodd Poynor else
2260aa8c685SGrygorii Strashko atomic_dec(&pdata->wakeirqs);
22749dcd070SSantosh Shilimkar
228ab2b9260STodd Poynor return 0;
22949dcd070SSantosh Shilimkar }
23049dcd070SSantosh Shilimkar
twl6030_interrupt_unmask(u8 bit_mask,u8 offset)231e8deb28cSBalaji T K int twl6030_interrupt_unmask(u8 bit_mask, u8 offset)
232e8deb28cSBalaji T K {
233e8deb28cSBalaji T K int ret;
234e8deb28cSBalaji T K u8 unmask_value;
2353103de8cSLee Jones
236e8deb28cSBalaji T K ret = twl_i2c_read_u8(TWL_MODULE_PIH, &unmask_value,
237e8deb28cSBalaji T K REG_INT_STS_A + offset);
238e8deb28cSBalaji T K unmask_value &= (~(bit_mask));
239e8deb28cSBalaji T K ret |= twl_i2c_write_u8(TWL_MODULE_PIH, unmask_value,
240e8deb28cSBalaji T K REG_INT_STS_A + offset); /* unmask INT_MSK_A/B/C */
241e8deb28cSBalaji T K return ret;
242e8deb28cSBalaji T K }
243e8deb28cSBalaji T K EXPORT_SYMBOL(twl6030_interrupt_unmask);
244e8deb28cSBalaji T K
twl6030_interrupt_mask(u8 bit_mask,u8 offset)245e8deb28cSBalaji T K int twl6030_interrupt_mask(u8 bit_mask, u8 offset)
246e8deb28cSBalaji T K {
247e8deb28cSBalaji T K int ret;
248e8deb28cSBalaji T K u8 mask_value;
2493103de8cSLee Jones
250e8deb28cSBalaji T K ret = twl_i2c_read_u8(TWL_MODULE_PIH, &mask_value,
251e8deb28cSBalaji T K REG_INT_STS_A + offset);
252e8deb28cSBalaji T K mask_value |= (bit_mask);
253e8deb28cSBalaji T K ret |= twl_i2c_write_u8(TWL_MODULE_PIH, mask_value,
254e8deb28cSBalaji T K REG_INT_STS_A + offset); /* mask INT_MSK_A/B/C */
255e8deb28cSBalaji T K return ret;
256e8deb28cSBalaji T K }
257e8deb28cSBalaji T K EXPORT_SYMBOL(twl6030_interrupt_mask);
258e8deb28cSBalaji T K
twl6030_mmc_card_detect_config(void)25972f2e2c7Skishore kadiyala int twl6030_mmc_card_detect_config(void)
26072f2e2c7Skishore kadiyala {
26172f2e2c7Skishore kadiyala int ret;
26272f2e2c7Skishore kadiyala u8 reg_val = 0;
26372f2e2c7Skishore kadiyala
26472f2e2c7Skishore kadiyala /* Unmasking the Card detect Interrupt line for MMC1 from Phoenix */
26572f2e2c7Skishore kadiyala twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
26672f2e2c7Skishore kadiyala REG_INT_MSK_LINE_B);
26772f2e2c7Skishore kadiyala twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
26872f2e2c7Skishore kadiyala REG_INT_MSK_STS_B);
26972f2e2c7Skishore kadiyala /*
27025985edcSLucas De Marchi * Initially Configuring MMC_CTRL for receiving interrupts &
27172f2e2c7Skishore kadiyala * Card status on TWL6030 for MMC1
27272f2e2c7Skishore kadiyala */
27372f2e2c7Skishore kadiyala ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, ®_val, TWL6030_MMCCTRL);
27472f2e2c7Skishore kadiyala if (ret < 0) {
27572f2e2c7Skishore kadiyala pr_err("twl6030: Failed to read MMCCTRL, error %d\n", ret);
27672f2e2c7Skishore kadiyala return ret;
27772f2e2c7Skishore kadiyala }
27872f2e2c7Skishore kadiyala reg_val &= ~VMMC_AUTO_OFF;
27972f2e2c7Skishore kadiyala reg_val |= SW_FC;
28072f2e2c7Skishore kadiyala ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, TWL6030_MMCCTRL);
28172f2e2c7Skishore kadiyala if (ret < 0) {
28272f2e2c7Skishore kadiyala pr_err("twl6030: Failed to write MMCCTRL, error %d\n", ret);
28372f2e2c7Skishore kadiyala return ret;
28472f2e2c7Skishore kadiyala }
28572f2e2c7Skishore kadiyala
28672f2e2c7Skishore kadiyala /* Configuring PullUp-PullDown register */
28772f2e2c7Skishore kadiyala ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, ®_val,
28872f2e2c7Skishore kadiyala TWL6030_CFG_INPUT_PUPD3);
28972f2e2c7Skishore kadiyala if (ret < 0) {
29072f2e2c7Skishore kadiyala pr_err("twl6030: Failed to read CFG_INPUT_PUPD3, error %d\n",
29172f2e2c7Skishore kadiyala ret);
29272f2e2c7Skishore kadiyala return ret;
29372f2e2c7Skishore kadiyala }
29472f2e2c7Skishore kadiyala reg_val &= ~(MMC_PU | MMC_PD);
29572f2e2c7Skishore kadiyala ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val,
29672f2e2c7Skishore kadiyala TWL6030_CFG_INPUT_PUPD3);
29772f2e2c7Skishore kadiyala if (ret < 0) {
29872f2e2c7Skishore kadiyala pr_err("twl6030: Failed to write CFG_INPUT_PUPD3, error %d\n",
29972f2e2c7Skishore kadiyala ret);
30072f2e2c7Skishore kadiyala return ret;
30172f2e2c7Skishore kadiyala }
302bdd61bc6SBenoit Cousson
3030aa8c685SGrygorii Strashko return irq_find_mapping(twl6030_irq->irq_domain,
3040aa8c685SGrygorii Strashko MMCDETECT_INTR_OFFSET);
30572f2e2c7Skishore kadiyala }
30672f2e2c7Skishore kadiyala EXPORT_SYMBOL(twl6030_mmc_card_detect_config);
30772f2e2c7Skishore kadiyala
twl6030_mmc_card_detect(struct device * dev,int slot)30872f2e2c7Skishore kadiyala int twl6030_mmc_card_detect(struct device *dev, int slot)
30972f2e2c7Skishore kadiyala {
31072f2e2c7Skishore kadiyala int ret = -EIO;
31172f2e2c7Skishore kadiyala u8 read_reg = 0;
31272f2e2c7Skishore kadiyala struct platform_device *pdev = to_platform_device(dev);
31372f2e2c7Skishore kadiyala
31472f2e2c7Skishore kadiyala if (pdev->id) {
31572f2e2c7Skishore kadiyala /* TWL6030 provide's Card detect support for
31672f2e2c7Skishore kadiyala * only MMC1 controller.
31772f2e2c7Skishore kadiyala */
31825985edcSLucas De Marchi pr_err("Unknown MMC controller %d in %s\n", pdev->id, __func__);
31972f2e2c7Skishore kadiyala return ret;
32072f2e2c7Skishore kadiyala }
32172f2e2c7Skishore kadiyala /*
32272f2e2c7Skishore kadiyala * BIT0 of MMC_CTRL on TWL6030 provides card status for MMC1
32372f2e2c7Skishore kadiyala * 0 - Card not present ,1 - Card present
32472f2e2c7Skishore kadiyala */
32572f2e2c7Skishore kadiyala ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &read_reg,
32672f2e2c7Skishore kadiyala TWL6030_MMCCTRL);
32772f2e2c7Skishore kadiyala if (ret >= 0)
32872f2e2c7Skishore kadiyala ret = read_reg & STS_MMC;
32972f2e2c7Skishore kadiyala return ret;
33072f2e2c7Skishore kadiyala }
33172f2e2c7Skishore kadiyala EXPORT_SYMBOL(twl6030_mmc_card_detect);
33272f2e2c7Skishore kadiyala
twl6030_irq_map(struct irq_domain * d,unsigned int virq,irq_hw_number_t hwirq)333b32408f6SGrygorii Strashko static int twl6030_irq_map(struct irq_domain *d, unsigned int virq,
334b32408f6SGrygorii Strashko irq_hw_number_t hwirq)
335b32408f6SGrygorii Strashko {
3360aa8c685SGrygorii Strashko struct twl6030_irq *pdata = d->host_data;
3370aa8c685SGrygorii Strashko
3380aa8c685SGrygorii Strashko irq_set_chip_data(virq, pdata);
3390aa8c685SGrygorii Strashko irq_set_chip_and_handler(virq, &pdata->irq_chip, handle_simple_irq);
340b32408f6SGrygorii Strashko irq_set_nested_thread(virq, true);
3410aa8c685SGrygorii Strashko irq_set_parent(virq, pdata->twl_irq);
342b32408f6SGrygorii Strashko irq_set_noprobe(virq);
343b32408f6SGrygorii Strashko
344b32408f6SGrygorii Strashko return 0;
345b32408f6SGrygorii Strashko }
346b32408f6SGrygorii Strashko
twl6030_irq_unmap(struct irq_domain * d,unsigned int virq)347b32408f6SGrygorii Strashko static void twl6030_irq_unmap(struct irq_domain *d, unsigned int virq)
348b32408f6SGrygorii Strashko {
349b32408f6SGrygorii Strashko irq_set_chip_and_handler(virq, NULL, NULL);
350b32408f6SGrygorii Strashko irq_set_chip_data(virq, NULL);
351b32408f6SGrygorii Strashko }
352b32408f6SGrygorii Strashko
3537ce7b26fSKrzysztof Kozlowski static const struct irq_domain_ops twl6030_irq_domain_ops = {
354b32408f6SGrygorii Strashko .map = twl6030_irq_map,
355b32408f6SGrygorii Strashko .unmap = twl6030_irq_unmap,
356b32408f6SGrygorii Strashko .xlate = irq_domain_xlate_onetwocell,
357b32408f6SGrygorii Strashko };
358b32408f6SGrygorii Strashko
359e73fd3f2SKrzysztof Kozlowski static const struct of_device_id twl6030_of_match[] __maybe_unused = {
36074d85e47SOleksandr Dmytryshyn {.compatible = "ti,twl6030", &twl6030_interrupt_mapping},
36174d85e47SOleksandr Dmytryshyn {.compatible = "ti,twl6032", &twl6032_interrupt_mapping},
36274d85e47SOleksandr Dmytryshyn { },
36374d85e47SOleksandr Dmytryshyn };
36474d85e47SOleksandr Dmytryshyn
twl6030_init_irq(struct device * dev,int irq_num)36578518ffaSBenoit Cousson int twl6030_init_irq(struct device *dev, int irq_num)
366e8deb28cSBalaji T K {
36778518ffaSBenoit Cousson struct device_node *node = dev->of_node;
368b32408f6SGrygorii Strashko int nr_irqs;
369a820e568SGrygorii Strashko int status;
37014591d88SPeter Ujfalusi u8 mask[3];
37174d85e47SOleksandr Dmytryshyn const struct of_device_id *of_id;
37274d85e47SOleksandr Dmytryshyn
37374d85e47SOleksandr Dmytryshyn of_id = of_match_device(twl6030_of_match, dev);
37474d85e47SOleksandr Dmytryshyn if (!of_id || !of_id->data) {
37574d85e47SOleksandr Dmytryshyn dev_err(dev, "Unknown TWL device model\n");
37674d85e47SOleksandr Dmytryshyn return -EINVAL;
37774d85e47SOleksandr Dmytryshyn }
378e8deb28cSBalaji T K
37978518ffaSBenoit Cousson nr_irqs = TWL6030_NR_IRQS;
38078518ffaSBenoit Cousson
3810aa8c685SGrygorii Strashko twl6030_irq = devm_kzalloc(dev, sizeof(*twl6030_irq), GFP_KERNEL);
3829363be21SMarkus Elfring if (!twl6030_irq)
3830aa8c685SGrygorii Strashko return -ENOMEM;
3840aa8c685SGrygorii Strashko
38514591d88SPeter Ujfalusi mask[0] = 0xFF;
386e8deb28cSBalaji T K mask[1] = 0xFF;
387e8deb28cSBalaji T K mask[2] = 0xFF;
388ec1a07b3SBenoit Cousson
389ec1a07b3SBenoit Cousson /* mask all int lines */
390a820e568SGrygorii Strashko status = twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_LINE_A, 3);
391ec1a07b3SBenoit Cousson /* mask all int sts */
392a820e568SGrygorii Strashko status |= twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_STS_A, 3);
393ec1a07b3SBenoit Cousson /* clear INT_STS_A,B,C */
394a820e568SGrygorii Strashko status |= twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_STS_A, 3);
395a820e568SGrygorii Strashko
396a820e568SGrygorii Strashko if (status < 0) {
397a820e568SGrygorii Strashko dev_err(dev, "I2C err writing TWL_MODULE_PIH: %d\n", status);
398a820e568SGrygorii Strashko return status;
399a820e568SGrygorii Strashko }
400e8deb28cSBalaji T K
401ec1a07b3SBenoit Cousson /*
402ec1a07b3SBenoit Cousson * install an irq handler for each of the modules;
403e8deb28cSBalaji T K * clone dummy irq_chip since PIH can't *do* anything
404e8deb28cSBalaji T K */
4050aa8c685SGrygorii Strashko twl6030_irq->irq_chip = dummy_irq_chip;
4060aa8c685SGrygorii Strashko twl6030_irq->irq_chip.name = "twl6030";
4070aa8c685SGrygorii Strashko twl6030_irq->irq_chip.irq_set_type = NULL;
4080aa8c685SGrygorii Strashko twl6030_irq->irq_chip.irq_set_wake = twl6030_irq_set_wake;
409e8deb28cSBalaji T K
4100aa8c685SGrygorii Strashko twl6030_irq->pm_nb.notifier_call = twl6030_irq_pm_notifier;
4110aa8c685SGrygorii Strashko atomic_set(&twl6030_irq->wakeirqs, 0);
41274d85e47SOleksandr Dmytryshyn twl6030_irq->irq_mapping_tbl = of_id->data;
4130aa8c685SGrygorii Strashko
4140aa8c685SGrygorii Strashko twl6030_irq->irq_domain =
4150aa8c685SGrygorii Strashko irq_domain_add_linear(node, nr_irqs,
4160aa8c685SGrygorii Strashko &twl6030_irq_domain_ops, twl6030_irq);
4170aa8c685SGrygorii Strashko if (!twl6030_irq->irq_domain) {
418b32408f6SGrygorii Strashko dev_err(dev, "Can't add irq_domain\n");
419b32408f6SGrygorii Strashko return -ENOMEM;
420e8deb28cSBalaji T K }
421e8deb28cSBalaji T K
422b32408f6SGrygorii Strashko dev_info(dev, "PIH (irq %d) nested IRQs\n", irq_num);
423e8deb28cSBalaji T K
424e8deb28cSBalaji T K /* install an irq handler to demultiplex the TWL6030 interrupt */
42587343e53SNaga Venkata Srikanth V status = request_threaded_irq(irq_num, NULL, twl6030_irq_thread,
4260aa8c685SGrygorii Strashko IRQF_ONESHOT, "TWL6030-PIH", twl6030_irq);
427e8deb28cSBalaji T K if (status < 0) {
428ec1a07b3SBenoit Cousson dev_err(dev, "could not claim irq %d: %d\n", irq_num, status);
429e8deb28cSBalaji T K goto fail_irq;
430e8deb28cSBalaji T K }
431862de70cSAxel Lin
4320aa8c685SGrygorii Strashko twl6030_irq->twl_irq = irq_num;
4330aa8c685SGrygorii Strashko register_pm_notifier(&twl6030_irq->pm_nb);
434b32408f6SGrygorii Strashko return 0;
435e8deb28cSBalaji T K
436862de70cSAxel Lin fail_irq:
4370aa8c685SGrygorii Strashko irq_domain_remove(twl6030_irq->irq_domain);
438e8deb28cSBalaji T K return status;
439e8deb28cSBalaji T K }
440e8deb28cSBalaji T K
twl6030_exit_irq(void)441*b6f29431SUwe Kleine-König void twl6030_exit_irq(void)
442e8deb28cSBalaji T K {
4430aa8c685SGrygorii Strashko if (twl6030_irq && twl6030_irq->twl_irq) {
4440aa8c685SGrygorii Strashko unregister_pm_notifier(&twl6030_irq->pm_nb);
4450aa8c685SGrygorii Strashko free_irq(twl6030_irq->twl_irq, NULL);
446b32408f6SGrygorii Strashko /*
447b32408f6SGrygorii Strashko * TODO: IRQ domain and allocated nested IRQ descriptors
448b32408f6SGrygorii Strashko * should be freed somehow here. Now It can't be done, because
449b32408f6SGrygorii Strashko * child devices will not be deleted during removing of
450b32408f6SGrygorii Strashko * TWL Core driver and they will still contain allocated
451b32408f6SGrygorii Strashko * virt IRQs in their Resources tables.
452b32408f6SGrygorii Strashko * The same prevents us from using devm_request_threaded_irq()
453b32408f6SGrygorii Strashko * in this module.
454b32408f6SGrygorii Strashko */
455e8deb28cSBalaji T K }
456e8deb28cSBalaji T K }
457e8deb28cSBalaji T K
458