1 /* 2 * twl4030-irq.c - TWL4030/TPS659x0 irq support 3 * 4 * Copyright (C) 2005-2006 Texas Instruments, Inc. 5 * 6 * Modifications to defer interrupt handling to a kernel thread: 7 * Copyright (C) 2006 MontaVista Software, Inc. 8 * 9 * Based on tlv320aic23.c: 10 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com> 11 * 12 * Code cleanup and modifications to IRQ handler. 13 * by syed khasim <x0khasim@ti.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 28 */ 29 30 #include <linux/init.h> 31 #include <linux/interrupt.h> 32 #include <linux/irq.h> 33 #include <linux/kthread.h> 34 35 #include <linux/i2c/twl4030.h> 36 37 38 /* 39 * TWL4030 IRQ handling has two stages in hardware, and thus in software. 40 * The Primary Interrupt Handler (PIH) stage exposes status bits saying 41 * which Secondary Interrupt Handler (SIH) stage is raising an interrupt. 42 * SIH modules are more traditional IRQ components, which support per-IRQ 43 * enable/disable and trigger controls; they do most of the work. 44 * 45 * These chips are designed to support IRQ handling from two different 46 * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status 47 * and mask registers in the PIH and SIH modules. 48 * 49 * We set up IRQs starting at a platform-specified base, always starting 50 * with PIH and the SIH for PWR_INT and then usually adding GPIO: 51 * base + 0 .. base + 7 PIH 52 * base + 8 .. base + 15 SIH for PWR_INT 53 * base + 16 .. base + 33 SIH for GPIO 54 */ 55 56 /* PIH register offsets */ 57 #define REG_PIH_ISR_P1 0x01 58 #define REG_PIH_ISR_P2 0x02 59 #define REG_PIH_SIR 0x03 /* for testing */ 60 61 62 /* Linux could (eventually) use either IRQ line */ 63 static int irq_line; 64 65 struct sih { 66 char name[8]; 67 u8 module; /* module id */ 68 u8 control_offset; /* for SIH_CTRL */ 69 bool set_cor; 70 71 u8 bits; /* valid in isr/imr */ 72 u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */ 73 74 u8 edr_offset; 75 u8 bytes_edr; /* bytelen of EDR */ 76 77 /* SIR ignored -- set interrupt, for testing only */ 78 struct irq_data { 79 u8 isr_offset; 80 u8 imr_offset; 81 } mask[2]; 82 /* + 2 bytes padding */ 83 }; 84 85 #define SIH_INITIALIZER(modname, nbits) \ 86 .module = TWL4030_MODULE_ ## modname, \ 87 .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \ 88 .bits = nbits, \ 89 .bytes_ixr = DIV_ROUND_UP(nbits, 8), \ 90 .edr_offset = TWL4030_ ## modname ## _EDR, \ 91 .bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \ 92 .mask = { { \ 93 .isr_offset = TWL4030_ ## modname ## _ISR1, \ 94 .imr_offset = TWL4030_ ## modname ## _IMR1, \ 95 }, \ 96 { \ 97 .isr_offset = TWL4030_ ## modname ## _ISR2, \ 98 .imr_offset = TWL4030_ ## modname ## _IMR2, \ 99 }, }, 100 101 /* register naming policies are inconsistent ... */ 102 #define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1 103 #define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD 104 #define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT 105 106 107 /* Order in this table matches order in PIH_ISR. That is, 108 * BIT(n) in PIH_ISR is sih_modules[n]. 109 */ 110 static const struct sih sih_modules[6] = { 111 [0] = { 112 .name = "gpio", 113 .module = TWL4030_MODULE_GPIO, 114 .control_offset = REG_GPIO_SIH_CTRL, 115 .set_cor = true, 116 .bits = TWL4030_GPIO_MAX, 117 .bytes_ixr = 3, 118 /* Note: *all* of these IRQs default to no-trigger */ 119 .edr_offset = REG_GPIO_EDR1, 120 .bytes_edr = 5, 121 .mask = { { 122 .isr_offset = REG_GPIO_ISR1A, 123 .imr_offset = REG_GPIO_IMR1A, 124 }, { 125 .isr_offset = REG_GPIO_ISR1B, 126 .imr_offset = REG_GPIO_IMR1B, 127 }, }, 128 }, 129 [1] = { 130 .name = "keypad", 131 .set_cor = true, 132 SIH_INITIALIZER(KEYPAD_KEYP, 4) 133 }, 134 [2] = { 135 .name = "bci", 136 .module = TWL4030_MODULE_INTERRUPTS, 137 .control_offset = TWL4030_INTERRUPTS_BCISIHCTRL, 138 .bits = 12, 139 .bytes_ixr = 2, 140 .edr_offset = TWL4030_INTERRUPTS_BCIEDR1, 141 /* Note: most of these IRQs default to no-trigger */ 142 .bytes_edr = 3, 143 .mask = { { 144 .isr_offset = TWL4030_INTERRUPTS_BCIISR1A, 145 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1A, 146 }, { 147 .isr_offset = TWL4030_INTERRUPTS_BCIISR1B, 148 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1B, 149 }, }, 150 }, 151 [3] = { 152 .name = "madc", 153 SIH_INITIALIZER(MADC, 4) 154 }, 155 [4] = { 156 /* USB doesn't use the same SIH organization */ 157 .name = "usb", 158 }, 159 [5] = { 160 .name = "power", 161 .set_cor = true, 162 SIH_INITIALIZER(INT_PWR, 8) 163 }, 164 /* there are no SIH modules #6 or #7 ... */ 165 }; 166 167 #undef TWL4030_MODULE_KEYPAD_KEYP 168 #undef TWL4030_MODULE_INT_PWR 169 #undef TWL4030_INT_PWR_EDR 170 171 /*----------------------------------------------------------------------*/ 172 173 static unsigned twl4030_irq_base; 174 175 static struct completion irq_event; 176 177 /* 178 * This thread processes interrupts reported by the Primary Interrupt Handler. 179 */ 180 static int twl4030_irq_thread(void *data) 181 { 182 long irq = (long)data; 183 static unsigned i2c_errors; 184 static const unsigned max_i2c_errors = 100; 185 186 187 current->flags |= PF_NOFREEZE; 188 189 while (!kthread_should_stop()) { 190 int ret; 191 int module_irq; 192 u8 pih_isr; 193 194 /* Wait for IRQ, then read PIH irq status (also blocking) */ 195 wait_for_completion_interruptible(&irq_event); 196 197 ret = twl4030_i2c_read_u8(TWL4030_MODULE_PIH, &pih_isr, 198 REG_PIH_ISR_P1); 199 if (ret) { 200 pr_warning("twl4030: I2C error %d reading PIH ISR\n", 201 ret); 202 if (++i2c_errors >= max_i2c_errors) { 203 printk(KERN_ERR "Maximum I2C error count" 204 " exceeded. Terminating %s.\n", 205 __func__); 206 break; 207 } 208 complete(&irq_event); 209 continue; 210 } 211 212 /* these handlers deal with the relevant SIH irq status */ 213 local_irq_disable(); 214 for (module_irq = twl4030_irq_base; 215 pih_isr; 216 pih_isr >>= 1, module_irq++) { 217 if (pih_isr & 0x1) { 218 struct irq_desc *d = irq_to_desc(module_irq); 219 220 if (!d) { 221 pr_err("twl4030: Invalid SIH IRQ: %d\n", 222 module_irq); 223 return -EINVAL; 224 } 225 226 /* These can't be masked ... always warn 227 * if we get any surprises. 228 */ 229 if (d->status & IRQ_DISABLED) 230 note_interrupt(module_irq, d, 231 IRQ_NONE); 232 else 233 d->handle_irq(module_irq, d); 234 } 235 } 236 local_irq_enable(); 237 238 enable_irq(irq); 239 } 240 241 return 0; 242 } 243 244 /* 245 * handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt. 246 * This is a chained interrupt, so there is no desc->action method for it. 247 * Now we need to query the interrupt controller in the twl4030 to determine 248 * which module is generating the interrupt request. However, we can't do i2c 249 * transactions in interrupt context, so we must defer that work to a kernel 250 * thread. All we do here is acknowledge and mask the interrupt and wakeup 251 * the kernel thread. 252 */ 253 static irqreturn_t handle_twl4030_pih(int irq, void *devid) 254 { 255 /* Acknowledge, clear *AND* mask the interrupt... */ 256 disable_irq_nosync(irq); 257 complete(devid); 258 return IRQ_HANDLED; 259 } 260 /*----------------------------------------------------------------------*/ 261 262 /* 263 * twl4030_init_sih_modules() ... start from a known state where no 264 * IRQs will be coming in, and where we can quickly enable them then 265 * handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL. 266 * 267 * NOTE: we don't touch EDR registers here; they stay with hardware 268 * defaults or whatever the last value was. Note that when both EDR 269 * bits for an IRQ are clear, that's as if its IMR bit is set... 270 */ 271 static int twl4030_init_sih_modules(unsigned line) 272 { 273 const struct sih *sih; 274 u8 buf[4]; 275 int i; 276 int status; 277 278 /* line 0 == int1_n signal; line 1 == int2_n signal */ 279 if (line > 1) 280 return -EINVAL; 281 282 irq_line = line; 283 284 /* disable all interrupts on our line */ 285 memset(buf, 0xff, sizeof buf); 286 sih = sih_modules; 287 for (i = 0; i < ARRAY_SIZE(sih_modules); i++, sih++) { 288 289 /* skip USB -- it's funky */ 290 if (!sih->bytes_ixr) 291 continue; 292 293 status = twl4030_i2c_write(sih->module, buf, 294 sih->mask[line].imr_offset, sih->bytes_ixr); 295 if (status < 0) 296 pr_err("twl4030: err %d initializing %s %s\n", 297 status, sih->name, "IMR"); 298 299 /* Maybe disable "exclusive" mode; buffer second pending irq; 300 * set Clear-On-Read (COR) bit. 301 * 302 * NOTE that sometimes COR polarity is documented as being 303 * inverted: for MADC and BCI, COR=1 means "clear on write". 304 * And for PWR_INT it's not documented... 305 */ 306 if (sih->set_cor) { 307 status = twl4030_i2c_write_u8(sih->module, 308 TWL4030_SIH_CTRL_COR_MASK, 309 sih->control_offset); 310 if (status < 0) 311 pr_err("twl4030: err %d initializing %s %s\n", 312 status, sih->name, "SIH_CTRL"); 313 } 314 } 315 316 sih = sih_modules; 317 for (i = 0; i < ARRAY_SIZE(sih_modules); i++, sih++) { 318 u8 rxbuf[4]; 319 int j; 320 321 /* skip USB */ 322 if (!sih->bytes_ixr) 323 continue; 324 325 /* Clear pending interrupt status. Either the read was 326 * enough, or we need to write those bits. Repeat, in 327 * case an IRQ is pending (PENDDIS=0) ... that's not 328 * uncommon with PWR_INT.PWRON. 329 */ 330 for (j = 0; j < 2; j++) { 331 status = twl4030_i2c_read(sih->module, rxbuf, 332 sih->mask[line].isr_offset, sih->bytes_ixr); 333 if (status < 0) 334 pr_err("twl4030: err %d initializing %s %s\n", 335 status, sih->name, "ISR"); 336 337 if (!sih->set_cor) 338 status = twl4030_i2c_write(sih->module, buf, 339 sih->mask[line].isr_offset, 340 sih->bytes_ixr); 341 /* else COR=1 means read sufficed. 342 * (for most SIH modules...) 343 */ 344 } 345 } 346 347 return 0; 348 } 349 350 static inline void activate_irq(int irq) 351 { 352 #ifdef CONFIG_ARM 353 /* ARM requires an extra step to clear IRQ_NOREQUEST, which it 354 * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE. 355 */ 356 set_irq_flags(irq, IRQF_VALID); 357 #else 358 /* same effect on other architectures */ 359 set_irq_noprobe(irq); 360 #endif 361 } 362 363 /*----------------------------------------------------------------------*/ 364 365 static DEFINE_SPINLOCK(sih_agent_lock); 366 367 static struct workqueue_struct *wq; 368 369 struct sih_agent { 370 int irq_base; 371 const struct sih *sih; 372 373 u32 imr; 374 bool imr_change_pending; 375 struct work_struct mask_work; 376 377 u32 edge_change; 378 struct work_struct edge_work; 379 }; 380 381 static void twl4030_sih_do_mask(struct work_struct *work) 382 { 383 struct sih_agent *agent; 384 const struct sih *sih; 385 union { 386 u8 bytes[4]; 387 u32 word; 388 } imr; 389 int status; 390 391 agent = container_of(work, struct sih_agent, mask_work); 392 393 /* see what work we have */ 394 spin_lock_irq(&sih_agent_lock); 395 if (agent->imr_change_pending) { 396 sih = agent->sih; 397 /* byte[0] gets overwritten as we write ... */ 398 imr.word = cpu_to_le32(agent->imr << 8); 399 agent->imr_change_pending = false; 400 } else 401 sih = NULL; 402 spin_unlock_irq(&sih_agent_lock); 403 if (!sih) 404 return; 405 406 /* write the whole mask ... simpler than subsetting it */ 407 status = twl4030_i2c_write(sih->module, imr.bytes, 408 sih->mask[irq_line].imr_offset, sih->bytes_ixr); 409 if (status) 410 pr_err("twl4030: %s, %s --> %d\n", __func__, 411 "write", status); 412 } 413 414 static void twl4030_sih_do_edge(struct work_struct *work) 415 { 416 struct sih_agent *agent; 417 const struct sih *sih; 418 u8 bytes[6]; 419 u32 edge_change; 420 int status; 421 422 agent = container_of(work, struct sih_agent, edge_work); 423 424 /* see what work we have */ 425 spin_lock_irq(&sih_agent_lock); 426 edge_change = agent->edge_change; 427 agent->edge_change = 0; 428 sih = edge_change ? agent->sih : NULL; 429 spin_unlock_irq(&sih_agent_lock); 430 if (!sih) 431 return; 432 433 /* Read, reserving first byte for write scratch. Yes, this 434 * could be cached for some speedup ... but be careful about 435 * any processor on the other IRQ line, EDR registers are 436 * shared. 437 */ 438 status = twl4030_i2c_read(sih->module, bytes + 1, 439 sih->edr_offset, sih->bytes_edr); 440 if (status) { 441 pr_err("twl4030: %s, %s --> %d\n", __func__, 442 "read", status); 443 return; 444 } 445 446 /* Modify only the bits we know must change */ 447 while (edge_change) { 448 int i = fls(edge_change) - 1; 449 struct irq_desc *d = irq_to_desc(i + agent->irq_base); 450 int byte = 1 + (i >> 2); 451 int off = (i & 0x3) * 2; 452 453 if (!d) { 454 pr_err("twl4030: Invalid IRQ: %d\n", 455 i + agent->irq_base); 456 return; 457 } 458 459 bytes[byte] &= ~(0x03 << off); 460 461 spin_lock_irq(&d->lock); 462 if (d->status & IRQ_TYPE_EDGE_RISING) 463 bytes[byte] |= BIT(off + 1); 464 if (d->status & IRQ_TYPE_EDGE_FALLING) 465 bytes[byte] |= BIT(off + 0); 466 spin_unlock_irq(&d->lock); 467 468 edge_change &= ~BIT(i); 469 } 470 471 /* Write */ 472 status = twl4030_i2c_write(sih->module, bytes, 473 sih->edr_offset, sih->bytes_edr); 474 if (status) 475 pr_err("twl4030: %s, %s --> %d\n", __func__, 476 "write", status); 477 } 478 479 /*----------------------------------------------------------------------*/ 480 481 /* 482 * All irq_chip methods get issued from code holding irq_desc[irq].lock, 483 * which can't perform the underlying I2C operations (because they sleep). 484 * So we must hand them off to a thread (workqueue) and cope with asynch 485 * completion, potentially including some re-ordering, of these requests. 486 */ 487 488 static void twl4030_sih_mask(unsigned irq) 489 { 490 struct sih_agent *sih = get_irq_chip_data(irq); 491 unsigned long flags; 492 493 spin_lock_irqsave(&sih_agent_lock, flags); 494 sih->imr |= BIT(irq - sih->irq_base); 495 sih->imr_change_pending = true; 496 queue_work(wq, &sih->mask_work); 497 spin_unlock_irqrestore(&sih_agent_lock, flags); 498 } 499 500 static void twl4030_sih_unmask(unsigned irq) 501 { 502 struct sih_agent *sih = get_irq_chip_data(irq); 503 unsigned long flags; 504 505 spin_lock_irqsave(&sih_agent_lock, flags); 506 sih->imr &= ~BIT(irq - sih->irq_base); 507 sih->imr_change_pending = true; 508 queue_work(wq, &sih->mask_work); 509 spin_unlock_irqrestore(&sih_agent_lock, flags); 510 } 511 512 static int twl4030_sih_set_type(unsigned irq, unsigned trigger) 513 { 514 struct sih_agent *sih = get_irq_chip_data(irq); 515 struct irq_desc *desc = irq_to_desc(irq); 516 unsigned long flags; 517 518 if (!desc) { 519 pr_err("twl4030: Invalid IRQ: %d\n", irq); 520 return -EINVAL; 521 } 522 523 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 524 return -EINVAL; 525 526 spin_lock_irqsave(&sih_agent_lock, flags); 527 if ((desc->status & IRQ_TYPE_SENSE_MASK) != trigger) { 528 desc->status &= ~IRQ_TYPE_SENSE_MASK; 529 desc->status |= trigger; 530 sih->edge_change |= BIT(irq - sih->irq_base); 531 queue_work(wq, &sih->edge_work); 532 } 533 spin_unlock_irqrestore(&sih_agent_lock, flags); 534 return 0; 535 } 536 537 static struct irq_chip twl4030_sih_irq_chip = { 538 .name = "twl4030", 539 .mask = twl4030_sih_mask, 540 .unmask = twl4030_sih_unmask, 541 .set_type = twl4030_sih_set_type, 542 }; 543 544 /*----------------------------------------------------------------------*/ 545 546 static inline int sih_read_isr(const struct sih *sih) 547 { 548 int status; 549 union { 550 u8 bytes[4]; 551 u32 word; 552 } isr; 553 554 /* FIXME need retry-on-error ... */ 555 556 isr.word = 0; 557 status = twl4030_i2c_read(sih->module, isr.bytes, 558 sih->mask[irq_line].isr_offset, sih->bytes_ixr); 559 560 return (status < 0) ? status : le32_to_cpu(isr.word); 561 } 562 563 /* 564 * Generic handler for SIH interrupts ... we "know" this is called 565 * in task context, with IRQs enabled. 566 */ 567 static void handle_twl4030_sih(unsigned irq, struct irq_desc *desc) 568 { 569 struct sih_agent *agent = get_irq_data(irq); 570 const struct sih *sih = agent->sih; 571 int isr; 572 573 /* reading ISR acks the IRQs, using clear-on-read mode */ 574 local_irq_enable(); 575 isr = sih_read_isr(sih); 576 local_irq_disable(); 577 578 if (isr < 0) { 579 pr_err("twl4030: %s SIH, read ISR error %d\n", 580 sih->name, isr); 581 /* REVISIT: recover; eventually mask it all, etc */ 582 return; 583 } 584 585 while (isr) { 586 irq = fls(isr); 587 irq--; 588 isr &= ~BIT(irq); 589 590 if (irq < sih->bits) 591 generic_handle_irq(agent->irq_base + irq); 592 else 593 pr_err("twl4030: %s SIH, invalid ISR bit %d\n", 594 sih->name, irq); 595 } 596 } 597 598 static unsigned twl4030_irq_next; 599 600 /* returns the first IRQ used by this SIH bank, 601 * or negative errno 602 */ 603 int twl4030_sih_setup(int module) 604 { 605 int sih_mod; 606 const struct sih *sih = NULL; 607 struct sih_agent *agent; 608 int i, irq; 609 int status = -EINVAL; 610 unsigned irq_base = twl4030_irq_next; 611 612 /* only support modules with standard clear-on-read for now */ 613 for (sih_mod = 0, sih = sih_modules; 614 sih_mod < ARRAY_SIZE(sih_modules); 615 sih_mod++, sih++) { 616 if (sih->module == module && sih->set_cor) { 617 if (!WARN((irq_base + sih->bits) > NR_IRQS, 618 "irq %d for %s too big\n", 619 irq_base + sih->bits, 620 sih->name)) 621 status = 0; 622 break; 623 } 624 } 625 if (status < 0) 626 return status; 627 628 agent = kzalloc(sizeof *agent, GFP_KERNEL); 629 if (!agent) 630 return -ENOMEM; 631 632 status = 0; 633 634 agent->irq_base = irq_base; 635 agent->sih = sih; 636 agent->imr = ~0; 637 INIT_WORK(&agent->mask_work, twl4030_sih_do_mask); 638 INIT_WORK(&agent->edge_work, twl4030_sih_do_edge); 639 640 for (i = 0; i < sih->bits; i++) { 641 irq = irq_base + i; 642 643 set_irq_chip_and_handler(irq, &twl4030_sih_irq_chip, 644 handle_edge_irq); 645 set_irq_chip_data(irq, agent); 646 activate_irq(irq); 647 } 648 649 status = irq_base; 650 twl4030_irq_next += i; 651 652 /* replace generic PIH handler (handle_simple_irq) */ 653 irq = sih_mod + twl4030_irq_base; 654 set_irq_data(irq, agent); 655 set_irq_chained_handler(irq, handle_twl4030_sih); 656 657 pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", sih->name, 658 irq, irq_base, twl4030_irq_next - 1); 659 660 return status; 661 } 662 663 /* FIXME need a call to reverse twl4030_sih_setup() ... */ 664 665 666 /*----------------------------------------------------------------------*/ 667 668 /* FIXME pass in which interrupt line we'll use ... */ 669 #define twl_irq_line 0 670 671 int twl_init_irq(int irq_num, unsigned irq_base, unsigned irq_end) 672 { 673 static struct irq_chip twl4030_irq_chip; 674 675 int status; 676 int i; 677 struct task_struct *task; 678 679 /* 680 * Mask and clear all TWL4030 interrupts since initially we do 681 * not have any TWL4030 module interrupt handlers present 682 */ 683 status = twl4030_init_sih_modules(twl_irq_line); 684 if (status < 0) 685 return status; 686 687 wq = create_singlethread_workqueue("twl4030-irqchip"); 688 if (!wq) { 689 pr_err("twl4030: workqueue FAIL\n"); 690 return -ESRCH; 691 } 692 693 twl4030_irq_base = irq_base; 694 695 /* install an irq handler for each of the SIH modules; 696 * clone dummy irq_chip since PIH can't *do* anything 697 */ 698 twl4030_irq_chip = dummy_irq_chip; 699 twl4030_irq_chip.name = "twl4030"; 700 701 twl4030_sih_irq_chip.ack = dummy_irq_chip.ack; 702 703 for (i = irq_base; i < irq_end; i++) { 704 set_irq_chip_and_handler(i, &twl4030_irq_chip, 705 handle_simple_irq); 706 activate_irq(i); 707 } 708 twl4030_irq_next = i; 709 pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", "PIH", 710 irq_num, irq_base, twl4030_irq_next - 1); 711 712 /* ... and the PWR_INT module ... */ 713 status = twl4030_sih_setup(TWL4030_MODULE_INT); 714 if (status < 0) { 715 pr_err("twl4030: sih_setup PWR INT --> %d\n", status); 716 goto fail; 717 } 718 719 /* install an irq handler to demultiplex the TWL4030 interrupt */ 720 721 722 init_completion(&irq_event); 723 724 status = request_irq(irq_num, handle_twl4030_pih, IRQF_DISABLED, 725 "TWL4030-PIH", &irq_event); 726 if (status < 0) { 727 pr_err("twl4030: could not claim irq%d: %d\n", irq_num, status); 728 goto fail_rqirq; 729 } 730 731 task = kthread_run(twl4030_irq_thread, (void *)irq_num, "twl4030-irq"); 732 if (IS_ERR(task)) { 733 pr_err("twl4030: could not create irq %d thread!\n", irq_num); 734 status = PTR_ERR(task); 735 goto fail_kthread; 736 } 737 return status; 738 fail_kthread: 739 free_irq(irq_num, &irq_event); 740 fail_rqirq: 741 /* clean up twl4030_sih_setup */ 742 fail: 743 for (i = irq_base; i < irq_end; i++) 744 set_irq_chip_and_handler(i, NULL, NULL); 745 destroy_workqueue(wq); 746 wq = NULL; 747 return status; 748 } 749 750 int twl_exit_irq(void) 751 { 752 /* FIXME undo twl_init_irq() */ 753 if (twl4030_irq_base) { 754 pr_err("twl4030: can't yet clean up IRQs?\n"); 755 return -ENOSYS; 756 } 757 return 0; 758 } 759